1 /* Copyright 2022 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 /** 26 * @file vpe_hw_types.h 27 * @brief This is the file containing the API hardware structures for the VPE library. 28 */ 29 #pragma once 30 31 #include <stdint.h> 32 #include <stddef.h> 33 #include <stdbool.h> 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 /*********************************************************************** 40 * Note: do *not* add any types which are *not* used for HW programming. 41 * this will ensure separation of Logic layer from HW layer 42 ***********************************************************************/ 43 44 /** @union large_integer 45 * @brief 64 bits integers, either with one 64 bit integer or two 32 bits. Mainly used to store 46 * memory addresses. 47 */ 48 union large_integer { 49 struct { 50 uint32_t low_part; 51 int32_t high_part; 52 }; 53 54 struct { 55 uint32_t low_part; /**< Bits [0:31] of the integer */ 56 int32_t high_part; /**< Bits [32:63] of the integer */ 57 } u; /**< Structure of one unsigend integer for [0:31] bits of the integer and one signed 58 * integer for [32:63]. 59 */ 60 61 int64_t quad_part; /**< One 64 bits integer. */ 62 }; 63 64 /** @def PHYSICAL_ADDRESS_LOC 65 * 66 * @brief Large integer to store memory address 67 */ 68 #define PHYSICAL_ADDRESS_LOC union large_integer 69 70 /** @enum vpe_plane_addr_type 71 * @brief Plane address types 72 */ 73 enum vpe_plane_addr_type { 74 VPE_PLN_ADDR_TYPE_GRAPHICS = 0, /**< For RGB planes */ 75 VPE_PLN_ADDR_TYPE_VIDEO_PROGRESSIVE, /**< For YCbCr planes */ 76 }; 77 78 /** @struct vpe_plane_address 79 * 80 * @brief The width and height of the surface 81 */ 82 struct vpe_plane_address { 83 enum vpe_plane_addr_type type; /**< Type of the plane address */ 84 bool tmz_surface; /**< Boolean to determine if the surface is allocated from tmz */ 85 union { 86 struct { 87 PHYSICAL_ADDRESS_LOC addr; 88 PHYSICAL_ADDRESS_LOC meta_addr; 89 union large_integer dcc_const_color; 90 } grph; /**< Only used for RGB planes. Struct of two \ref PHYSICAL_ADDRESS_LOC to 91 * store address and meta address, and one \ref large_integer to store 92 * dcc constant color. 93 */ 94 95 struct { 96 PHYSICAL_ADDRESS_LOC luma_addr; 97 PHYSICAL_ADDRESS_LOC luma_meta_addr; 98 union large_integer luma_dcc_const_color; 99 100 PHYSICAL_ADDRESS_LOC chroma_addr; 101 PHYSICAL_ADDRESS_LOC chroma_meta_addr; 102 union large_integer chroma_dcc_const_color; 103 } video_progressive; /**< Only used for YUV planes. Struct of four \ref 104 * PHYSICAL_ADDRESS_LOC to store address and meta addresses of both 105 * luma and chroma planes, and two \ref large_integer to store dcc 106 * constant color for each plane. For packed YUV formats, the chroma 107 * plane addresses should be blank. 108 */ 109 }; 110 }; 111 112 /** @enum vpe_rotation_angle 113 * @brief Plane clockwise rotation angle 114 */ 115 enum vpe_rotation_angle { 116 VPE_ROTATION_ANGLE_0 = 0, /**< No rotation */ 117 VPE_ROTATION_ANGLE_90, /**< 90 degrees clockwise rotation */ 118 VPE_ROTATION_ANGLE_180, /**< 180 degrees clockwise rotation */ 119 VPE_ROTATION_ANGLE_270, /**< 270 degrees clockwise rotation */ 120 VPE_ROTATION_ANGLE_COUNT 121 }; 122 123 /** @enum vpe_mirror 124 * @brief Mirroring type 125 */ 126 enum vpe_mirror { 127 VPE_MIRROR_NONE, /**< No mirroring */ 128 VPE_MIRROR_HORIZONTAL, /**< Horizontal mirroring */ 129 VPE_MIRROR_VERTICAL /**< Vertical mirroring */ 130 }; 131 132 /** @enum vpe_scan_direction 133 * @brief Plane memory scan pattern 134 */ 135 enum vpe_scan_direction { 136 VPE_SCAN_PATTERN_0_DEGREE = 137 0, /**< Left to Right, Top to Bottom. 0 Degree Rotation and no Mirroring */ 138 VPE_SCAN_PATTERN_90_DEGREE = 139 1, /**< Bottom to Top, Left to Right. 90 Degree Rotation and no Mirroring */ 140 VPE_SCAN_PATTERN_180_DEGREE = 141 2, /**< Right to Left, Bottom to Top. 180 Degree Rotation and no Mirroring */ 142 VPE_SCAN_PATTERN_270_DEGREE = 143 3, /**< Top to Bottom, Right to Left. 270 Degree Rotation and no Mirroring */ 144 }; 145 146 /** @struct vpe_size 147 * @brief The width and height of the surface 148 */ 149 struct vpe_size { 150 uint32_t width; /**< Width of the surface in pixels */ 151 uint32_t height; /**< Height of the surface in pixels */ 152 }; 153 154 /** @struct vpe_rect 155 * @brief A rectangle used in vpe is specified by the position of the left most top corner of the 156 * rectangle and the width and height of the rectangle. 157 */ 158 struct vpe_rect { 159 int32_t x; /**< The x coordinate of the left most top corner */ 160 int32_t y; /**< The y coordinate of the left most top corner */ 161 uint32_t width; /**< Width of the surface in pixels */ 162 uint32_t height; /**< Height of the rectangle in pixels */ 163 }; 164 165 /** @struct vpe_plane_size 166 * @brief Size and pitch alignment for vpe surface plane(s) 167 */ 168 struct vpe_plane_size { 169 struct vpe_rect surface_size; /**< Plane rectangle */ 170 struct vpe_rect chroma_size; /**< Chroma plane rectangle for semi-planar YUV formats */ 171 uint32_t surface_pitch; /**< Horizintal pitch alignment of the plane in pixels */ 172 uint32_t chroma_pitch; /**< Horizintal pitch alignment of the chroma plane for 173 semi-planar YUV formats in pixels */ 174 uint32_t surface_aligned_height; /**< Vertical alignment of the plane in pixels */ 175 uint32_t chrome_aligned_height; /**< Vertical alignment of the chroma plane for semi-planar 176 YUV formats in pixels */ 177 }; 178 179 /** @struct vpe_plane_dcc_param 180 * @brief Not used 181 */ 182 struct vpe_plane_dcc_param { 183 bool enable; 184 185 uint32_t meta_pitch; 186 bool independent_64b_blks; 187 uint8_t dcc_ind_blk; 188 189 uint32_t meta_pitch_c; 190 bool independent_64b_blks_c; 191 uint8_t dcc_ind_blk_c; 192 }; 193 194 /** @enum vpe_surface_pixel_format 195 * @brief Surface formats 196 * 197 * The order of components are MSB to LSB. For example, for VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB1555, 198 * the most significant bit is reserved for alpha and the 5 least significant bits are reserved for 199 * the blue channel, i.e. 200 * 201 * <pre> 202 * MSB _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ LSB 203 * A R R R R R G G G G G B B B B B 204 * </pre> 205 */ 206 enum vpe_surface_pixel_format { 207 VPE_SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0, 208 /*16 bpp*/ 209 VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB1555, 210 /*16 bpp*/ 211 VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB565, 212 /*32 bpp*/ 213 VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB8888, 214 /*32 bpp swaped*/ 215 VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888, 216 /*32 bpp alpha rotated*/ 217 VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888, 218 /*32 bpp swaped & alpha rotated*/ 219 VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888, 220 221 VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010, 222 /*swaped*/ 223 VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010, 224 /*alpha rotated*/ 225 VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102, 226 /*swaped & alpha rotated*/ 227 VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102, 228 229 /*64 bpp */ 230 VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616, 231 /*float*/ 232 VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F, 233 /*swaped & float*/ 234 VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F, 235 /*alpha rotated*/ 236 VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F, 237 /*swaped & alpha rotated*/ 238 VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F, 239 240 VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888, 241 /*swaped*/ 242 VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888, 243 /*rotated*/ 244 VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888, 245 /*swaped & rotated*/ 246 VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888, 247 /*grow graphics here if necessary */ 248 VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX, 249 VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX, 250 VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT, 251 VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT, 252 VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE, 253 VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA, 254 VPE_SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, 255 VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr = VPE_SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, 256 VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb, 257 VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr, 258 VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb, 259 VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_16bpc_YCrCb, 260 VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_16bpc_YCbCr, 261 VPE_SURFACE_PIXEL_FORMAT_SUBSAMPLE_END = VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_16bpc_YCbCr, 262 VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010, 263 VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102, 264 VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888, 265 VPE_SURFACE_PIXEL_FORMAT_VIDEO_YCrCbA8888, 266 VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb8888, 267 VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA8888, 268 VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888, //seems to be dummy, not part of surface pixel register values 269 VPE_SURFACE_PIXEL_FORMAT_VIDEO_END = VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888, 270 VPE_SURFACE_PIXEL_FORMAT_INVALID 271 272 /*grow 444 video here if necessary */ 273 }; 274 275 /** @enum vpe_swizzle_mode_values 276 * @brief Surface swizzle modes 277 */ 278 enum vpe_swizzle_mode_values { 279 VPE_SW_LINEAR = 0, 280 VPE_SW_256B_S = 1, 281 VPE_SW_256B_D = 2, 282 VPE_SW_256B_R = 3, 283 VPE_SW_4KB_Z = 4, 284 VPE_SW_4KB_S = 5, 285 VPE_SW_4KB_D = 6, 286 VPE_SW_4KB_R = 7, 287 VPE_SW_64KB_Z = 8, 288 VPE_SW_64KB_S = 9, 289 VPE_SW_64KB_D = 10, 290 VPE_SW_64KB_R = 11, 291 VPE_SW_VAR_Z = 12, 292 VPE_SW_VAR_S = 13, 293 VPE_SW_VAR_D = 14, 294 VPE_SW_VAR_R = 15, 295 VPE_SW_64KB_Z_T = 16, 296 VPE_SW_64KB_S_T = 17, 297 VPE_SW_64KB_D_T = 18, 298 VPE_SW_64KB_R_T = 19, 299 VPE_SW_4KB_Z_X = 20, 300 VPE_SW_4KB_S_X = 21, 301 VPE_SW_4KB_D_X = 22, 302 VPE_SW_4KB_R_X = 23, 303 VPE_SW_64KB_Z_X = 24, 304 VPE_SW_64KB_S_X = 25, 305 VPE_SW_64KB_D_X = 26, 306 VPE_SW_64KB_R_X = 27, 307 VPE_SW_VAR_Z_X = 28, 308 VPE_SW_VAR_S_X = 29, 309 VPE_SW_VAR_D_X = 30, 310 VPE_SW_VAR_R_X = 31, 311 VPE_SW_MAX = 32, 312 VPE_SW_UNKNOWN = VPE_SW_MAX 313 }; 314 315 /** @struct vpe_scaling_taps 316 * @brief Number of taps used for scaling 317 * 318 * If the number of taps are set to 0, VPElib internally chooses the best tap based on the scaling 319 * ratio. 320 */ 321 struct vpe_scaling_taps { 322 uint32_t v_taps; /**< Number of vertical taps */ 323 uint32_t h_taps; /**< Number of horizontal taps */ 324 uint32_t v_taps_c; /**< Number of vertical taps for chroma plane */ 325 uint32_t h_taps_c; /**< Number of horizontal taps for chroma plane */ 326 }; 327 328 #ifdef __cplusplus 329 } 330 #endif 331