1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #ifndef SOC_MEDIATEK_PMIC_WRAP_COMMON_H
4 #define SOC_MEDIATEK_PMIC_WRAP_COMMON_H
5
6 #include <console/console.h>
7
8 #define PWRAPTAG "[PWRAP] "
9 #define pwrap_err(fmt, arg ...) printk(BIOS_ERR, PWRAPTAG "ERROR,line=%d" fmt, \
10 __LINE__, ## arg)
11
12 /* external API */
13 s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check);
14 s32 pwrap_init(void);
pwrap_read(u16 addr,u16 * rdata)15 static inline s32 pwrap_read(u16 addr, u16 *rdata)
16 {
17 return pwrap_wacs2(0, addr, 0, rdata, 1);
18 }
19
pwrap_write(u16 addr,u16 wdata)20 static inline s32 pwrap_write(u16 addr, u16 wdata)
21 {
22 return pwrap_wacs2(1, addr, wdata, 0, 1);
23 }
24
pwrap_read_field(u16 reg,u16 mask,u16 shift)25 static inline u16 pwrap_read_field(u16 reg, u16 mask, u16 shift)
26 {
27 u16 rdata;
28
29 pwrap_read(reg, &rdata);
30 rdata &= (mask << shift);
31 rdata = (rdata >> shift);
32
33 return rdata;
34 }
35
pwrap_write_field(u16 reg,u16 val,u16 mask,u16 shift)36 static inline void pwrap_write_field(u16 reg, u16 val, u16 mask, u16 shift)
37 {
38 u16 old, new;
39
40 pwrap_read(reg, &old);
41 new = old & ~(mask << shift);
42 new |= (val << shift);
43 pwrap_write(reg, new);
44 }
45
46 /* internal API */
47 s32 pwrap_reset_spislv(void);
48
pwrap_read_nochk(u16 addr,u16 * rdata)49 static inline s32 pwrap_read_nochk(u16 addr, u16 *rdata)
50 {
51 return pwrap_wacs2(0, addr, 0, rdata, 0);
52 }
53
pwrap_write_nochk(u16 addr,u16 wdata)54 static inline s32 pwrap_write_nochk(u16 addr, u16 wdata)
55 {
56 return pwrap_wacs2(1, addr, wdata, 0, 0);
57 }
58
59 /* dewrapper default value */
60 enum {
61 DEFAULT_VALUE_READ_TEST = 0x5aa5,
62 WRITE_TEST_VALUE = 0xa55a
63 };
64
65 /* timeout setting */
66 enum {
67 TIMEOUT_READ_US = 255,
68 TIMEOUT_WAIT_IDLE_US = 255
69 };
70
71 /* manual command */
72 enum {
73 OP_WR = 0x1,
74 OP_CSH = 0x0,
75 OP_CSL = 0x1,
76 OP_OUTS = 0x8,
77 };
78
79 enum {
80 RDATA_WACS_RDATA_SHIFT = 0,
81 RDATA_WACS_FSM_SHIFT = 16,
82 RDATA_WACS_REQ_SHIFT = 19,
83 RDATA_SYNC_IDLE_SHIFT,
84 RDATA_INIT_DONE_V1_SHIFT,
85 RDATA_SYS_IDLE_V1_SHIFT,
86 };
87
88 enum {
89 RDATA_INIT_DONE_V2_SHIFT = 22, /* 8186 */
90 RDATA_SYS_IDLE_V2_SHIFT = 23, /* 8186 */
91 };
92
93 enum {
94 RDATA_WACS_RDATA_MASK = 0xffff,
95 RDATA_WACS_FSM_MASK = 0x7,
96 RDATA_WACS_REQ_MASK = 0x1,
97 RDATA_SYNC_IDLE_MASK = 0x1,
98 RDATA_INIT_DONE_MASK = 0x1,
99 RDATA_SYS_IDLE_MASK = 0x1,
100 };
101
102 /* WACS_FSM */
103 enum {
104 WACS_FSM_IDLE = 0x00,
105 WACS_FSM_REQ = 0x02,
106 WACS_FSM_WFDLE = 0x04, /* wait for dle, wait for read data done */
107 WACS_FSM_WFVLDCLR = 0x06, /* finish read data, wait for valid flag
108 * clearing */
109 WACS_INIT_DONE = 0x01,
110 WACS_SYNC_IDLE = 0x01,
111 WACS_SYNC_BUSY = 0x00
112 };
113
114 /* error information flag */
115 enum {
116 E_PWR_INVALID_ARG = 1,
117 E_PWR_INVALID_RW = 2,
118 E_PWR_INVALID_ADDR = 3,
119 E_PWR_INVALID_WDAT = 4,
120 E_PWR_INVALID_OP_MANUAL = 5,
121 E_PWR_NOT_IDLE_STATE = 6,
122 E_PWR_NOT_INIT_DONE = 7,
123 E_PWR_NOT_INIT_DONE_READ = 8,
124 E_PWR_WAIT_IDLE_TIMEOUT = 9,
125 E_PWR_WAIT_IDLE_TIMEOUT_READ = 10,
126 E_PWR_INIT_SIDLY_FAIL = 11,
127 E_PWR_RESET_TIMEOUT = 12,
128 E_PWR_TIMEOUT = 13,
129 E_PWR_INIT_RESET_SPI = 20,
130 E_PWR_INIT_SIDLY = 21,
131 E_PWR_INIT_REG_CLOCK = 22,
132 E_PWR_INIT_ENABLE_PMIC = 23,
133 E_PWR_INIT_DIO = 24,
134 E_PWR_INIT_CIPHER = 25,
135 E_PWR_INIT_WRITE_TEST = 26,
136 E_PWR_INIT_ENABLE_CRC = 27,
137 E_PWR_INIT_ENABLE_DEWRAP = 28,
138 E_PWR_INIT_ENABLE_EVENT = 29,
139 E_PWR_READ_TEST_FAIL = 30,
140 E_PWR_WRITE_TEST_FAIL = 31,
141 E_PWR_SWITCH_DIO = 32
142 };
143
144 typedef u32 (*loop_condition_fp)(u32);
145
wait_for_fsm_vldclr(u32 x)146 static inline u32 wait_for_fsm_vldclr(u32 x)
147 {
148 return ((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) !=
149 WACS_FSM_WFVLDCLR;
150 }
151
wait_for_sync(u32 x)152 static inline u32 wait_for_sync(u32 x)
153 {
154 return ((x >> RDATA_SYNC_IDLE_SHIFT) & RDATA_SYNC_IDLE_MASK) !=
155 WACS_SYNC_IDLE;
156 }
157
wait_for_idle_and_sync(u32 x)158 static inline u32 wait_for_idle_and_sync(u32 x)
159 {
160 return ((((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) !=
161 WACS_FSM_IDLE) || (((x >> RDATA_SYNC_IDLE_SHIFT) &
162 RDATA_SYNC_IDLE_MASK) != WACS_SYNC_IDLE));
163 }
164
wait_for_cipher_ready(u32 x)165 static inline u32 wait_for_cipher_ready(u32 x)
166 {
167 return x != 3;
168 }
169
170 u32 wait_for_state_idle(u32 timeout_us, void *wacs_register,
171 void *wacs_vldclr_register, u32 *read_reg);
172
173 u32 wait_for_state_ready(loop_condition_fp fp, u32 timeout_us,
174 void *wacs_register, u32 *read_reg);
175
176 #endif /* SOC_MEDIATEK_PMIC_WRAP_COMMON_H */
177