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Searched defs:zdn (Results 1 – 5 of 5) sorted by relevance

/external/vixl/src/aarch64/
Dsimulator-aarch64.cc3458 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in SimulateSVEBitwiseTernary() local
3495 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in SimulateSVEHalvingAddSub() local
3533 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in SimulateSVESaturatingArithmetic() local
3573 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in SimulateSVEIntArithPair() local
3603 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in Simulate_ZdnT_PgM_ZdnT_ZmT() local
3631 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in Simulate_ZdnT_PgM_ZdnT_const() local
3666 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in SimulateSVEExclusiveOrRotate() local
3681 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in Simulate_ZdnT_ZdnT_ZmT_const() local
10280 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in VisitSVEBitwiseShiftByImm_Predicated() local
10329 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in VisitSVEBitwiseShiftByVector_Predicated() local
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Dassembler-sve-aarch64.cc86 void Assembler::SVELogicalImmediate(const ZRegister& zdn, in SVELogicalImmediate()
168 void Assembler::SVEBitwiseShiftImmediatePred(const ZRegister& zdn, in SVEBitwiseShiftImmediatePred()
1403 void Assembler::fmad(const ZRegister& zdn, in fmad()
1448 void Assembler::fmsb(const ZRegister& zdn, in fmsb()
1463 void Assembler::fnmad(const ZRegister& zdn, in fnmad()
1508 void Assembler::fnmsb(const ZRegister& zdn, in fnmsb()
2034 void Assembler::decp(const ZRegister& zdn, const PRegister& pg) { in decp()
2059 void Assembler::incp(const ZRegister& zdn, const PRegister& pg) { in incp()
2099 void Assembler::sqdecp(const ZRegister& zdn, const PRegister& pg) { in sqdecp()
2138 void Assembler::sqincp(const ZRegister& zdn, const PRegister& pg) { in sqincp()
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Dmacro-assembler-aarch64.h4165 void Decp(const ZRegister& zdn, const PRegister& pg) { Decp(zdn, pg, zdn); } in Decp()
4510 void Fmad(const ZRegister& zdn, in Fmad()
4642 void Fmsb(const ZRegister& zdn, in Fmsb()
4890 void Incp(const ZRegister& zdn, const PRegister& pg) { Incp(zdn, pg, zdn); } in Incp()
4902 void Insr(const ZRegister& zdn, const Register& rm) { in Insr()
4907 void Insr(const ZRegister& zdn, const VRegister& vm) { in Insr()
5888 void Sqdecp(const ZRegister& zdn, const PRegister& pg) { in Sqdecp()
5977 void Sqincp(const ZRegister& zdn, const PRegister& pg) { in Sqincp()
6312 void Uqdecp(const ZRegister& zdn, const PRegister& pg) { in Uqdecp()
6376 void Uqincp(const ZRegister& zdn, const PRegister& pg) { in Uqincp()
Dmacro-assembler-sve-aarch64.cc944 void MacroAssembler::Insr(const ZRegister& zdn, IntegerOperand imm) { in Insr()
/external/vixl/test/aarch64/
Dtest-utils-aarch64.h669 const ZRegister& zdn, in InsrHelper()