| /external/arm-trusted-firmware/plat/arm/css/common/ |
| D | css_common.mk | 2 # Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
4 # SPDX-License-Identifier: BSD-3-Clause
8 # By default, SCP images are needed by CSS platforms.
14 PLAT_INCLUDES += -Iinclude/plat/arm/css/common/aarch64
30 drivers/arm/css/scp/css_pm_scpi.c \
38 drivers/arm/css/scp/css_pm_scmi.c
48 $(eval $(call TOOL_ADD_IMG,scp_bl2u,--scp-fwu-cfg,FWU_))
52 BL2U_SOURCES += drivers/arm/css/scp/css_sds.c \
55 BL2_SOURCES += drivers/arm/css/scp/css_sds.c \
59 drivers/arm/css/scp/css_bom_bootloader.c \
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| /external/trusty/arm-trusted-firmware/plat/arm/css/common/ |
| D | css_common.mk | 2 # Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
4 # SPDX-License-Identifier: BSD-3-Clause
8 # By default, SCP images are needed by CSS platforms.
14 PLAT_INCLUDES += -Iinclude/plat/arm/css/common/aarch64
30 drivers/arm/css/scp/css_pm_scpi.c \
39 drivers/arm/css/scp/css_pm_scmi.c
49 $(eval $(call TOOL_ADD_IMG,scp_bl2u,--scp-fwu-cfg,FWU_))
53 BL2U_SOURCES += drivers/arm/css/scp/css_sds.c \
56 BL2_SOURCES += drivers/arm/css/scp/css_sds.c \
60 drivers/arm/css/scp/css_bom_bootloader.c \
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|
| /external/trusty/arm-trusted-firmware/docs/plat/ |
| D | socionext-uniphier.rst | 4 Socionext UniPhier Armv8-A SoCs use Trusted Firmware-A (TF-A) as the secure
8 image from a non-volatile storage to the on-chip SRAM, and jumps over to it.
9 TF-A provides a special mode, BL2-AT-EL3, which enables BL2 to execute at EL3.
10 It is useful for platforms with non-TF-A boot ROM, like UniPhier. Here, a
14 `UniPhier BL`_. This loader runs in the on-chip SRAM, initializes the DRAM,
16 of TF-A run in DRAM.
24 the BL2 validity in a different way; BL2 is GZIP-compressed and appended to
31 ---------
35 This is hard-wired ROM, so never corrupted. It loads the UniPhier BL (with
36 compressed-BL2 appended) into the on-chip SRAM. If the SoC fuses are blown,
[all …]
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| /external/arm-trusted-firmware/docs/plat/ |
| D | socionext-uniphier.rst | 4 Socionext UniPhier Armv8-A SoCs use Trusted Firmware-A (TF-A) as the secure
8 image from a non-volatile storage to the on-chip SRAM, and jumps over to it.
9 TF-A provides a special mode, BL2-AT-EL3, which enables BL2 to execute at EL3.
10 It is useful for platforms with non-TF-A boot ROM, like UniPhier. Here, a
14 `UniPhier BL`_. This loader runs in the on-chip SRAM, initializes the DRAM,
16 of TF-A run in DRAM.
24 the BL2 validity in a different way; BL2 is GZIP-compressed and appended to
31 ---------
35 This is hard-wired ROM, so never corrupted. It loads the UniPhier BL (with
36 compressed-BL2 appended) into the on-chip SRAM. If the SoC fuses are blown,
[all …]
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| /external/arm-trusted-firmware/docs/plat/arm/tc/ |
| D | index.rst | 4 Some of the features of TC platform referenced in TF-A include:
6 - A `System Control Processor <https://github.com/ARM-software/SCP-firmware>`_
8 processors. The RAM firmware for SCP is included in the TF-A FIP and is
9 loaded by AP BL2 from FIP in flash to SRAM for copying by SCP (SCP has access
11 - GICv4
12 - Trusted Board Boot
13 - SCMI
14 - MHUv2
17 (TARGET_PLATFORM=1) platforms w.r.t to TF-A is the CPUs supported. TC0 has
23 -------------
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| /external/arm-trusted-firmware/plat/socionext/synquacer/ |
| D | sq_psci.c | 2 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
30 * SCP takes care of powering up parent power domains so we in sq_pwr_domain_on()
46 * Perform the common cluster specific operations i.e enable coherency in sq_pwr_domain_on_finisher_common()
60 /* Program the gic per-cpu distributor or re-distributor interface */ in sq_pwr_domain_on_finish()
63 /* Enable the gic cpu interface */ in sq_pwr_domain_on_finish()
87 * Ask the SCP to power down the appropriate components depending upon in sq_power_down_common()
151 /* Send the system reset request to the SCP */ in sq_system_reset()
155 ERROR("SQ System Reset: SCP error %u.\n", response); in sq_system_reset()
171 /* Enable PhysicalIRQ bit for NS world to wake the CPU */ in sq_cpu_standby()
|
| D | platform.mk | 2 # Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
4 # SPDX-License-Identifier: BSD-3-Clause
12 # Enable workarounds for selected Cortex-A53 erratas.
14 # Enable SCMI support
21 PLAT_INCLUDES := -I$(PLAT_PATH)/include \
22 -I$(PLAT_PATH)/drivers/scpi \
23 -I$(PLAT_PATH)/drivers/mhu \
24 -Idrivers/arm/css/scmi \
25 -Idrivers/arm/css/scmi/vendor
47 $(PLAT_PATH)/drivers/scp/sq_scp.c
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|
| /external/trusty/arm-trusted-firmware/docs/plat/arm/tc/ |
| D | index.rst | 4 Some of the features of TC platform referenced in TF-A include:
6 - A `System Control Processor <https://github.com/ARM-software/SCP-firmware>`_
8 processors. The RAM firmware for SCP is included in the TF-A FIP and is
9 loaded by AP BL2 from FIP in flash to SRAM for copying by SCP (SCP has access
11 - GICv4
12 - Trusted Board Boot
13 - SCMI
14 - MHUv2
16 The TF-A build is specified by the option `TARGET_PLATFORM` which represents
20 - TC0 has support for Cortex A510, Cortex A710 and Cortex X2. (Note TC0 is now deprecated)
[all …]
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| /external/arm-trusted-firmware/docs/plat/arm/ |
| D | arm-build-options.rst | 5 --------------------------
7 - ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
13 - ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
16 should match the frame used by the Non-Secure image (normally the Linux
19 - ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
27 - ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
37 - ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
38 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
40 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
43 - ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
[all …]
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| /external/trusty/arm-trusted-firmware/plat/socionext/synquacer/ |
| D | sq_psci.c | 2 * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
30 * SCP takes care of powering up parent power domains so we in sq_pwr_domain_on()
46 * Perform the common cluster specific operations i.e enable coherency in sq_pwr_domain_on_finisher_common()
60 /* Program the gic per-cpu distributor or re-distributor interface */ in sq_pwr_domain_on_finish()
63 /* Enable the gic cpu interface */ in sq_pwr_domain_on_finish()
87 * Ask the SCP to power down the appropriate components depending upon in sq_power_down_common()
155 /* Send the system reset request to the SCP */ in sq_system_reset()
159 ERROR("SQ System Reset: SCP error %u.\n", response); in sq_system_reset()
175 /* Enable PhysicalIRQ bit for NS world to wake the CPU */ in sq_cpu_standby()
|
| /external/trusty/arm-trusted-firmware/docs/plat/arm/ |
| D | arm-build-options.rst | 5 --------------------------
7 - ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
13 - ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
16 should match the frame used by the Non-Secure image (normally the Linux
19 - ``ARM_FW_CONFIG_LOAD_ENABLE``: Boolean option to enable the loading of
25 - ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
33 - ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
43 - ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
44 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
46 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
[all …]
|
| /external/curl/docs/cmdline-opts/ |
| D | compressed-ssh.md | 1 ---
3 SPDX-License-Identifier: curl
4 Long: compressed-ssh
5 Help: Enable SSH compression
6 Protocols: SCP SFTP
8 Category: scp ssh
10 See-also:
11 - compressed
13 - --compressed-ssh sftp://example.com/
14 ---
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|
| /external/arm-trusted-firmware/plat/allwinner/common/ |
| D | allwinner-common.mk | 2 # Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
4 # SPDX-License-Identifier: BSD-3-Clause
13 PLAT_INCLUDES := -Iinclude/plat/arm/common/aarch64 \
14 -I${AW_PLAT}/common/include \
15 -I${AW_PLAT}/${PLAT}/include
36 # is not enabled or SCP firmware is not loaded, fall back to a simpler native
39 # If SCP firmware will always be present (or absent), the unused implementation
67 # Do not enable SPE (not supported on ARM v8.0).
70 # Do not enable SVE (not supported on ARM v8.0).
73 # Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4.
[all …]
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| /external/trusty/arm-trusted-firmware/plat/brcm/board/stingray/src/ |
| D | scp_utils.c | 2 * Copyright (c) 2017-2020, Broadcom
4 * SPDX-License-Identifier: BSD-3-Clause
20 #include <scp.h>
84 * First check if SCP patch has already been loaded in plat_bcm_bl2_plat_handle_scp_bl2()
91 INFO("SCP Patch is already active.\n"); in plat_bcm_bl2_plat_handle_scp_bl2()
114 * MCU patch stamps critical points in REG9 (debug test-point) in plat_bcm_bl2_plat_handle_scp_bl2()
123 ret = download_scp_patch((void *)scp_bl2_image_info->image_base, in plat_bcm_bl2_plat_handle_scp_bl2()
124 scp_bl2_image_info->image_size); in plat_bcm_bl2_plat_handle_scp_bl2()
128 VERBOSE("SCP Patch loaded OK.\n"); in plat_bcm_bl2_plat_handle_scp_bl2()
134 ERROR("SCP Patch could not initialize; error %d\n", in plat_bcm_bl2_plat_handle_scp_bl2()
[all …]
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| D | brcm_pm_ops.c | 2 * Copyright (c) 2017 - 2020, Broadcom
4 * SPDX-License-Identifier: BSD-3-Clause
29 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
31 ((state)->pwr_domain_state[MPIDR_AFFLVL1])
32 #define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL2])
38 * On systems where participant CPUs are cache-coherent, we can use spinlocks
58 * SCP takes care of powering up parent power domains so we in brcm_pwr_domain_on()
85 * Perform the common cluster specific operations i.e enable coherency in brcm_pwr_domain_on_finish()
93 /* Program the gic per-cpu distributor or re-distributor interface */ in brcm_pwr_domain_on_finish()
96 /* Enable the gic cpu interface */ in brcm_pwr_domain_on_finish()
[all …]
|
| /external/arm-trusted-firmware/plat/brcm/board/stingray/src/ |
| D | scp_utils.c | 2 * Copyright (c) 2017-2020, Broadcom
4 * SPDX-License-Identifier: BSD-3-Clause
20 #include <scp.h>
84 * First check if SCP patch has already been loaded in plat_bcm_bl2_plat_handle_scp_bl2()
91 INFO("SCP Patch is already active.\n"); in plat_bcm_bl2_plat_handle_scp_bl2()
114 * MCU patch stamps critical points in REG9 (debug test-point) in plat_bcm_bl2_plat_handle_scp_bl2()
123 ret = download_scp_patch((void *)scp_bl2_image_info->image_base, in plat_bcm_bl2_plat_handle_scp_bl2()
124 scp_bl2_image_info->image_size); in plat_bcm_bl2_plat_handle_scp_bl2()
128 VERBOSE("SCP Patch loaded OK.\n"); in plat_bcm_bl2_plat_handle_scp_bl2()
134 ERROR("SCP Patch could not initialize; error %d\n", in plat_bcm_bl2_plat_handle_scp_bl2()
[all …]
|
| D | brcm_pm_ops.c | 2 * Copyright (c) 2017 - 2020, Broadcom
4 * SPDX-License-Identifier: BSD-3-Clause
29 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
31 ((state)->pwr_domain_state[MPIDR_AFFLVL1])
32 #define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL2])
38 * On systems where participant CPUs are cache-coherent, we can use spinlocks
58 * SCP takes care of powering up parent power domains so we in brcm_pwr_domain_on()
85 * Perform the common cluster specific operations i.e enable coherency in brcm_pwr_domain_on_finish()
93 /* Program the gic per-cpu distributor or re-distributor interface */ in brcm_pwr_domain_on_finish()
96 /* Enable the gic cpu interface */ in brcm_pwr_domain_on_finish()
[all …]
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| /external/arm-trusted-firmware/plat/arm/board/n1sdp/ |
| D | platform.mk | 2 # Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
4 # SPDX-License-Identifier: BSD-3-Clause
12 PLAT_INCLUDES := -I${N1SDP_BASE}/include
17 # GIC-600 configuration
41 FDT_SOURCES += fdts/${PLAT}-single-chip.dts \
42 fdts/${PLAT}-multi-chip.dts
44 # TF-A not required to load the SCP Images
61 # SCP during power management operations and for SCP RAM Firmware transfer.
67 # When building for systems with hardware-assisted coherency, there's no need to
71 # Enable the flag since N1SDP has a system level cache
|
| /external/coreboot/src/vendorcode/cavium/include/bdk/libbdk-arch/ |
| D | bdk-csrs-rst.h | 3 /* This file is auto-generated. Do not edit */
6 * Copyright (c) 2003-2017 Cavium Inc. (support@cavium.com). All rights
44 #include <bdk-minimal.h>
45 #include <libbdk-arch/bdk-csr.h>
76 * Enumerates the reasons for boot failure, returned to post-boot code
96 * RST Primary Boot-strap Method Enumeration
156 * RST MSI-X Vector Enumeration
157 * Enumerates the MSI-X interrupt vectors.
200 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
202 uint32_t trusted : 1; /**< [ 15: 15] This was a trusted-mode boot. */
[all …]
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| /external/curl/docs/libcurl/opts/ |
| D | CURLOPT_REDIR_PROTOCOLS_STR.md | 1 ---
3 SPDX-License-Identifier: curl
7 See-also:
8 - CURLINFO_SCHEME (3)
9 - CURLOPT_DEFAULT_PROTOCOL (3)
10 - CURLOPT_PROTOCOLS (3)
11 - CURLOPT_PROTOCOLS_STR (3)
12 - CURLOPT_REDIR_PROTOCOLS (3)
14 - HTTP
15 Added-in: 7.85.0
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|
| /external/trusty/arm-trusted-firmware/plat/allwinner/common/ |
| D | allwinner-common.mk | 2 # Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
4 # SPDX-License-Identifier: BSD-3-Clause
13 PLAT_INCLUDES := -Iinclude/plat/arm/common/aarch64 \
14 -I${AW_PLAT}/common/include \
15 -I${AW_PLAT}/${PLAT}/include
37 # is not enabled or SCP firmware is not loaded, fall back to a simpler native
40 # If SCP firmware will always be present (or absent), the unused implementation
89 # Do not enable SPE (not supported on ARM v8.0).
92 # Do not enable SVE (not supported on ARM v8.0).
95 # Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4.
[all …]
|
| /external/trusty/arm-trusted-firmware/plat/marvell/armada/a8k/common/mss/ |
| D | mss_bl2_setup.c | 4 * SPDX-License-Identifier: BSD-3-Clause
40 * - get the information about device id which is stored in CP0 registers
42 * - get the access to cp which is needed for loading fw for cp0/cp1
56 /* CCU window-0 should not be counted - it's already used */ in bl2_plat_mmap_init()
57 if (cfg_num > (MVEBU_CCU_MAX_WINS - 1)) { in bl2_plat_mmap_init()
59 return -1; in bl2_plat_mmap_init()
62 /* Enable required CCU windows in bl2_plat_mmap_init()
71 /* Enable required CCU windows */ in bl2_plat_mmap_init()
94 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
95 * Return 0 on success, -1 otherwise.
[all …]
|
| /external/arm-trusted-firmware/plat/marvell/armada/a8k/common/mss/ |
| D | mss_bl2_setup.c | 4 * SPDX-License-Identifier: BSD-3-Clause
40 * - get the information about device id which is stored in CP0 registers
42 * - get the access to cp which is needed for loading fw for cp0/cp1
56 /* CCU window-0 should not be counted - it's already used */ in bl2_plat_mmap_init()
57 if (cfg_num > (MVEBU_CCU_MAX_WINS - 1)) { in bl2_plat_mmap_init()
59 return -1; in bl2_plat_mmap_init()
62 /* Enable required CCU windows in bl2_plat_mmap_init()
71 /* Enable required CCU windows */ in bl2_plat_mmap_init()
94 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
95 * Return 0 on success, -1 otherwise.
[all …]
|
| /external/trusty/arm-trusted-firmware/plat/arm/board/n1sdp/ |
| D | platform.mk | 2 # Copyright (c) 2018-2023, Arm Limited. All rights reserved.
4 # SPDX-License-Identifier: BSD-3-Clause
12 PLAT_INCLUDES := -I${N1SDP_BASE}/include
21 # GIC-600 configuration
59 FDT_SOURCES += fdts/${PLAT}-single-chip.dts \
60 fdts/${PLAT}-multi-chip.dts \
70 $(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
72 $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
74 $(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
81 $(eval $(call TOOL_ADD_PAYLOAD,${N1SDP_TOS_FW_CONFIG},--tos-fw-config,${N1SDP_TOS_FW_CONFIG}))
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| /external/arm-trusted-firmware/plat/arm/board/juno/ |
| D | platform.mk | 2 # Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
4 # SPDX-License-Identifier: BSD-3-Clause
29 # SCP during power management operations and for SCP RAM Firmware transfer.
32 PLAT_INCLUDES := -Iplat/arm/board/juno/include
37 # Flag to enable support for AArch32 state on JUNO
42 # Flag to enable support for TZMP1 on JUNO
122 ./lib/romlib/gen_combined_bl1_romlib.sh -o bl1_romlib.bin $(BUILD_PLAT)
124 # Errata workarounds for Cortex-A53:
134 # Errata workarounds for Cortex-A57:
147 # Errata workarounds for Cortex-A72:
[all …]
|