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/external/llvm/test/MC/ARM/
Dv8_IT_manual.s5 it ge
9 it ge
12 it ge
15 it ge
19 it ge
23 it ge
27 it ge
31 it ge
35 it ge
39 it ge
[all …]
/external/json-schema-validator/src/main/resources/
Djsv-messages_tr.properties4 allOf = {0}: t�m {1} \u015Femalar\u0131 i�in ge�erli olmal\u0131d\u0131r
5 anyOf = {0}: {1} \u015Femalar\u0131ndan herhangi biri i�in ge�erli olmal\u0131d\u0131r
7 contains = {0}: bu do\u011Frulamalar\u0131 ge�en bir �\u011Fe i�ermiyor: {2}
8 contains.max = {0}: \u015Fu do\u011Frulamalar\u0131 ge�en en fazla {1} �\u011Fe i�ermelidir: {2}
9 contains.min = {0}: \u015Fu do\u011Frulamalar\u0131 ge�en en az {1} �\u011Fe i�ermelidir: {2}
18 format.date = {0}: {1} modeliyle e\u015Fle\u015Fmiyor, ge�erli bir RFC 3339 tam tarihi olmal\u0131d…
19 format.date-time = {0}: {1} modeliyle e\u015Fle\u015Fmiyor, ge�erli bir RFC 3339 tarih-saat olmal\u…
20 format.duration = {0}: {1} modeliyle e\u015Fle\u015Fmiyor, ge�erli bir ISO 8601 s�resi olmal\u0131d…
21 format.email = {0}: {1} modeliyle e\u015Fle\u015Fmiyor, ge�erli bir RFC 5321 Posta Kutusu olmal\u01…
22 format.ipv4 = {0}: {1} modeliyle e\u015Fle\u015Fmiyor, ge�erli bir RFC 2673 IP adresi olmal\u0131d\…
[all …]
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-operand-rn-in-it-block-t32.cc2346 {{ge, r0, r0}, true, ge, "ge r0 r0", "ge_r0_r0"},
2347 {{ge, r0, r1}, true, ge, "ge r0 r1", "ge_r0_r1"},
2348 {{ge, r0, r2}, true, ge, "ge r0 r2", "ge_r0_r2"},
2349 {{ge, r0, r3}, true, ge, "ge r0 r3", "ge_r0_r3"},
2350 {{ge, r0, r4}, true, ge, "ge r0 r4", "ge_r0_r4"},
2351 {{ge, r0, r5}, true, ge, "ge r0 r5", "ge_r0_r5"},
2352 {{ge, r0, r6}, true, ge, "ge r0 r6", "ge_r0_r6"},
2353 {{ge, r0, r7}, true, ge, "ge r0 r7", "ge_r0_r7"},
2354 {{ge, r0, r8}, true, ge, "ge r0 r8", "ge_r0_r8"},
2355 {{ge, r0, r9}, true, ge, "ge r0 r9", "ge_r0_r9"},
[all …]
Dtest-assembler-cond-rdlow-operand-imm8-in-it-block-t32.cc116 {{ge, r1, 250}, true, ge, "ge r1 250", "ge_r1_250"},
125 {{ge, r6, 203}, true, ge, "ge r6 203", "ge_r6_203"},
132 {{ge, r4, 133}, true, ge, "ge r4 133", "ge_r4_133"},
151 {{ge, r7, 217}, true, ge, "ge r7 217", "ge_r7_217"},
158 {{ge, r1, 182}, true, ge, "ge r1 182", "ge_r1_182"},
169 {{ge, r5, 91}, true, ge, "ge r5 91", "ge_r5_91"},
177 {{ge, r0, 171}, true, ge, "ge r0 171", "ge_r0_171"},
179 {{ge, r5, 245}, true, ge, "ge r5 245", "ge_r5_245"},
183 {{ge, r1, 17}, true, ge, "ge r1 17", "ge_r1_17"},
195 {{ge, r0, 210}, true, ge, "ge r0 210", "ge_r0_210"},
[all …]
Dtest-assembler-cond-rd-operand-rn-low-registers-in-it-block-t32.cc735 {{ge, r0, r0}, true, ge, "ge r0 r0", "ge_r0_r0"},
736 {{ge, r0, r1}, true, ge, "ge r0 r1", "ge_r0_r1"},
737 {{ge, r0, r2}, true, ge, "ge r0 r2", "ge_r0_r2"},
738 {{ge, r0, r3}, true, ge, "ge r0 r3", "ge_r0_r3"},
739 {{ge, r0, r4}, true, ge, "ge r0 r4", "ge_r0_r4"},
740 {{ge, r0, r5}, true, ge, "ge r0 r5", "ge_r0_r5"},
741 {{ge, r0, r6}, true, ge, "ge r0 r6", "ge_r0_r6"},
742 {{ge, r0, r7}, true, ge, "ge r0 r7", "ge_r0_r7"},
743 {{ge, r1, r0}, true, ge, "ge r1 r0", "ge_r1_r0"},
744 {{ge, r1, r1}, true, ge, "ge r1 r1", "ge_r1_r1"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-zero-in-it-block-t32.cc735 {{ge, r0, r0, 0}, true, ge, "ge r0 r0 0", "ge_r0_r0_0"},
736 {{ge, r0, r1, 0}, true, ge, "ge r0 r1 0", "ge_r0_r1_0"},
737 {{ge, r0, r2, 0}, true, ge, "ge r0 r2 0", "ge_r0_r2_0"},
738 {{ge, r0, r3, 0}, true, ge, "ge r0 r3 0", "ge_r0_r3_0"},
739 {{ge, r0, r4, 0}, true, ge, "ge r0 r4 0", "ge_r0_r4_0"},
740 {{ge, r0, r5, 0}, true, ge, "ge r0 r5 0", "ge_r0_r5_0"},
741 {{ge, r0, r6, 0}, true, ge, "ge r0 r6 0", "ge_r0_r6_0"},
742 {{ge, r0, r7, 0}, true, ge, "ge r0 r7 0", "ge_r0_r7_0"},
743 {{ge, r1, r0, 0}, true, ge, "ge r1 r0 0", "ge_r1_r0_0"},
744 {{ge, r1, r1, 0}, true, ge, "ge r1 r1 0", "ge_r1_r1_0"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-rmlow-in-it-block-t32.cc735 {{ge, r0, r0, r0}, true, ge, "ge r0 r0 r0", "ge_r0_r0_r0"},
736 {{ge, r0, r1, r0}, true, ge, "ge r0 r1 r0", "ge_r0_r1_r0"},
737 {{ge, r0, r2, r0}, true, ge, "ge r0 r2 r0", "ge_r0_r2_r0"},
738 {{ge, r0, r3, r0}, true, ge, "ge r0 r3 r0", "ge_r0_r3_r0"},
739 {{ge, r0, r4, r0}, true, ge, "ge r0 r4 r0", "ge_r0_r4_r0"},
740 {{ge, r0, r5, r0}, true, ge, "ge r0 r5 r0", "ge_r0_r5_r0"},
741 {{ge, r0, r6, r0}, true, ge, "ge r0 r6 r0", "ge_r0_r6_r0"},
742 {{ge, r0, r7, r0}, true, ge, "ge r0 r7 r0", "ge_r0_r7_r0"},
743 {{ge, r1, r0, r1}, true, ge, "ge r1 r0 r1", "ge_r1_r0_r1"},
744 {{ge, r1, r1, r1}, true, ge, "ge r1 r1 r1", "ge_r1_r1_r1"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-imm3-in-it-block-t32.cc112 {{ge, r7, r5, 7}, true, ge, "ge r7 r5 7", "ge_r7_r5_7"},
118 {{ge, r7, r1, 0}, true, ge, "ge r7 r1 0", "ge_r7_r1_0"},
119 {{ge, r2, r0, 0}, true, ge, "ge r2 r0 0", "ge_r2_r0_0"},
120 {{ge, r1, r7, 0}, true, ge, "ge r1 r7 0", "ge_r1_r7_0"},
143 {{ge, r0, r5, 3}, true, ge, "ge r0 r5 3", "ge_r0_r5_3"},
148 {{ge, r0, r0, 6}, true, ge, "ge r0 r0 6", "ge_r0_r0_6"},
169 {{ge, r0, r3, 2}, true, ge, "ge r0 r3 2", "ge_r0_r3_2"},
171 {{ge, r7, r3, 5}, true, ge, "ge r7 r3 5", "ge_r7_r3_5"},
199 {{ge, r2, r3, 5}, true, ge, "ge r2 r3 5", "ge_r2_r3_5"},
211 {{ge, r2, r4, 0}, true, ge, "ge r2 r4 0", "ge_r2_r4_0"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc96 {{{ge, r1, r1, LSL, r6}, true, ge, "ge r1 r1 LSL r6", "ge_r1_r1_LSL_r6"},
118 {{ge, r4, r4, ASR, r1}, true, ge, "ge r4 r4 ASR r1", "ge_r4_r4_ASR_r1"},
122 {{ge, r6, r6, ROR, r3}, true, ge, "ge r6 r6 ROR r3", "ge_r6_r6_ROR_r3"},
127 {{ge, r4, r4, LSL, r0}, true, ge, "ge r4 r4 LSL r0", "ge_r4_r4_LSL_r0"},
132 {{ge, r1, r1, ASR, r7}, true, ge, "ge r1 r1 ASR r7", "ge_r1_r1_ASR_r7"},
156 {{ge, r3, r3, ROR, r7}, true, ge, "ge r3 r3 ROR r7", "ge_r3_r3_ROR_r7"},
162 {{ge, r4, r4, ROR, r1}, true, ge, "ge r4 r4 ROR r1", "ge_r4_r4_ROR_r1"},
165 {{ge, r3, r3, LSL, r4}, true, ge, "ge r3 r3 LSL r4", "ge_r3_r3_LSL_r4"},
170 {{ge, r1, r1, ASR, r2}, true, ge, "ge r1 r1 ASR r2", "ge_r1_r1_ASR_r2"},
171 {{ge, r7, r7, LSR, r4}, true, ge, "ge r7 r7 LSR r4", "ge_r7_r7_LSR_r4"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-t32.cc106 {{ge, r6, r6, r1}, true, ge, "ge r6 r6 r1", "ge_r6_r6_r1"},
113 {{ge, r7, r7, r6}, true, ge, "ge r7 r7 r6", "ge_r7_r7_r6"},
135 {{ge, r3, r3, r7}, true, ge, "ge r3 r3 r7", "ge_r3_r3_r7"},
152 {{ge, r2, r2, r5}, true, ge, "ge r2 r2 r5", "ge_r2_r2_r5"},
209 {{ge, r2, r2, r6}, true, ge, "ge r2 r2 r6", "ge_r2_r2_r6"},
227 {{ge, r6, r6, r4}, true, ge, "ge r6 r6 r4", "ge_r6_r6_r4"},
242 {{ge, r3, r3, r6}, true, ge, "ge r3 r3 r6", "ge_r3_r3_r6"},
257 {{ge, r4, r4, r6}, true, ge, "ge r4 r4 r6", "ge_r4_r4_r6"},
265 {{ge, r0, r0, r6}, true, ge, "ge r0 r0 r6", "ge_r0_r0_r6"},
277 {{ge, r2, r2, r2}, true, ge, "ge r2 r2 r2", "ge_r2_r2_r2"},
[all …]
Dtest-assembler-cond-rd-operand-rn-a32.cc116 {{ge, r12, r3}, false, al, "ge r12 r3", "ge_r12_r3"},
118 {{ge, r7, r13}, false, al, "ge r7 r13", "ge_r7_r13"},
120 {{ge, r9, r3}, false, al, "ge r9 r3", "ge_r9_r3"},
135 {{ge, r13, r5}, false, al, "ge r13 r5", "ge_r13_r5"},
137 {{ge, r7, r11}, false, al, "ge r7 r11", "ge_r7_r11"},
151 {{ge, r7, r7}, false, al, "ge r7 r7", "ge_r7_r7"},
154 {{ge, r9, r7}, false, al, "ge r9 r7", "ge_r9_r7"},
184 {{ge, r3, r10}, false, al, "ge r3 r10", "ge_r3_r10"},
203 {{ge, r4, r5}, false, al, "ge r4 r5", "ge_r4_r5"},
213 {{ge, r11, r13}, false, al, "ge r11 r13", "ge_r11_r13"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-imm8-in-it-block-t32.cc100 {{ge, r6, r6, 181}, true, ge, "ge r6 r6 181", "ge_r6_r6_181"},
103 {{ge, r4, r4, 195}, true, ge, "ge r4 r4 195", "ge_r4_r4_195"},
124 {{ge, r6, r6, 88}, true, ge, "ge r6 r6 88", "ge_r6_r6_88"},
126 {{ge, r5, r5, 242}, true, ge, "ge r5 r5 242", "ge_r5_r5_242"},
154 {{ge, r1, r1, 103}, true, ge, "ge r1 r1 103", "ge_r1_r1_103"},
157 {{ge, r7, r7, 22}, true, ge, "ge r7 r7 22", "ge_r7_r7_22"},
187 {{ge, r1, r1, 69}, true, ge, "ge r1 r1 69", "ge_r1_r1_69"},
279 {{ge, r0, r0, 223}, true, ge, "ge r0 r0 223", "ge_r0_r0_223"},
295 {{ge, r4, r4, 208}, true, ge, "ge r4 r4 208", "ge_r4_r4_208"},
303 {{ge, r7, r7, 233}, true, ge, "ge r7 r7 233", "ge_r7_r7_233"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-all-low-in-it-block-t32.cc124 {{ge, r1, r3, r4}, true, ge, "ge r1 r3 r4", "ge_r1_r3_r4"},
127 {{ge, r6, r2, r3}, true, ge, "ge r6 r2 r3", "ge_r6_r2_r3"},
129 {{ge, r7, r2, r4}, true, ge, "ge r7 r2 r4", "ge_r7_r2_r4"},
132 {{ge, r0, r7, r7}, true, ge, "ge r0 r7 r7", "ge_r0_r7_r7"},
140 {{ge, r6, r5, r5}, true, ge, "ge r6 r5 r5", "ge_r6_r5_r5"},
168 {{ge, r3, r2, r3}, true, ge, "ge r3 r2 r3", "ge_r3_r2_r3"},
181 {{ge, r4, r3, r6}, true, ge, "ge r4 r3 r6", "ge_r4_r3_r6"},
183 {{ge, r6, r7, r6}, true, ge, "ge r6 r7 r6", "ge_r6_r7_r6"},
185 {{ge, r4, r2, r3}, true, ge, "ge r4 r2 r3", "ge_r4_r2_r3"},
186 {{ge, r3, r5, r1}, true, ge, "ge r3 r5 r1", "ge_r3_r5_r1"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-amount-1to31-in-it-block-t32.cc99 {{ge, r5, r0, LSL, 3}, true, ge, "ge r5 r0 LSL 3", "ge_r5_r0_LSL_3"},
101 {{ge, r6, r6, LSL, 28}, true, ge, "ge r6 r6 LSL 28", "ge_r6_r6_LSL_28"},
105 {{ge, r0, r1, LSL, 6}, true, ge, "ge r0 r1 LSL 6", "ge_r0_r1_LSL_6"},
126 {{ge, r1, r3, LSL, 10}, true, ge, "ge r1 r3 LSL 10", "ge_r1_r3_LSL_10"},
143 {{ge, r5, r3, LSL, 26}, true, ge, "ge r5 r3 LSL 26", "ge_r5_r3_LSL_26"},
147 {{ge, r1, r3, LSL, 20}, true, ge, "ge r1 r3 LSL 20", "ge_r1_r3_LSL_20"},
165 {{ge, r1, r3, LSL, 25}, true, ge, "ge r1 r3 LSL 25", "ge_r1_r3_LSL_25"},
168 {{ge, r4, r5, LSL, 19}, true, ge, "ge r4 r5 LSL 19", "ge_r4_r5_LSL_19"},
181 {{ge, r2, r3, LSL, 21}, true, ge, "ge r2 r3 LSL 21", "ge_r2_r3_LSL_21"},
241 {{ge, r2, r0, LSL, 4}, true, ge, "ge r2 r0 LSL 4", "ge_r2_r0_LSL_4"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-rd-is-rn-in-it-block-t32.cc107 {{ge, r7, r7, r12}, true, ge, "ge r7 r7 r12", "ge_r7_r7_r12"},
116 {{ge, r12, r12, r2}, true, ge, "ge r12 r12 r2", "ge_r12_r12_r2"},
120 {{ge, r14, r14, r4}, true, ge, "ge r14 r14 r4", "ge_r14_r14_r4"},
125 {{ge, r3, r3, r12}, true, ge, "ge r3 r3 r12", "ge_r3_r3_r12"},
203 {{ge, r5, r5, r6}, true, ge, "ge r5 r5 r6", "ge_r5_r5_r6"},
215 {{ge, r11, r11, r2}, true, ge, "ge r11 r11 r2", "ge_r11_r11_r2"},
242 {{ge, r4, r4, r9}, true, ge, "ge r4 r4 r9", "ge_r4_r4_r9"},
271 {{ge, r14, r14, r12}, true, ge, "ge r14 r14 r12", "ge_r14_r14_r12"},
333 {{ge, r6, r6, r11}, true, ge, "ge r6 r6 r11", "ge_r6_r6_r11"},
342 {{ge, r13, r13, r4}, true, ge, "ge r13 r13 r4", "ge_r13_r13_r4"},
[all …]
Dtest-macro-assembler-cond-rd-rn-pc-a32.cc397 {{ge, r0, r15}, "ge, r0, r15", "ge_r0_r15"},
398 {{ge, r1, r15}, "ge, r1, r15", "ge_r1_r15"},
399 {{ge, r2, r15}, "ge, r2, r15", "ge_r2_r15"},
400 {{ge, r3, r15}, "ge, r3, r15", "ge_r3_r15"},
401 {{ge, r4, r15}, "ge, r4, r15", "ge_r4_r15"},
402 {{ge, r5, r15}, "ge, r5, r15", "ge_r5_r15"},
403 {{ge, r6, r15}, "ge, r6, r15", "ge_r6_r15"},
404 {{ge, r7, r15}, "ge, r7, r15", "ge_r7_r15"},
405 {{ge, r8, r15}, "ge, r8, r15", "ge_r8_r15"},
406 {{ge, r9, r15}, "ge, r9, r15", "ge_r9_r15"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-rd-is-rn-is-sp-in-it-block-t32.cc245 {{ge, r13, r13, r0}, true, ge, "ge r13 r13 r0", "ge_r13_r13_r0"},
246 {{ge, r13, r13, r1}, true, ge, "ge r13 r13 r1", "ge_r13_r13_r1"},
247 {{ge, r13, r13, r2}, true, ge, "ge r13 r13 r2", "ge_r13_r13_r2"},
248 {{ge, r13, r13, r3}, true, ge, "ge r13 r13 r3", "ge_r13_r13_r3"},
249 {{ge, r13, r13, r4}, true, ge, "ge r13 r13 r4", "ge_r13_r13_r4"},
250 {{ge, r13, r13, r5}, true, ge, "ge r13 r13 r5", "ge_r13_r13_r5"},
251 {{ge, r13, r13, r6}, true, ge, "ge r13 r13 r6", "ge_r13_r13_r6"},
252 {{ge, r13, r13, r7}, true, ge, "ge r13 r13 r7", "ge_r13_r13_r7"},
253 {{ge, r13, r13, r8}, true, ge, "ge r13 r13 r8", "ge_r13_r13_r8"},
254 {{ge, r13, r13, r9}, true, ge, "ge r13 r13 r9", "ge_r13_r13_r9"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc122 {{ge, r6, r0, ROR, 16}, false, al, "ge r6 r0 ROR 16", "ge_r6_r0_ROR_16"},
124 {{ge, r10, r13, ROR, 31},
127 "ge r10 r13 ROR 31",
164 {{ge, r9, r3, ROR, 4}, false, al, "ge r9 r3 ROR 4", "ge_r9_r3_ROR_4"},
187 {{ge, r4, r8, ROR, 29}, false, al, "ge r4 r8 ROR 29", "ge_r4_r8_ROR_29"},
211 {{ge, r2, r0, LSL, 18}, false, al, "ge r2 r0 LSL 18", "ge_r2_r0_LSL_18"},
257 {{ge, r13, r8, LSL, 26}, false, al, "ge r13 r8 LSL 26", "ge_r13_r8_LSL_26"},
270 {{ge, r13, r0, LSL, 31}, false, al, "ge r13 r0 LSL 31", "ge_r13_r0_LSL_31"},
279 {{ge, r4, r11, ROR, 17}, false, al, "ge r4 r11 ROR 17", "ge_r4_r11_ROR_17"},
305 {{ge, r8, r12, LSL, 31}, false, al, "ge r8 r12 LSL 31", "ge_r8_r12_LSL_31"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-amount-1to32-in-it-block-t32.cc96 {{{ge, r7, r6, LSR, 20}, true, ge, "ge r7 r6 LSR 20", "ge_r7_r6_LSR_20"},
104 {{ge, r5, r0, ASR, 23}, true, ge, "ge r5 r0 ASR 23", "ge_r5_r0_ASR_23"},
137 {{ge, r7, r3, ASR, 28}, true, ge, "ge r7 r3 ASR 28", "ge_r7_r3_ASR_28"},
139 {{ge, r3, r7, LSR, 23}, true, ge, "ge r3 r7 LSR 23", "ge_r3_r7_LSR_23"},
140 {{ge, r3, r3, LSR, 25}, true, ge, "ge r3 r3 LSR 25", "ge_r3_r3_LSR_25"},
157 {{ge, r0, r5, ASR, 24}, true, ge, "ge r0 r5 ASR 24", "ge_r0_r5_ASR_24"},
195 {{ge, r0, r4, LSR, 24}, true, ge, "ge r0 r4 LSR 24", "ge_r0_r4_LSR_24"},
214 {{ge, r3, r7, LSR, 17}, true, ge, "ge r3 r7 LSR 17", "ge_r3_r7_LSR_17"},
218 {{ge, r7, r7, ASR, 20}, true, ge, "ge r7 r7 ASR 20", "ge_r7_r7_ASR_20"},
236 {{ge, r7, r4, LSR, 15}, true, ge, "ge r7 r4 LSR 15", "ge_r7_r4_LSR_15"},
[all …]
/external/federated-compute/fcp/base/
Dwall_clock_stopwatch_test.cc31 using ::testing::Ge;
57 EXPECT_THAT(stopwatch->GetTotalDuration(), Ge(absl::Milliseconds(100))); in TEST()
68 EXPECT_THAT(stopwatch->GetTotalDuration(), Ge(absl::Milliseconds(100))); in TEST()
73 EXPECT_THAT(stopwatch->GetTotalDuration(), Ge(absl::Milliseconds(100))); in TEST()
79 EXPECT_THAT(stopwatch->GetTotalDuration(), Ge(absl::Milliseconds(200))); in TEST()
88 EXPECT_THAT(stopwatch->GetTotalDuration(), Ge(absl::Milliseconds(100))); in TEST()
92 EXPECT_THAT(stopwatch->GetTotalDuration(), Ge(absl::Milliseconds(200))); in TEST()
101 EXPECT_THAT(stopwatch->GetTotalDuration(), Ge(absl::Milliseconds(100))); in TEST()
105 EXPECT_THAT(stopwatch->GetTotalDuration(), Ge(absl::Milliseconds(200))); in TEST()
112 EXPECT_THAT(stopwatch->GetTotalDuration(), Ge(absl::Milliseconds(300))); in TEST()
[all …]
/external/swiftshader/third_party/subzero/src/
DIceTargetLoweringARM32.def39 X(Oge , GE , kNone, ge , none , false, false) \
41 X(Ole , LS , kNone, ge , none , true , false) \
43 X(Ord , VC , kNone, ge , gt , false, false) \
45 X(Ugt , HI , kNone, ge , none , true , true) \
47 X(Ult , LT , kNone, ge , none , false, true) \
50 X(Uno , VS , kNone, ge , gt , false, true) \
60 X(Uge, false , false , CS, CS , CC , ge , false, false) \
62 X(Ule, false , false , LS, LS , HI , ge , true , false) \
63 X(Sgt, true , true , GT, LT , GE , gt , false, false) \
64 X(Sge, true , false , GE, GE , LT , ge , false, false) \
[all …]
/external/federated-compute/fcp/client/
Dphase_logger_impl_test.cc39 using ::testing::Ge;
154 HistogramCounters::TRAINING_FL_ELIGIBILITY_EVAL_CHECKIN_LATENCY, Ge(0)); in TEST_P()
173 HistogramCounters::TRAINING_FL_ELIGIBILITY_EVAL_CHECKIN_LATENCY, Ge(0)); in TEST_P()
193 HistogramCounters::TRAINING_FL_ELIGIBILITY_EVAL_CHECKIN_LATENCY, Ge(0)); in TEST_P()
207 HistogramCounters::TRAINING_FL_ELIGIBILITY_EVAL_CHECKIN_LATENCY, Ge(0)); in TEST_P()
220 HistogramCounters::TRAINING_FL_ELIGIBILITY_EVAL_CHECKIN_LATENCY, Ge(0)); in TEST_P()
243 HistogramCounters::TRAINING_FL_ELIGIBILITY_EVAL_CHECKIN_LATENCY, Ge(0)); in TEST_P()
257 AllOf(Ge(absl::Minutes(1)), in TEST_P()
278 AllOf(Ge(expected_duration), in TEST_P()
363 VerifyCounterLogged(HistogramCounters::TRAINING_RUN_PHASE_LATENCY, Ge(0)); in TEST_P()
[all …]
/external/hyphenation-patterns/rekenaar/af/
Dhyph-af.hyp.txt38 ge-beds-ket-ting
39 ge-bruik-sfeer
40 ge-loofs-i-den-ti-teit
42 ge-skoert
43 ge-slags-om-gang
44 ge-voels-kri-tiek
45 ge-voels-waar-de
46 ge-we-tens-angs
47 ge-wrig-smeer
66 in-ter-net-om-ge-wing
[all …]
/external/rust/android-crates-io/crates/googletest/src/matchers/
Dge_matcher.rs30 /// verify_that!(1, ge(0))?; // Passes
34 /// verify_that!(0, ge(1))?; // Fails
48 /// verify_that!(123u32, ge(0u64))?; // Does not compile
49 /// verify_that!(123u32 as u64, ge(0u64))?; // Passes
59 /// verify_that!(actual, ge(expected))?; // Does not compile
69 /// verify_that!(actual, ge(&expected))?; // Compiles and passes
77 pub fn ge<ExpectedT>(expected: ExpectedT) -> GeMatcher<ExpectedT> { in ge() function
114 verify_that!(actual, ge(expected)) in ge_matches_i32_with_i32()
119 let matcher = ge(10); in ge_does_not_match_smaller_i32()
126 verify_that!("B", ge("A")) in ge_matches_bigger_str()
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/external/pytorch/.ci/docker/common/
Dinstall_miopen.sh75 if [[ $ROCM_INT -ge 60200 ]] && [[ $ROCM_INT -lt 60300 ]]; then
77 elif [[ $ROCM_INT -ge 60100 ]] && [[ $ROCM_INT -lt 60200 ]]; then
80 elif [[ $ROCM_INT -ge 60000 ]] && [[ $ROCM_INT -lt 60100 ]]; then
83 elif [[ $ROCM_INT -ge 50700 ]] && [[ $ROCM_INT -lt 60000 ]]; then
86 elif [[ $ROCM_INT -ge 50600 ]] && [[ $ROCM_INT -lt 50700 ]]; then
88 elif [[ $ROCM_INT -ge 50500 ]] && [[ $ROCM_INT -lt 50600 ]]; then
90 elif [[ $ROCM_INT -ge 50400 ]] && [[ $ROCM_INT -lt 50500 ]]; then
93 elif [[ $ROCM_INT -ge 50300 ]] && [[ $ROCM_INT -lt 50400 ]]; then
96 elif [[ $ROCM_INT -ge 50200 ]] && [[ $ROCM_INT -lt 50300 ]]; then
99 elif [[ $ROCM_INT -ge 50100 ]] && [[ $ROCM_INT -lt 50200 ]]; then
[all …]

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