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/external/capstone/bindings/ocaml/
Dsysz_const.ml3 let _SYSZ_CC_INVALID = 0;;
4 let _SYSZ_CC_O = 1;;
5 let _SYSZ_CC_H = 2;;
6 let _SYSZ_CC_NLE = 3;;
7 let _SYSZ_CC_L = 4;;
8 let _SYSZ_CC_NHE = 5;;
9 let _SYSZ_CC_LH = 6;;
10 let _SYSZ_CC_NE = 7;;
11 let _SYSZ_CC_E = 8;;
12 let _SYSZ_CC_NLH = 9;;
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Dx86_const.ml3 let _X86_REG_INVALID = 0;;
4 let _X86_REG_AH = 1;;
5 let _X86_REG_AL = 2;;
6 let _X86_REG_AX = 3;;
7 let _X86_REG_BH = 4;;
8 let _X86_REG_BL = 5;;
9 let _X86_REG_BP = 6;;
10 let _X86_REG_BPL = 7;;
11 let _X86_REG_BX = 8;;
12 let _X86_REG_CH = 9;;
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Darm_const.ml3 let _ARM_SFT_INVALID = 0;;
4 let _ARM_SFT_ASR = 1;;
5 let _ARM_SFT_LSL = 2;;
6 let _ARM_SFT_LSR = 3;;
7 let _ARM_SFT_ROR = 4;;
8 let _ARM_SFT_RRX = 5;;
9 let _ARM_SFT_ASR_REG = 6;;
10 let _ARM_SFT_LSL_REG = 7;;
11 let _ARM_SFT_LSR_REG = 8;;
12 let _ARM_SFT_ROR_REG = 9;;
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Darm64_const.ml3 let _ARM64_SFT_INVALID = 0;;
4 let _ARM64_SFT_LSL = 1;;
5 let _ARM64_SFT_MSL = 2;;
6 let _ARM64_SFT_LSR = 3;;
7 let _ARM64_SFT_ASR = 4;;
8 let _ARM64_SFT_ROR = 5;;
10 let _ARM64_EXT_INVALID = 0;;
11 let _ARM64_EXT_UXTB = 1;;
12 let _ARM64_EXT_UXTH = 2;;
13 let _ARM64_EXT_UXTW = 3;;
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Dppc_const.ml3 let _PPC_BC_INVALID = 0;;
4 let _PPC_BC_LT = (0 lsl 5) lor 12;;
5 let _PPC_BC_LE = (1 lsl 5) lor 4;;
6 let _PPC_BC_EQ = (2 lsl 5) lor 12;;
7 let _PPC_BC_GE = (0 lsl 5) lor 4;;
8 let _PPC_BC_GT = (1 lsl 5) lor 12;;
9 let _PPC_BC_NE = (2 lsl 5) lor 4;;
10 let _PPC_BC_UN = (3 lsl 5) lor 12;;
11 let _PPC_BC_NU = (3 lsl 5) lor 4;;
12 let _PPC_BC_SO = (4 lsl 5) lor 12;;
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Dmips_const.ml3 let _MIPS_OP_INVALID = 0;;
4 let _MIPS_OP_REG = 1;;
5 let _MIPS_OP_IMM = 2;;
6 let _MIPS_OP_MEM = 3;;
8 let _MIPS_REG_INVALID = 0;;
9 let _MIPS_REG_PC = 1;;
10 let _MIPS_REG_0 = 2;;
11 let _MIPS_REG_1 = 3;;
12 let _MIPS_REG_2 = 4;;
13 let _MIPS_REG_3 = 5;;
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Dm68k_const.ml2 let _M68K_OPERAND_COUNT = 4;;
4 let _M68K_REG_INVALID = 0;;
5 let _M68K_REG_D0 = 1;;
6 let _M68K_REG_D1 = 2;;
7 let _M68K_REG_D2 = 3;;
8 let _M68K_REG_D3 = 4;;
9 let _M68K_REG_D4 = 5;;
10 let _M68K_REG_D5 = 6;;
11 let _M68K_REG_D6 = 7;;
12 let _M68K_REG_D7 = 8;;
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Dm680x_const.ml2 let _M680X_OPERAND_COUNT = 9;;
4 let _M680X_REG_INVALID = 0;;
5 let _M680X_REG_A = 1;;
6 let _M680X_REG_B = 2;;
7 let _M680X_REG_E = 3;;
8 let _M680X_REG_F = 4;;
9 let _M680X_REG_0 = 5;;
10 let _M680X_REG_D = 6;;
11 let _M680X_REG_W = 7;;
12 let _M680X_REG_CC = 8;;
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Dsparc_const.ml3 let _SPARC_CC_INVALID = 0;;
4 let _SPARC_CC_ICC_A = 8+256;;
5 let _SPARC_CC_ICC_N = 0+256;;
6 let _SPARC_CC_ICC_NE = 9+256;;
7 let _SPARC_CC_ICC_E = 1+256;;
8 let _SPARC_CC_ICC_G = 10+256;;
9 let _SPARC_CC_ICC_LE = 2+256;;
10 let _SPARC_CC_ICC_GE = 11+256;;
11 let _SPARC_CC_ICC_L = 3+256;;
12 let _SPARC_CC_ICC_GU = 12+256;;
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Dtms320c64x_const.ml3 let _TMS320C64X_OP_INVALID = 0;;
4 let _TMS320C64X_OP_REG = 1;;
5 let _TMS320C64X_OP_IMM = 2;;
6 let _TMS320C64X_OP_MEM = 3;;
7 let _TMS320C64X_OP_REGPAIR = 64;;
9 let _TMS320C64X_MEM_DISP_INVALID = 0;;
10 let _TMS320C64X_MEM_DISP_CONSTANT = 1;;
11 let _TMS320C64X_MEM_DISP_REGISTER = 2;;
13 let _TMS320C64X_MEM_DIR_INVALID = 0;;
14 let _TMS320C64X_MEM_DIR_FW = 1;;
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Dxcore_const.ml3 let _XCORE_OP_INVALID = 0;;
4 let _XCORE_OP_REG = 1;;
5 let _XCORE_OP_IMM = 2;;
6 let _XCORE_OP_MEM = 3;;
8 let _XCORE_REG_INVALID = 0;;
9 let _XCORE_REG_CP = 1;;
10 let _XCORE_REG_DP = 2;;
11 let _XCORE_REG_LR = 3;;
12 let _XCORE_REG_SP = 4;;
13 let _XCORE_REG_R0 = 5;;
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Devm_const.ml3 let _EVM_INS_STOP = 0;;
4 let _EVM_INS_ADD = 1;;
5 let _EVM_INS_MUL = 2;;
6 let _EVM_INS_SUB = 3;;
7 let _EVM_INS_DIV = 4;;
8 let _EVM_INS_SDIV = 5;;
9 let _EVM_INS_MOD = 6;;
10 let _EVM_INS_SMOD = 7;;
11 let _EVM_INS_ADDMOD = 8;;
12 let _EVM_INS_MULMOD = 9;;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonDepInstrInfo.td16 let Inst{13-5} = 0b000000100;
17 let Inst{31-21} = 0b10001100100;
18 let hasNewValue = 1;
19 let opNewValue = 0;
20 let prefersSlot3 = 1;
27 let Inst{13-5} = 0b000000110;
28 let Inst{31-21} = 0b10000000100;
29 let prefersSlot3 = 1;
36 let Inst{13-5} = 0b000000101;
37 let Inst{31-21} = 0b10001100100;
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DHexagonDepInstrFormats.td13 let Inst{20-16} = Rs32{4-0};
15 let Inst{4-0} = Rd32{4-0};
17 let Inst{6-5} = Pe4{1-0};
21 let Inst{6-5} = Qs4{1-0};
23 let Inst{20-16} = Rt32{4-0};
25 let Inst{13-13} = Mu2{0-0};
27 let Inst{12-8} = Vv32{4-0};
29 let Inst{4-0} = Vw32{4-0};
33 let Inst{17-16} = Ps4{1-0};
35 let Inst{9-8} = Pt4{1-0};
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/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/
DHexagonDepInstrInfo.td16 let Inst{13-5} = 0b000000100;
17 let Inst{31-21} = 0b10001100100;
18 let hasNewValue = 1;
19 let opNewValue = 0;
20 let prefersSlot3 = 1;
27 let Inst{13-5} = 0b000000110;
28 let Inst{31-21} = 0b10000000100;
29 let prefersSlot3 = 1;
36 let Inst{13-5} = 0b000000101;
37 let Inst{31-21} = 0b10001100100;
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/external/clang/include/clang/Basic/
DAttr.td53 let Category = DocCatUndocumented;
215 let KnownToGCC = 1;
261 let OSes = ["Win32"];
264 let CXXABIs = ["Microsoft"];
315 let ASTNode = 0;
350 let Subjects = SubjectList<[ParmVar]>;
355 let Ignored = 1;
356 let ASTNode = 0;
357 let SemaHandler = 0;
358 let Documentation = [Undocumented];
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DGenericOpcodes.td19 let isPreISelOpcode = 1;
25 let OutOperandList = (outs type0:$dst);
26 let InOperandList = (ins type1:$src);
27 let hasSideEffects = 0;
33 let OutOperandList = (outs type0:$dst);
34 let InOperandList = (ins type1:$src);
35 let hasSideEffects = 0;
47 let OutOperandList = (outs type0:$dst);
48 let InOperandList = (ins type0:$src, untyped_imm_0:$sz);
49 let hasSideEffects = 0;
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/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/
DMicroMipsInstrFormats.td24 let Namespace = "Mips";
25 let DecoderNamespace = "MicroMips";
27 let OutOperandList = outs;
28 let InOperandList = ins;
30 let AsmString = asmstr;
31 let Pattern = pattern;
32 let Itinerary = itin;
34 let EncodingPredicates = [InMicroMips];
46 let Size = 2;
63 let Inst{15-10} = 0x01;
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DMipsMSAInstrFormats.td11 let EncodingPredicates = [HasStdEnc];
12 let Inst{31-26} = 0b011110;
16 let Inst{31-26} = 0b010001;
20 let Inst{31-26} = 0b000000;
26 let EncodingPredicates = [HasStdEnc];
27 let ASEPredicate = [HasMSA];
35 let Inst{25-23} = major;
36 let Inst{22-19} = 0b1110;
37 let Inst{18-16} = m;
38 let Inst{15-11} = ws;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMicroMipsInstrFormats.td24 let Namespace = "Mips";
25 let DecoderNamespace = "MicroMips";
27 let OutOperandList = outs;
28 let InOperandList = ins;
30 let AsmString = asmstr;
31 let Pattern = pattern;
32 let Itinerary = itin;
34 let EncodingPredicates = [InMicroMips];
46 let Size = 2;
63 let Inst{15-10} = 0x01;
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DMipsMSAInstrFormats.td11 let EncodingPredicates = [HasStdEnc];
12 let Inst{31-26} = 0b011110;
16 let Inst{31-26} = 0b010001;
20 let Inst{31-26} = 0b000000;
26 let EncodingPredicates = [HasStdEnc];
27 let ASEPredicate = [HasMSA];
35 let Inst{25-23} = major;
36 let Inst{22-19} = 0b1110;
37 let Inst{18-16} = m;
38 let Inst{15-11} = ws;
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/external/llvm/lib/Target/Mips/
DMicroMipsInstrFormats.td12 let Namespace = "Mips";
13 let DecoderNamespace = "MicroMips";
15 let OutOperandList = outs;
16 let InOperandList = ins;
18 let AsmString = asmstr;
19 let Pattern = pattern;
20 let Itinerary = itin;
22 let Predicates = [InMicroMips];
34 let Size = 2;
51 let Inst{15-10} = 0x01;
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DMicroMips32r6InstrFormats.td23 let InsnPredicates = [HasMicroMips32r6];
49 let Inst{15-10} = 0x33;
50 let Inst{9-0} = offset;
59 let Inst{15-10} = op;
60 let Inst{9-7} = rs;
61 let Inst{6-0} = offset;
69 let Inst{15-10} = 0x11;
70 let Inst{9-5} = rs;
71 let Inst{4-0} = op;
81 let Inst{31-26} = 0b011101;
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/external/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td54 let TSFlags{0} = VM_CNT;
55 let TSFlags{1} = EXP_CNT;
56 let TSFlags{2} = LGKM_CNT;
58 let TSFlags{3} = SALU;
59 let TSFlags{4} = VALU;
61 let TSFlags{5} = SOP1;
62 let TSFlags{6} = SOP2;
63 let TSFlags{7} = SOPC;
64 let TSFlags{8} = SOPK;
65 let TSFlags{9} = SOPP;
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/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/Target/
DGenericOpcodes.td19 let isPreISelOpcode = true;
28 let OutOperandList = baseInst.OutOperandList;
29 let InOperandList = baseInst.InOperandList;
30 let isCommutable = baseInst.isCommutable;
34 let hasSideEffects = true;
35 let mayRaiseFPException = true;
41 let OutOperandList = (outs type0:$dst);
42 let InOperandList = (ins type1:$src);
43 let hasSideEffects = false;
49 let OutOperandList = (outs type0:$dst);
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