| /external/coreboot/src/soc/intel/broadwell/pch/ |
| D | power_state.c | 35 static int prev_sleep_state(const struct chipset_power_state *ps) in prev_sleep_state() argument
40 if (ps->pm1_sts & WAK_STS) { in prev_sleep_state()
41 switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { in prev_sleep_state()
51 outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); in prev_sleep_state()
54 if (ps->gen_pmcon3 & (PWR_FLR | SUS_PWR_FLR)) in prev_sleep_state()
60 static void dump_power_state(struct chipset_power_state *ps) in dump_power_state() argument
62 printk(BIOS_DEBUG, "PM1_STS: %04x\n", ps->pm1_sts); in dump_power_state()
63 printk(BIOS_DEBUG, "PM1_EN: %04x\n", ps->pm1_en); in dump_power_state()
64 printk(BIOS_DEBUG, "PM1_CNT: %08x\n", ps->pm1_cnt); in dump_power_state()
66 ps->tco1_sts, ps->tco2_sts); in dump_power_state()
[all …]
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| D | elog.c | 22 static void pch_log_wake_source(const struct chipset_power_state *ps) in pch_log_wake_source() argument
25 if (ps->pm1_sts & PWRBTN_STS) in pch_log_wake_source()
29 if (ps->pm1_sts & RTC_STS) in pch_log_wake_source()
33 if (ps->pm1_sts & PCIEXPWAK_STS) in pch_log_wake_source()
37 if (ps->gpe0_sts[GPE_STD] & PME_STS) in pch_log_wake_source()
41 if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) in pch_log_wake_source()
45 if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) in pch_log_wake_source()
49 if (ps->gpe0_sts[GPE_STD] & GP27_STS) in pch_log_wake_source()
53 pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); in pch_log_wake_source()
54 pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32); in pch_log_wake_source()
[all …]
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| /external/libxaac/decoder/ |
| D | ixheaacd_mps_calc_m1m2_tree_515x.c | 50 WORD32 ps, pb; in ixheaacd_calc_m1m2_5151() local
145 for (ps = 0; ps < num_parameter_sets; ps++) { in ixheaacd_calc_m1m2_5151()
147 h22_res_fs, c_l_fs, c_r_fs, 0, ps, res_bands[0]); in ixheaacd_calc_m1m2_5151()
149 c_l_c, c_r_c, 1, ps, res_bands[1]); in ixheaacd_calc_m1m2_5151()
151 c_l_s, c_r_s, 2, ps, res_bands[2]); in ixheaacd_calc_m1m2_5151()
153 c_l_f, c_r_f, 3, ps, res_bands[3]); in ixheaacd_calc_m1m2_5151()
158 ->r1_matrix_l[p_cur_bs->ott_cld_idx[4][ps][pb] + 15]; in ixheaacd_calc_m1m2_5151()
160 ->r1_matrix_l[15 - p_cur_bs->ott_cld_idx[4][ps][pb]]; in ixheaacd_calc_m1m2_5151()
169 m1_param->m1_param_real[0][0][ps][pb] = ONE_IN_Q15; in ixheaacd_calc_m1m2_5151()
170 m1_param->m1_param_real[1][0][ps][pb] = ONE_IN_Q15; in ixheaacd_calc_m1m2_5151()
[all …]
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| D | ixheaacd_mps_calc_m1m2_tree_727x.c | 50 WORD32 ps, pb, col, row, i; in ixheaacd_calc_m1m2_7271() local
159 for (ps = 0; ps < num_parameter_sets; ps++) { in ixheaacd_calc_m1m2_7271()
161 c_f_l, dummy, 1, ps, res_bands[1]); in ixheaacd_calc_m1m2_7271()
163 c_f_r, dummy, 2, ps, res_bands[2]); in ixheaacd_calc_m1m2_7271()
165 h22_res_lc, c_f_lc, dummy, 3, ps, res_bands[3]); in ixheaacd_calc_m1m2_7271()
167 h22_res_rc, c_f_rc, dummy, 4, ps, res_bands[4]); in ixheaacd_calc_m1m2_7271()
181 ixheaacd_calculate_ttt(pstr_mps_state, ps, pb, p_aux_struct->ttt_config[i][0].mode, in ixheaacd_calc_m1m2_7271()
192 ixheaacd_calculate_arb_dmx_mtx(pstr_mps_state, ps, pb, g_real); in ixheaacd_calc_m1m2_7271()
208 ixheaacd_calculate_mtx_inv(pstr_mps_state, ps, pb, p_aux_struct->ttt_config[i][0].mode, in ixheaacd_calc_m1m2_7271()
214 m1_param->m1_param_real[0][0][ps][pb] = (WORD32)acc; in ixheaacd_calc_m1m2_7271()
[all …]
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| D | ixheaacd_mps_calc_m1m2_tree_757x.c | 49 WORD32 ps, pb; in ixheaacd_calc_m1m2_7571() local
91 for (ps = 0; ps < num_parameter_sets; ps++) { in ixheaacd_calc_m1m2_7571()
93 c_f_l, dummy, 0, ps, pstr_mps_state->res_bands[0]); in ixheaacd_calc_m1m2_7571()
95 c_f_r, dummy, 1, ps, pstr_mps_state->res_bands[1]); in ixheaacd_calc_m1m2_7571()
98 m1_param->m1_param_real[0][0][ps][pb] = ONE_IN_Q15; in ixheaacd_calc_m1m2_7571()
99 m1_param->m1_param_real[1][1][ps][pb] = ONE_IN_Q15; in ixheaacd_calc_m1m2_7571()
100 m1_param->m1_param_real[2][2][ps][pb] = ONE_IN_Q15; in ixheaacd_calc_m1m2_7571()
101 m1_param->m1_param_real[3][3][ps][pb] = ONE_IN_Q15; in ixheaacd_calc_m1m2_7571()
102 m1_param->m1_param_real[4][4][ps][pb] = ONE_IN_Q15; in ixheaacd_calc_m1m2_7571()
103 m1_param->m1_param_real[5][5][ps][pb] = ONE_IN_Q15; in ixheaacd_calc_m1m2_7571()
[all …]
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| D | ixheaacd_mps_calc_m1m2_emm.c | 49 WORD32 ps; in ixheaacd_calc_m1m2_emm() local
72 for (ps = 0; ps < pstr_mps_state->num_parameter_sets; ps++) { in ixheaacd_calc_m1m2_emm()
74 ps, 0); in ixheaacd_calc_m1m2_emm()
77 WORD32 m11 = p_aux_struct->ttt_cpc_1[0][ps][pb] + ONE_IN_Q16; in ixheaacd_calc_m1m2_emm()
78 WORD32 m12 = p_aux_struct->ttt_cpc_2[0][ps][pb] - ONE_IN_Q15; in ixheaacd_calc_m1m2_emm()
79 WORD32 m21 = p_aux_struct->ttt_cpc_1[0][ps][pb] - ONE_IN_Q15; in ixheaacd_calc_m1m2_emm()
80 WORD32 m22 = p_aux_struct->ttt_cpc_2[0][ps][pb] + ONE_IN_Q16; in ixheaacd_calc_m1m2_emm()
81 WORD32 m31 = ONE_IN_Q15 - p_aux_struct->ttt_cpc_1[0][ps][pb]; in ixheaacd_calc_m1m2_emm()
82 WORD32 m32 = ONE_IN_Q15 - p_aux_struct->ttt_cpc_2[0][ps][pb]; in ixheaacd_calc_m1m2_emm()
91 p_cur_bs->ott_cld_idx[0][ps][pb], p_cur_bs->ott_cld_idx[0][ps][pb], 1, in ixheaacd_calc_m1m2_emm()
[all …]
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| D | ixheaacd_mps_smoothing.c | 60 WORD32 ps = 0, pb, row, col; in ixheaacd_mps_pre_matrix_mix_matrix_smoothing() local
66 p_smoothing_data = &self->smoothing_data[ps][res_bands]; in ixheaacd_mps_pre_matrix_mix_matrix_smoothing()
68 delta = self->param_slot_diff[ps] * self->inv_smoothing_time[ps]; in ixheaacd_mps_pre_matrix_mix_matrix_smoothing()
76 self->m1_param_re[ps][pb][row][col] = in ixheaacd_mps_pre_matrix_mix_matrix_smoothing()
77 (MULT(delta, self->m1_param_re[ps][pb][row][col]) + in ixheaacd_mps_pre_matrix_mix_matrix_smoothing()
79 self->m1_param_im[ps][pb][row][col] = in ixheaacd_mps_pre_matrix_mix_matrix_smoothing()
80 (MULT(delta, self->m1_param_im[ps][pb][row][col]) + in ixheaacd_mps_pre_matrix_mix_matrix_smoothing()
82 self->m2_decor_re[ps][pb][row][col] = in ixheaacd_mps_pre_matrix_mix_matrix_smoothing()
83 (MULT(delta, self->m2_decor_re[ps][pb][row][col]) + in ixheaacd_mps_pre_matrix_mix_matrix_smoothing()
85 self->m2_decor_im[ps][pb][row][col] = in ixheaacd_mps_pre_matrix_mix_matrix_smoothing()
[all …]
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| D | ixheaacd_mps_calc_m1m2_tree_52xx.c | 48 WORD32 ps, pb, i; in ixheaacd_calc_m1m2_5227() local
93 for (ps = 0; ps < num_parameter_sets; ps++) { in ixheaacd_calc_m1m2_5227()
108 ixheaacd_calculate_ttt(pstr_mps_state, ps, pb, p_aux_struct->ttt_config[i][0].mode, in ixheaacd_calc_m1m2_5227()
119 ixheaacd_calculate_arb_dmx_mtx(pstr_mps_state, ps, pb, g_real); in ixheaacd_calc_m1m2_5227()
142 ixheaacd_calculate_mtx_inv(pstr_mps_state, ps, pb, p_aux_struct->ttt_config[i][0].mode, in ixheaacd_calc_m1m2_5227()
239 a_c1[pb] = p_aux_struct->ttt_cpc_1[0][ps][pb]; in ixheaacd_calc_m1m2_5227()
240 a_c2[pb] = p_aux_struct->ttt_cpc_2[0][ps][pb]; in ixheaacd_calc_m1m2_5227()
241 a_icc_c[pb] = p_aux_struct->ttt_icc[0][ps][pb]; in ixheaacd_calc_m1m2_5227()
244 a_c1[pb] = p_aux_struct->ttt_cld_1[0][ps][pb]; in ixheaacd_calc_m1m2_5227()
245 a_c2[pb] = p_aux_struct->ttt_cld_2[0][ps][pb]; in ixheaacd_calc_m1m2_5227()
[all …]
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| /external/coreboot/src/soc/intel/apollolake/ |
| D | elog.c | 25 static void pch_log_wake_source(const struct chipset_power_state *ps) in pch_log_wake_source() argument
32 if (ps->pm1_sts & PWRBTN_STS) in pch_log_wake_source()
36 if (ps->pm1_sts & RTC_STS) in pch_log_wake_source()
40 if (ps->pm1_sts & PCIEXPWAK_STS) in pch_log_wake_source()
44 if (ps->gpe0_sts[GPE0_A] & CSE_PME_STS) in pch_log_wake_source()
48 if (ps->gpe0_sts[GPE0_A] & XHCI_PME_STS) in pch_log_wake_source()
53 if (ps->gpe0_sts[GPE0_A] & SMB_WAK_STS) in pch_log_wake_source()
57 if (ps->prev_sleep_state != ACPI_S0) in pch_log_wake_source()
58 elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); in pch_log_wake_source()
61 pch_log_gpio_gpe(ps->gpe0_sts[GPE0_A], ps->gpe0_en[GPE0_A], 0); in pch_log_wake_source()
[all …]
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| /external/llvm/test/MC/Mips/mips5/ |
| D | valid-xfail.s | 10 abs.ps $f22,$f8
11 add.ps $f25,$f27,$f13
12 alnv.ps $f12,$f18,$f30,$12
14 c.eq.ps $fcc5,$f0,$f9
17 c.f.ps $fcc6,$f11,$f11
20 c.le.ps $fcc1,$f7,$f20
23 c.lt.ps $f19,$f5
26 c.nge.ps $f1,$f26
28 c.ngl.ps $f21,$f30
30 c.ngle.ps $fcc7,$f12,$f20
[all …]
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| /external/llvm/test/MC/Mips/mips64/ |
| D | valid-xfail.s | 10 abs.ps $f22,$f8
11 add.ps $f25,$f27,$f13
15 alnv.ps $f12,$f18,$f30,$12
17 c.eq.ps $fcc5,$f0,$f9
20 c.f.ps $fcc6,$f11,$f11
23 c.le.ps $fcc1,$f7,$f20
26 c.lt.ps $f19,$f5
29 c.nge.ps $f1,$f26
31 c.ngl.ps $f21,$f30
33 c.ngle.ps $fcc7,$f12,$f20
[all …]
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| /external/angle/third_party/glslang/src/Test/baseResults/ |
| D | hlsl.PointSize.geom.out | 10 0:8 'ps' ( in 3-element array of uint)
11 0:8 'OutputStream' ( out structure{ temp float ps})
16 0:? 'OutputStream.ps' ( out float PointSize)
17 0:10 ps: direct index for structure ( temp float)
18 0:10 's' ( temp structure{ temp float ps})
26 0:? 'ps' ( temp 3-element array of uint)
27 0:? 'ps' ( in 3-element array of uint PointSize)
29 0:? 'ps' ( temp 3-element array of uint)
30 0:? 'OutputStream' ( temp structure{ temp float ps})
32 0:? 'ps' ( in 3-element array of uint PointSize)
[all …]
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| /external/deqp-deps/glslang/Test/baseResults/ |
| D | hlsl.PointSize.geom.out | 10 0:8 'ps' ( in 3-element array of uint)
11 0:8 'OutputStream' ( out structure{ temp float ps})
16 0:? 'OutputStream.ps' ( out float PointSize)
17 0:10 ps: direct index for structure ( temp float)
18 0:10 's' ( temp structure{ temp float ps})
26 0:? 'ps' ( temp 3-element array of uint)
27 0:? 'ps' ( in 3-element array of uint PointSize)
29 0:? 'ps' ( temp 3-element array of uint)
30 0:? 'OutputStream' ( temp structure{ temp float ps})
32 0:? 'ps' ( in 3-element array of uint PointSize)
[all …]
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| /external/coreboot/src/soc/intel/cannonlake/ |
| D | elog.c | 88 static void pch_log_wake_source(const struct chipset_power_state *ps) in pch_log_wake_source() argument
91 if (ps->pm1_sts & PWRBTN_STS) in pch_log_wake_source()
95 if (ps->pm1_sts & RTC_STS) in pch_log_wake_source()
99 if (ps->pm1_sts & PCIEXPWAK_STS) in pch_log_wake_source()
103 if (ps->gpe0_sts[GPE_STD] & PME_STS) in pch_log_wake_source()
107 if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) in pch_log_wake_source()
111 if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) in pch_log_wake_source()
115 pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); in pch_log_wake_source()
116 pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32); in pch_log_wake_source()
117 pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64); in pch_log_wake_source()
[all …]
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| /external/coreboot/src/soc/intel/jasperlake/ |
| D | elog.c | 96 static void pch_log_wake_source(const struct chipset_power_state *ps) in pch_log_wake_source() argument
99 if (ps->pm1_sts & PWRBTN_STS) in pch_log_wake_source()
103 if (ps->pm1_sts & RTC_STS) in pch_log_wake_source()
107 if (ps->pm1_sts & PCIEXPWAK_STS) in pch_log_wake_source()
111 if (ps->gpe0_sts[GPE_STD] & PME_STS) in pch_log_wake_source()
115 if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) in pch_log_wake_source()
119 if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) in pch_log_wake_source()
123 pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); in pch_log_wake_source()
124 pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32); in pch_log_wake_source()
125 pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64); in pch_log_wake_source()
[all …]
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| /external/llvm/test/MC/Mips/mips64r3/ |
| D | valid-xfail.s | 10 abs.ps $f22,$f8
11 add.ps $f25,$f27,$f13
17 alnv.ps $f12,$f18,$f30,$12
19 c.eq.ps $fcc5,$f0,$f9
22 c.f.ps $fcc6,$f11,$f11
25 c.le.ps $fcc1,$f7,$f20
28 c.lt.ps $f19,$f5
31 c.nge.ps $f1,$f26
33 c.ngl.ps $f21,$f30
35 c.ngle.ps $fcc7,$f12,$f20
[all …]
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| D | valid-xfail.s | 10 abs.ps $f22,$f8
11 add.ps $f25,$f27,$f13
14 alnv.ps $f12,$f18,$f30,$12
16 c.eq.ps $fcc5,$f0,$f9
19 c.f.ps $fcc6,$f11,$f11
22 c.le.ps $fcc1,$f7,$f20
25 c.lt.ps $f19,$f5
28 c.nge.ps $f1,$f26
30 c.ngl.ps $f21,$f30
32 c.ngle.ps $fcc7,$f12,$f20
[all …]
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| D | valid-xfail.s | 10 abs.ps $f22,$f8
11 add.ps $f25,$f27,$f13
17 alnv.ps $f12,$f18,$f30,$12
19 c.eq.ps $fcc5,$f0,$f9
22 c.f.ps $fcc6,$f11,$f11
25 c.le.ps $fcc1,$f7,$f20
28 c.lt.ps $f19,$f5
31 c.nge.ps $f1,$f26
33 c.ngl.ps $f21,$f30
35 c.ngle.ps $fcc7,$f12,$f20
[all …]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| D | valid-xfail.s | 10 abs.ps $f22,$f8
11 add.ps $f25,$f27,$f13
14 alnv.ps $f12,$f18,$f30,$12
16 c.eq.ps $fcc5,$f0,$f9
19 c.f.ps $fcc6,$f11,$f11
22 c.le.ps $fcc1,$f7,$f20
25 c.lt.ps $f19,$f5
28 c.nge.ps $f1,$f26
30 c.ngl.ps $f21,$f30
32 c.ngle.ps $fcc7,$f12,$f20
[all …]
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| D | valid-xfail.s | 10 abs.ps $f22,$f8
11 add.ps $f25,$f27,$f13
14 alnv.ps $f12,$f18,$f30,$12
16 c.eq.ps $fcc5,$f0,$f9
19 c.f.ps $fcc6,$f11,$f11
22 c.le.ps $fcc1,$f7,$f20
25 c.lt.ps $f19,$f5
28 c.nge.ps $f1,$f26
30 c.ngl.ps $f21,$f30
32 c.ngle.ps $fcc7,$f12,$f20
[all …]
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| D | valid-xfail.s | 10 abs.ps $f22,$f8
11 add.ps $f25,$f27,$f13
14 alnv.ps $f12,$f18,$f30,$12
16 c.eq.ps $fcc5,$f0,$f9
19 c.f.ps $fcc6,$f11,$f11
22 c.le.ps $fcc1,$f7,$f20
25 c.lt.ps $f19,$f5
28 c.nge.ps $f1,$f26
30 c.ngl.ps $f21,$f30
32 c.ngle.ps $fcc7,$f12,$f20
[all …]
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| /external/coreboot/src/soc/intel/baytrail/romstage/ |
| D | romstage.c | 39 struct chipset_power_state *ps = &power_state; in fill_power_state() local
41 ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); in fill_power_state()
42 ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); in fill_power_state()
43 ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); in fill_power_state()
44 ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); in fill_power_state()
45 ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); in fill_power_state()
46 ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); in fill_power_state()
47 ps->prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS)); in fill_power_state()
48 ps->gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); in fill_power_state()
49 ps->gen_pmcon2 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2)); in fill_power_state()
[all …]
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| /external/coreboot/src/soc/intel/alderlake/ |
| D | elog.c | 111 static void pch_log_wake_source(struct chipset_power_state *ps) in pch_log_wake_source() argument
114 if (ps->pm1_sts & PWRBTN_STS) in pch_log_wake_source()
118 if (ps->pm1_sts & RTC_STS) in pch_log_wake_source()
122 if (ps->pm1_sts & PCIEXPWAK_STS) in pch_log_wake_source()
126 if (ps->gpe0_sts[GPE_STD] & PME_STS) in pch_log_wake_source()
130 if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) in pch_log_wake_source()
134 if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) in pch_log_wake_source()
138 pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); in pch_log_wake_source()
139 pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32); in pch_log_wake_source()
140 pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64); in pch_log_wake_source()
[all …]
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| /external/coreboot/src/soc/intel/meteorlake/ |
| D | elog.c | 113 static void pch_log_wake_source(struct chipset_power_state *ps) in pch_log_wake_source() argument
116 if (ps->pm1_sts & PWRBTN_STS) in pch_log_wake_source()
120 if (ps->pm1_sts & RTC_STS) in pch_log_wake_source()
124 if (ps->pm1_sts & PCIEXPWAK_STS) in pch_log_wake_source()
128 if (ps->gpe0_sts[GPE_STD] & PME_STS) in pch_log_wake_source()
132 if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) in pch_log_wake_source()
136 if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) in pch_log_wake_source()
140 pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); in pch_log_wake_source()
141 pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32); in pch_log_wake_source()
142 pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64); in pch_log_wake_source()
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| /external/coreboot/src/soc/intel/tigerlake/ |
| D | elog.c | 119 static void pch_log_wake_source(const struct chipset_power_state *ps) in pch_log_wake_source() argument
122 if (ps->pm1_sts & PWRBTN_STS) in pch_log_wake_source()
126 if (ps->pm1_sts & RTC_STS) in pch_log_wake_source()
130 if (ps->pm1_sts & PCIEXPWAK_STS) in pch_log_wake_source()
134 if (ps->gpe0_sts[GPE_STD] & PME_STS) in pch_log_wake_source()
138 if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) in pch_log_wake_source()
142 if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) in pch_log_wake_source()
146 pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); in pch_log_wake_source()
147 pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32); in pch_log_wake_source()
148 pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64); in pch_log_wake_source()
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