| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/GISel/ |
| D | PPCInstructionSelector.cpp | 40 const PPCRegisterBankInfo &RBI);
68 const PPCRegisterBankInfo &RBI; member in __anon7b8db8de0111::PPCInstructionSelector
87 const PPCRegisterBankInfo &RBI) in PPCInstructionSelector() argument
88 : STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), in PPCInstructionSelector()
123 const RegisterBankInfo &RBI) { in selectCopy() argument
129 const RegisterBank *DstRegBank = RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
136 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
199 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); in selectIntToFP()
229 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); in selectFPToInt()
236 const RegisterBank *DstRegBank = RBI.getRegBank(DstReg, MRI, TRI); in selectZExt()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anonbcf9cb920111::ARMInstructionSelector
162 const ARMRegisterBankInfo &RBI) { in createARMInstructionSelector() argument
163 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
175 const ARMRegisterBankInfo &RBI) in ARMInstructionSelector() argument
177 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI), in ARMInstructionSelector()
190 const RegisterBankInfo &RBI) { in guessRegClass() argument
191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
215 const RegisterBankInfo &RBI) { in selectCopy() argument
220 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI); in selectCopy()
[all …]
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anon22d030580111::ARMInstructionSelector
162 const ARMRegisterBankInfo &RBI) { in createARMInstructionSelector() argument
163 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
173 const ARMRegisterBankInfo &RBI) in ARMInstructionSelector() argument
174 : TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), in ARMInstructionSelector()
188 const RegisterBankInfo &RBI) { in guessRegClass() argument
189 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
213 const RegisterBankInfo &RBI) { in selectCopy() argument
218 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI); in selectCopy()
[all …]
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/ |
| D | MipsInstructionSelector.cpp | 36 const MipsRegisterBankInfo &RBI);
63 const MipsRegisterBankInfo &RBI; member in __anonc76c3d8a0111::MipsInstructionSelector
82 const MipsRegisterBankInfo &RBI) in MipsInstructionSelector() argument
84 RBI(RBI), in MipsInstructionSelector()
97 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID; in isRegInGprb()
102 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID; in isRegInFprb()
112 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
158 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
165 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsInstructionSelector.cpp | 36 const MipsRegisterBankInfo &RBI);
57 const MipsRegisterBankInfo &RBI; member in __anon92698f440111::MipsInstructionSelector
76 const MipsRegisterBankInfo &RBI) in MipsInstructionSelector() argument
78 TRI(*STI.getRegisterInfo()), RBI(RBI), in MipsInstructionSelector()
91 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID; in isRegInGprb()
96 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID; in isRegInFprb()
106 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
146 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
159 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 53 const AArch64RegisterBankInfo &RBI);
294 const AArch64RegisterBankInfo &RBI; member in __anona8e4f4e40111::AArch64InstructionSelector
317 const AArch64RegisterBankInfo &RBI) in AArch64InstructionSelector() argument
319 TRI(*STI.getRegisterInfo()), RBI(RBI), in AArch64InstructionSelector()
333 const RegisterBankInfo &RBI, in getRegClassForTypeOnBank() argument
431 const AArch64RegisterBankInfo &RBI, in unsupportedBinOp() argument
457 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp()
586 const RegisterBankInfo &RBI) { in isValidCopy() argument
589 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in isValidCopy()
590 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI); in isValidCopy()
[all …]
|
| D | AArch64Subtarget.cpp | 182 auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo()); in AArch64Subtarget() local
184 // FIXME: At this point, we can't rely on Subtarget having RBI. in AArch64Subtarget()
185 // It's awkward to mix passing RBI and the Subtarget; should we pass in AArch64Subtarget()
188 *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI)); in AArch64Subtarget()
190 RegBankInfo.reset(RBI); in AArch64Subtarget()
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/M68k/GISel/ |
| D | M68kInstructionSelector.cpp | 29 const M68kRegisterBankInfo &RBI);
40 const M68kRegisterBankInfo &RBI; member in __anon02b2ae470111::M68kInstructionSelector
59 const M68kRegisterBankInfo &RBI) in M68kInstructionSelector() argument
61 TRI(*STI.getRegisterInfo()), RBI(RBI), in M68kInstructionSelector()
87 const M68kRegisterBankInfo &RBI) { in createM68kInstructionSelector() argument
88 return new M68kInstructionSelector(TM, Subtarget, RBI); in createM68kInstructionSelector()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstructionSelector.cpp | 62 const X86RegisterBankInfo &RBI);
135 const X86RegisterBankInfo &RBI; member in __anon399325de0111::X86InstructionSelector
154 const X86RegisterBankInfo &RBI) in X86InstructionSelector() argument
156 TRI(*STI.getRegisterInfo()), RBI(RBI), in X86InstructionSelector()
199 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
234 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in selectCopy()
235 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
238 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI); in selectCopy()
239 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
274 DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI))) && in selectCopy()
[all …]
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| D | X86InstructionSelector.cpp | 63 const X86RegisterBankInfo &RBI);
137 const X86RegisterBankInfo &RBI; member in __anon9f698aa40111::X86InstructionSelector
156 const X86RegisterBankInfo &RBI) in X86InstructionSelector() argument
158 RBI(RBI), in X86InstructionSelector()
203 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
234 // FIXME: We need some sort of API in RBI/TRI to allow generic code to
260 RBI.constrainGenericRegister(Reg, *RC, MRI); in selectDebugInstr()
270 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in selectCopy()
271 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
274 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI); in selectCopy()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstructionSelector.cpp | 35 const RISCVRegisterBankInfo &RBI);
46 const RISCVRegisterBankInfo &RBI; member in __anonfdc763a00111::RISCVInstructionSelector
70 const RISCVRegisterBankInfo &RBI) in RISCVInstructionSelector() argument
72 TRI(*STI.getRegisterInfo()), RBI(RBI), in RISCVInstructionSelector()
100 RISCVRegisterBankInfo &RBI) { in createRISCVInstructionSelector() argument
101 return new RISCVInstructionSelector(TM, Subtarget, RBI); in createRISCVInstructionSelector()
|
| D | RISCVSubtarget.cpp | 59 auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo()); in RISCVSubtarget() local
60 RegBankInfo.reset(RBI); in RISCVSubtarget()
62 *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI)); in RISCVSubtarget()
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/GISel/ |
| D | RISCVInstructionSelector.cpp | 36 const RISCVRegisterBankInfo &RBI);
47 const RISCVRegisterBankInfo &RBI; member in __anona0e41ac90111::RISCVInstructionSelector
71 const RISCVRegisterBankInfo &RBI) in RISCVInstructionSelector() argument
72 : STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), in RISCVInstructionSelector()
100 RISCVRegisterBankInfo &RBI) { in createRISCVInstructionSelector() argument
101 return new RISCVInstructionSelector(TM, Subtarget, RBI); in createRISCVInstructionSelector()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 50 const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, in AMDGPUInstructionSelector() argument
53 TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM), in AMDGPUInstructionSelector()
107 return RBI.constrainGenericRegister(DstReg, *RC, *MRI); in selectCOPY()
112 if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI)) in selectCOPY()
141 if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI)) in selectCOPY()
153 if (SrcRC && !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI)) in selectCOPY()
168 RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI); in selectCOPY()
200 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI); in selectPHI()
256 unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI); in selectG_AND_OR_XOR()
258 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_AND_OR_XOR()
[all …]
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 49 const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, in AMDGPUInstructionSelector() argument
51 : TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM), in AMDGPUInstructionSelector()
116 return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) && in constrainCopyLikeIntrin()
117 RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI); in constrainCopyLikeIntrin()
136 return RBI.constrainGenericRegister(DstReg, *RC, *MRI); in selectCOPY()
141 if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI)) in selectCOPY()
179 if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI)) in selectCOPY()
193 RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI); in selectCOPY()
233 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI); in selectPHI()
286 unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI); in selectG_AND_OR_XOR()
[all …]
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64InstructionSelector.cpp | 73 const AArch64RegisterBankInfo &RBI);
466 const AArch64RegisterBankInfo &RBI; member in __anon6089c54d0111::AArch64InstructionSelector
496 const AArch64RegisterBankInfo &RBI) in AArch64InstructionSelector() argument
498 RBI(RBI), in AArch64InstructionSelector()
705 const AArch64RegisterBankInfo &RBI, in unsupportedBinOp() argument
731 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp()
860 const RegisterBankInfo &RBI, Register SrcReg, in copySubReg() argument
875 RBI.constrainGenericRegister(I.getOperand(0).getReg(), *To, MRI); in copySubReg()
887 const RegisterBankInfo &RBI) { in getRegClassesForCopy() argument
890 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in getRegClassesForCopy()
[all …]
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/SPIRV/ |
| D | SPIRVInstructionSelector.cpp | 49 const RegisterBankInfo &RBI; member in __anon81b739000111::SPIRVInstructionSelector
56 const RegisterBankInfo &RBI);
191 const RegisterBankInfo &RBI) in SPIRVInstructionSelector() argument
193 TRI(*ST.getRegisterInfo()), RBI(RBI), GR(*ST.getSPIRVGlobalRegistry()), in SPIRVInstructionSelector()
239 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select()
294 return MIB.constrainAllUses(TII, TRI, RBI); in spvSelect()
455 return MIB.constrainAllUses(TII, TRI, RBI); in spvSelect()
525 return MIB.constrainAllUses(TII, TRI, RBI); in selectExtInst()
540 .constrainAllUses(TII, TRI, RBI); in selectUnOpWithSrc()
606 return MIB.constrainAllUses(TII, TRI, RBI); in selectLoad()
[all …]
|
| /external/snakeyaml/src/test/resources/specification/ |
| D | example2_9.yaml | 5 rbi:
6 # 1998 rbi ranking
|
| /external/snakeyaml/src/test/resources/pyyaml/ |
| D | spec-02-09.data | 5 rbi:
6 # 1998 rbi ranking
|
| /external/python/pyyaml/tests/data/ |
| D | spec-02-09.data | 5 rbi:
6 # 1998 rbi ranking
|
| /external/llvm/test/YAMLParser/ |
| D | spec-02-09.test | 7 rbi:
8 # 1998 rbi ranking
|
| /external/python/pyyaml/examples/pygments-lexer/ |
| D | example.yaml | 17 rbi: 147 # Runs Batted In
81 rbi:
82 # 1998 rbi ranking
92 rbi:
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | Utils.cpp | 32 const RegisterBankInfo &RBI, unsigned Reg, in constrainRegToClass() argument
34 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) in constrainRegToClass()
43 const RegisterBankInfo &RBI, MachineInstr &InsertPt, in constrainOperandRegClass() argument
50 unsigned ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); in constrainOperandRegClass()
73 const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, in constrainOperandRegClass() argument
107 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass, in constrainOperandRegClass()
114 const RegisterBankInfo &RBI) { in constrainSelectedInstRegOperands() argument
144 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), in constrainSelectedInstRegOperands()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | Utils.h | 47 const RegisterBankInfo &RBI, unsigned Reg,
61 const RegisterBankInfo &RBI,
79 const RegisterBankInfo &RBI,
95 const RegisterBankInfo &RBI);
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| D | MergedLoadStoreMotion.cpp | 307 for (BasicBlock::reverse_iterator RBI = Pred0->rbegin(), RBE = Pred0->rend(); in mergeStores() local
308 RBI != RBE;) { in mergeStores()
310 Instruction *I = &*RBI; in mergeStores()
311 ++RBI; in mergeStores()
339 RBI = Pred0->rbegin(); in mergeStores()
341 LLVM_DEBUG(dbgs() << "Search again\n"; Instruction *I = &*RBI; I->dump()); in mergeStores()
|