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/external/deqp-deps/glslang/Test/baseResults/
Dspv.vulkan100.subgroupPartitioned.comp.out2 ERROR: 0:19: 'subgroup op' : requires SPIR-V 1.3
3 ERROR: 0:21: 'subgroup op' : requires SPIR-V 1.3
4 ERROR: 0:22: 'subgroup op' : requires SPIR-V 1.3
5 ERROR: 0:23: 'subgroup op' : requires SPIR-V 1.3
6 ERROR: 0:24: 'subgroup op' : requires SPIR-V 1.3
7 ERROR: 0:26: 'subgroup op' : requires SPIR-V 1.3
8 ERROR: 0:27: 'subgroup op' : requires SPIR-V 1.3
9 ERROR: 0:28: 'subgroup op' : requires SPIR-V 1.3
10 ERROR: 0:29: 'subgroup op' : requires SPIR-V 1.3
11 ERROR: 0:31: 'subgroup op' : requires SPIR-V 1.3
[all …]
Dspv.vulkan100.subgroupArithmetic.comp.out2 ERROR: 0:19: 'subgroup op' : requires SPIR-V 1.3
3 ERROR: 0:20: 'subgroup op' : requires SPIR-V 1.3
4 ERROR: 0:21: 'subgroup op' : requires SPIR-V 1.3
5 ERROR: 0:22: 'subgroup op' : requires SPIR-V 1.3
6 ERROR: 0:24: 'subgroup op' : requires SPIR-V 1.3
7 ERROR: 0:25: 'subgroup op' : requires SPIR-V 1.3
8 ERROR: 0:26: 'subgroup op' : requires SPIR-V 1.3
9 ERROR: 0:27: 'subgroup op' : requires SPIR-V 1.3
10 ERROR: 0:29: 'subgroup op' : requires SPIR-V 1.3
11 ERROR: 0:30: 'subgroup op' : requires SPIR-V 1.3
[all …]
/external/angle/third_party/glslang/src/Test/baseResults/
Dspv.vulkan100.subgroupPartitioned.comp.out2 ERROR: 0:19: 'subgroup op' : requires SPIR-V 1.3
3 ERROR: 0:21: 'subgroup op' : requires SPIR-V 1.3
4 ERROR: 0:22: 'subgroup op' : requires SPIR-V 1.3
5 ERROR: 0:23: 'subgroup op' : requires SPIR-V 1.3
6 ERROR: 0:24: 'subgroup op' : requires SPIR-V 1.3
7 ERROR: 0:26: 'subgroup op' : requires SPIR-V 1.3
8 ERROR: 0:27: 'subgroup op' : requires SPIR-V 1.3
9 ERROR: 0:28: 'subgroup op' : requires SPIR-V 1.3
10 ERROR: 0:29: 'subgroup op' : requires SPIR-V 1.3
11 ERROR: 0:31: 'subgroup op' : requires SPIR-V 1.3
[all …]
Dspv.vulkan100.subgroupArithmetic.comp.out2 ERROR: 0:19: 'subgroup op' : requires SPIR-V 1.3
3 ERROR: 0:20: 'subgroup op' : requires SPIR-V 1.3
4 ERROR: 0:21: 'subgroup op' : requires SPIR-V 1.3
5 ERROR: 0:22: 'subgroup op' : requires SPIR-V 1.3
6 ERROR: 0:24: 'subgroup op' : requires SPIR-V 1.3
7 ERROR: 0:25: 'subgroup op' : requires SPIR-V 1.3
8 ERROR: 0:26: 'subgroup op' : requires SPIR-V 1.3
9 ERROR: 0:27: 'subgroup op' : requires SPIR-V 1.3
10 ERROR: 0:29: 'subgroup op' : requires SPIR-V 1.3
11 ERROR: 0:30: 'subgroup op' : requires SPIR-V 1.3
[all …]
/external/llvm/test/MC/ARM/
Dfullfp16-neon-neg.s8 @ CHECK: error: instruction requires:
9 @ CHECK: error: instruction requires:
13 @ CHECK: error: instruction requires:
14 @ CHECK: error: instruction requires:
18 @ CHECK: error: instruction requires:
19 @ CHECK: error: instruction requires:
23 @ CHECK: error: instruction requires:
24 @ CHECK: error: instruction requires:
28 @ CHECK: error: instruction requires:
29 @ CHECK: error: instruction requires:
[all …]
Ddirective-arch_extension-fp.s20 @ CHECK-V7: error: instruction requires: FPARMv8
23 @ CHECK-V7: error: instruction requires: FPARMv8
25 @ CHECK-V7: error: instruction requires: FPARMv8
27 @ CHECK-V7: error: instruction requires: FPARMv8
29 @ CHECK-V7: error: instruction requires: FPARMv8
31 @ CHECK-V7: error: instruction requires: FPARMv8
33 @ CHECK-V7: error: instruction requires: FPARMv8
36 @ CHECK-V7: error: instruction requires: FPARMv8
38 @ CHECK-V7: error: instruction requires: FPARMv8
40 @ CHECK-V7: error: instruction requires: FPARMv8
[all …]
Ddirective-arch_extension-simd.s20 @ CHECK-V7: error: instruction requires: FPARMv8
22 @ CHECK-V7: error: instruction requires: FPARMv8
25 @ CHECK-V7: error: instruction requires: FPARMv8
27 @ CHECK-V7: error: instruction requires: FPARMv8
30 @ CHECK-V7: error: instruction requires: FPARMv8
32 @ CHECK-V7: error: instruction requires: FPARMv8
34 @ CHECK-V7: error: instruction requires: FPARMv8
36 @ CHECK-V7: error: instruction requires: FPARMv8
38 @ CHECK-V7: error: instruction requires: FPARMv8
40 @ CHECK-V7: error: instruction requires: FPARMv8
[all …]
Dfullfp16-neg.s5 @ CHECK: error: instruction requires:
8 @ CHECK: error: instruction requires:
11 @ CHECK: error: instruction requires:
14 @ CHECK: error: instruction requires:
17 @ CHECK: error: instruction requires:
20 @ CHECK: error: instruction requires:
23 @ CHECK: error: instruction requires:
26 @ CHECK: error: instruction requires:
29 @ CHECK: error: instruction requires:
32 @ CHECK: error: instruction requires:
[all …]
Ddirective-arch_extension-crypto.s20 @ CHECK-V7: error: instruction requires: crypto armv8
23 @ CHECK-V7: error: instruction requires: crypto armv8
25 @ CHECK-V7: error: instruction requires: crypto armv8
27 @ CHECK-V7: error: instruction requires: crypto armv8
29 @ CHECK-V7: error: instruction requires: crypto armv8
32 @ CHECK-V7: error: instruction requires: crypto armv8
34 @ CHECK-V7: error: instruction requires: crypto armv8
36 @ CHECK-V7: error: instruction requires: crypto armv8
39 @ CHECK-V7: error: instruction requires: crypto armv8
41 @ CHECK-V7: error: instruction requires: crypto armv8
[all …]
/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/Support/
DX86DisassemblerDecoderCommon.h80 ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \
82 ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \
84 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
89 ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \
91 ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \
93 ENUM_ENTRY(IC_XD_ADSIZE, 3, "requires an ADSIZE prefix, so " \
95 ENUM_ENTRY(IC_XS_ADSIZE, 3, "requires an ADSIZE prefix, so " \
97 ENUM_ENTRY(IC_64BIT_REXW, 5, "requires a REX.W prefix, so operands "\
99 ENUM_ENTRY(IC_64BIT_REXW_ADSIZE, 6, "requires a REX.W prefix and 0x67 " \
119 ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DX86DisassemblerDecoderCommon.h76 ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \
78 ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \
80 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
85 ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \
87 ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \
89 ENUM_ENTRY(IC_XD_ADSIZE, 3, "requires an ADSIZE prefix, so " \
91 ENUM_ENTRY(IC_XS_ADSIZE, 3, "requires an ADSIZE prefix, so " \
93 ENUM_ENTRY(IC_64BIT_REXW, 5, "requires a REX.W prefix, so operands "\
95 ENUM_ENTRY(IC_64BIT_REXW_ADSIZE, 6, "requires a REX.W prefix and 0x67 " \
115 ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \
[all …]
/external/capstone/arch/X86/
DX86DisassemblerDecoderCommon.h80 ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \
82 ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \
84 ENUM_ENTRY(IC_OF, 2, "requires 0f prefix ") \
85 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
90 ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \
92 ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \
94 ENUM_ENTRY(IC_64BIT_REXW, 5, "requires a REX.W prefix, so operands "\
96 ENUM_ENTRY(IC_64BIT_REXW_ADSIZE, 6, "requires a REX.W prefix and 0x67 " \
114 ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \
115 ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \
[all …]
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoderCommon.h81 ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \
83 ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \
85 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
90 ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \
92 ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \
94 ENUM_ENTRY(IC_64BIT_REXW, 5, "requires a REX.W prefix, so operands "\
96 ENUM_ENTRY(IC_64BIT_REXW_ADSIZE, 6, "requires a REX.W prefix and 0x67 " \
114 ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \
115 ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \
116 ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \
[all …]
/external/llvm/test/MC/SystemZ/
Dinsn-bad-zEC12.s5 #CHECK: error: {{(instruction requires: vector)?}}
91 #CHECK: error: {{(instruction requires: vector)?}}
93 #CHECK: error: {{(instruction requires: vector)?}}
95 #CHECK: error: {{(instruction requires: vector)?}}
97 #CHECK: error: {{(instruction requires: vector)?}}
99 #CHECK: error: {{(instruction requires: vector)?}}
108 #CHECK: error: {{(instruction requires: vector)?}}
110 #CHECK: error: {{(instruction requires: vector)?}}
112 #CHECK: error: {{(instruction requires: vector)?}}
114 #CHECK: error: {{(instruction requires: vector)?}}
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonDepMapAsm2Intrin.td15 (S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
17 (S2_vsatwh DoubleRegs:$src1)>, Requires<[HasV5]>;
19 (M2_mpysu_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
21 (M2_mpyud_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
23 (M2_mpyud_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
25 (M2_cmpysc_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
27 (M2_cmpysc_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
29 (M4_cmpyi_whc DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
31 (M2_mpy_sat_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
33 (M2_mpy_sat_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
[all …]
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/
DHexagonDepMapAsm2Intrin.td15 (A2_abs IntRegs:$src1)>, Requires<[HasV5]>;
17 (A2_absp DoubleRegs:$src1)>, Requires<[HasV5]>;
19 (A2_abssat IntRegs:$src1)>, Requires<[HasV5]>;
21 (A2_add IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
23 (A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
25 (A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
27 (A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
29 (A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
31 (A2_addh_h16_sat_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
33 (A2_addh_h16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
[all …]
/external/llvm/test/MC/Mips/
Dtarget-soft-float.s12 # 64: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
14 # 64: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
17 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
19 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
21 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
23 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
25 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
27 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
29 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
31 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
[all …]
/external/llvm/test/MC/AArch64/
Dfullfp16-neon-neg.s5 // CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires:
7 // CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires:
9 // CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires:
11 // CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires:
13 // CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires:
15 // CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires:
17 // CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires:
19 // CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires:
21 // CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires:
23 // CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires:
[all …]
/external/llvm/test/MC/Mips/mips32r2/
Dinvalid-dspr2.s8 …absq_s.ph $8,$a0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
9 …absq_s.qb $15,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
10 …absq_s.w $s3,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
11 …addq.ph $s1,$15,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
12 …addq_s.ph $s3,$s6,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
13 …addq_s.w $a2,$8,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
14 …addqh.ph $s4,$14,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
15 …addqh_r.ph $sp,$25,$s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
16 …addsc $s8,$15,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
17 …addu.ph $a2,$14,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
[all …]
Dinvalid-dsp.s8 …absq_s.ph $8,$a0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
9 …absq_s.w $s3,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
10 …addq.ph $s1,$15,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
11 …addq_s.ph $s3,$s6,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
12 …addq_s.w $a2,$8,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
13 …addsc $s8,$15,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
14 …addu.qb $s6,$v1,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
15 …addu_s.qb $s4,$s8,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
16 …addwc $k0,$s6,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
17 …bitrev $14,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
[all …]
Dinvalid-msa.s8 …and.v $w10,$w25,$w29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
9 …bmnz.v $w15,$w2,$w28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
10 …bmz.v $w13,$w11,$w21 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
11 …bsel.v $w28,$w7,$w0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
12 …fclass.d $w14,$w27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
13 …fclass.w $w19,$w28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
14 …fexupl.d $w10,$w29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
15 …fexupl.w $w12,$w27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
16 …fexupr.d $w31,$w15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
17 …fexupr.w $w29,$w12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
[all …]
/external/clang/test/Parser/
Dcxx-concepts-requires-clause.cpp4 // Test parsing of the optional requires-clause in a template-declaration.
6 template <typename T> requires true
10 template <typename T> requires !0
17 template <typename> requires true
20 template <typename> requires true
23 template <typename> requires true
26 template <typename TT> requires true
30 template <typename T> requires !0
33 template <typename T> requires !0
36 template <typename T> requires !0
[all …]
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips3.s8 …dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
9 …dsub $a3,$s6,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
10 …ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
11 …ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
12 …ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
13 …ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
14 …cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
15 …cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
16 …cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
17 …cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
[all …]
Dinvalid-mips5.s10 …ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
11 …ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
12 …ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
13 …ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
14 …cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
15 …cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
16 …cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
17 …cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
18 …dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
19 …daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
[all …]
/external/clang/test/Modules/
Dtarget-features.m1 // REQUIRES: x86-registered-target
2 // REQUIRES: arm-registered-target
3 // REQUIRES: aarch64-registered-target
23 // AARCH32-NOT: module 'TargetFeatures' requires
24 // AARCH64-NOT: module 'TargetFeatures' requires
25 // X86_32-NOT: module 'TargetFeatures' requires
26 // X86_64-NOT: module 'TargetFeatures' requires
28 // AARCH32-NOT: module 'TargetFeatures.arm' requires
29 // AARCH64-NOT: module 'TargetFeatures.arm' requires
30 // X86_32: module 'TargetFeatures.arm' requires feature 'arm'
[all …]

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