| /external/lzma/Asm/x86/ |
| D | AesOpt.asm | 105 ways = 11 define
107 ways = 4 define
112 iv equ @CatStr(xmm, %(ways_start_reg + ways))
113 iv_ymm equ @CatStr(ymm, %(ways_start_reg + ways))
118 rept ways
256 key0 equ @CatStr(xmm, %(ways_start_reg + ways + 1))
257 key0_ymm equ @CatStr(ymm, %(ways_start_reg + ways + 1))
259 key_last equ @CatStr(xmm, %(ways_start_reg + ways + 2))
260 key_last_ymm equ @CatStr(ymm, %(ways_start_reg + ways + 2))
261 key_last_ymm_n equ (ways_start_reg + ways + 2)
[all …]
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| /external/cpu_features/src/ |
| D | impl_x86__base_implementation.inl | 873 .ways = 4,
881 .ways = 0xFF,
889 .ways = 4,
897 .ways = 4,
905 .ways = 4,
913 .ways = 4,
921 .ways = 4,
929 .ways = 4,
937 .ways = 2,
945 .ways = 4,
[all …]
|
| /external/cronet/stable/third_party/cpu_features/src/src/ |
| D | impl_x86__base_implementation.inl | 862 .ways = 4,
870 .ways = 0xFF,
878 .ways = 4,
886 .ways = 4,
894 .ways = 4,
902 .ways = 4,
910 .ways = 4,
918 .ways = 4,
926 .ways = 2,
934 .ways = 4,
[all …]
|
| /external/cronet/tot/third_party/cpu_features/src/src/ |
| D | impl_x86__base_implementation.inl | 862 .ways = 4,
870 .ways = 0xFF,
878 .ways = 4,
886 .ways = 4,
894 .ways = 4,
902 .ways = 4,
910 .ways = 4,
918 .ways = 4,
926 .ways = 2,
934 .ways = 4,
[all …]
|
| /external/coreboot/src/vendorcode/cavium/bdk/libbdk-hal/ |
| D | bdk-l2c.c | 50 int ways; member
101 l2_node_state[node].ways = ccsidr_el1.s.associativity + 1; in bdk_l2c_get_num_sets()
103 /* Early chips didn't update the number of ways based on fusing */ in bdk_l2c_get_num_sets()
104 if ((l2_node_state[node].ways == 16) && CAVIUM_IS_MODEL(CAVIUM_CN8XXX)) in bdk_l2c_get_num_sets()
111 l2_node_state[node].ways *= 1; in bdk_l2c_get_num_sets()
114 l2_node_state[node].ways *= 2; in bdk_l2c_get_num_sets()
117 l2_node_state[node].ways *= 3; in bdk_l2c_get_num_sets()
120 l2_node_state[node].ways *= 4; in bdk_l2c_get_num_sets()
123 l2_node_state[node].ways /= 4; in bdk_l2c_get_num_sets()
132 /* Get the number of sets if the global sets/ways is not setup */ in bdk_l2c_get_num_assoc()
[all …]
|
| /external/coreboot/src/vendorcode/cavium/bdk/libdram/ |
| D | dram-l2c.c | 46 int limit_l2_ways(bdk_node_t node, int ways, int verbose) in limit_l2_ways() argument
52 if (ways >= ways_min && ways <= ways_max) in limit_l2_ways()
55 uint32_t mask = (valid_mask << ways) & valid_mask; in limit_l2_ways()
57 printf("Limiting L2 to %d ways\n", ways); in limit_l2_ways()
66 ways, ways_min, ways_max); in limit_l2_ways()
69 puts("ERROR limiting L2 cache ways\n"); in limit_l2_ways()
|
| /external/eigen/Eigen/src/Core/util/ |
| D | Memory.h | 972 int ways = (abcd[1] & 0xFFC00000) >> 22; // B[31:22]
977 int cache_size = (ways+1) * (partitions+1) * (line_size+1) * (sets+1);
1003 case 0x0A: l1 = 8; break; // 0Ah data L1 cache, 8 KB, 2 ways, 32 byte lines
1004 case 0x0C: l1 = 16; break; // 0Ch data L1 cache, 16 KB, 4 ways, 32 byte lines
1005 case 0x0E: l1 = 24; break; // 0Eh data L1 cache, 24 KB, 6 ways, 64 byte lines
1006 case 0x10: l1 = 16; break; // 10h data L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64)
1007 case 0x15: l1 = 16; break; // 15h code L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64)
1008 case 0x2C: l1 = 32; break; // 2Ch data L1 cache, 32 KB, 8 ways, 64 byte lines
1009 case 0x30: l1 = 32; break; // 30h code L1 cache, 32 KB, 8 ways, 64 byte lines
1010 case 0x60: l1 = 16; break; // 60h data L1 cache, 16 KB, 8 ways, 64 byte lines, sectored
[all …]
|
| /external/coreboot/src/vendorcode/cavium/include/bdk/libbdk-hal/ |
| D | bdk-l2c.h | 73 * the cache 'ways' that a core can evict from.
84 * @param mask The partitioning of the ways expressed as a binary mask. A 0 bit allows the core
88 * @note If any ways are blocked for all cores and the HW blocks, then those ways will never have
90 * all ways regardless of the partitioning.
99 * the cache 'ways' that a core can evict from.
109 * @param mask The partitioning of the ways expressed as a binary mask. A 0 bit allows the core
113 * @note If any ways are blocked for all cores and the HW blocks, then those ways will never have
115 * all ways regardless of the partitioning.
123 * but one of the ways (associations) available to the locking
|
| /external/trusty/arm-trusted-firmware/plat/intel/soc/agilex5/soc/ |
| D | agilex5_cache.S | 35 ubfx x3, x6, #3, #10 /* x3 <- number of cache ways - 1 */
38 clz w5, w3 /* bit position of #ways */
41 /* x3 <- number of cache ways - 1 */
43 /* x5 <- bit position of #ways */
46 mov x6, x3 /* x6 <- working copy of #ways */
|
| /external/mesa3d/src/intel/common/ |
| D | intel_pixel_hash.h | 68 * previous 3-way hash table function to an arbitrary number of ways
79 /* If both masks are equal all ways are expected to show up with in intel_compute_pixel_hash_table_nway()
87 * indices given by the bits set on the mask arguments. Ways in intel_compute_pixel_hash_table_nway()
137 * single mask is present (which means that all ways are expected in intel_compute_pixel_hash_table_nway()
141 * In cases where some ways have twice the frequency of the others, in intel_compute_pixel_hash_table_nway()
153 * since ways that appear duplicated in the phys_ids mapping above in intel_compute_pixel_hash_table_nway()
159 * number of ways. in intel_compute_pixel_hash_table_nway()
|
| /external/jazzer-api/src/main/java/com/code_intelligence/jazzer/api/ |
| D | Autofuzz.java | 107 * meaningful ways for a number of reasons.
137 * meaningful ways for a number of reasons.
167 * meaningful ways for a number of reasons.
197 * meaningful ways for a number of reasons.
228 * meaningful ways for a number of reasons.
259 * meaningful ways for a number of reasons.
284 * meaningful ways for a number of reasons.
309 * meaningful ways for a number of reasons.
334 * meaningful ways for a number of reasons.
360 * meaningful ways for a number of reasons.
|
| /external/eigen/bench/ |
| D | check_cache_queries.cpp | 65 int ways = (abcd[1] & 0xFFC00000) >> 22; // B[31:22] in main() local
69 int cache_size = (ways+1) * (partitions+1) * (line_size+1) * (sets+1); in main()
73 cout << "cache[" << cache_id << "].ways = " << ways << "\n"; in main()
|
| /external/rust/android-crates-io/crates/icu_locale/src/ |
| D | provider.rs | 11 …! �� This code is considered unstable; it may change at any time, in breaking or non-breaking ways,
23 …/ �� This code is considered unstable; it may change at any time, in breaking or non-breaking ways,
185 …/ �� This code is considered unstable; it may change at any time, in breaking or non-breaking ways,
236 …/ �� This code is considered unstable; it may change at any time, in breaking or non-breaking ways,
314 …/ �� This code is considered unstable; it may change at any time, in breaking or non-breaking ways,
360 …/ �� This code is considered unstable; it may change at any time, in breaking or non-breaking ways,
390 …/ �� This code is considered unstable; it may change at any time, in breaking or non-breaking ways,
446 …/ �� This code is considered unstable; it may change at any time, in breaking or non-breaking ways,
468 …/ �� This code is considered unstable; it may change at any time, in breaking or non-breaking ways,
|
| /external/leakcanary2/docs/ |
| D | blog-articles.md | 3 * [9 ways to avoid memory leaks in Android](https://android.jlelse.eu/9-ways-to-avoid-memory-leaks-…
|
| /external/coreboot/src/soc/intel/common/block/cpu/ |
| D | Kconfig | 89 IA32_L3_SF_MASK_x programming is required along with the data ways.
96 In the case of non-inclusive cache architecture when two ways in
112 L3 ways in Non-Inclusive eNEM mode. Hence, MSR 0xc85 is to program
113 the data ways.
|
| /external/cronet/stable/third_party/cpu_features/src/test/ |
| D | cpuinfo_x86_test.cc | 284 EXPECT_EQ(info.levels[0].ways, 8); in TEST_F()
293 EXPECT_EQ(info.levels[1].ways, 8); in TEST_F()
301 EXPECT_EQ(info.levels[2].ways, 4); in TEST_F()
309 EXPECT_EQ(info.levels[3].ways, 12); in TEST_F()
334 EXPECT_EQ(info.levels[0].ways, 8); in TEST_F()
343 EXPECT_EQ(info.levels[1].ways, 8); in TEST_F()
351 EXPECT_EQ(info.levels[2].ways, 8); in TEST_F()
359 EXPECT_EQ(info.levels[3].ways, 12); in TEST_F()
519 EXPECT_EQ(info.levels[0].ways, 4); in TEST_F()
528 EXPECT_EQ(info.levels[1].ways, 2); in TEST_F()
[all …]
|
| /external/cronet/tot/third_party/cpu_features/src/test/ |
| D | cpuinfo_x86_test.cc | 284 EXPECT_EQ(info.levels[0].ways, 8); in TEST_F()
293 EXPECT_EQ(info.levels[1].ways, 8); in TEST_F()
301 EXPECT_EQ(info.levels[2].ways, 4); in TEST_F()
309 EXPECT_EQ(info.levels[3].ways, 12); in TEST_F()
334 EXPECT_EQ(info.levels[0].ways, 8); in TEST_F()
343 EXPECT_EQ(info.levels[1].ways, 8); in TEST_F()
351 EXPECT_EQ(info.levels[2].ways, 8); in TEST_F()
359 EXPECT_EQ(info.levels[3].ways, 12); in TEST_F()
519 EXPECT_EQ(info.levels[0].ways, 4); in TEST_F()
528 EXPECT_EQ(info.levels[1].ways, 2); in TEST_F()
[all …]
|
| /external/rust/android-crates-io/crates/icu_properties/src/provider/ |
| D | names.rs | 8 …! �� This code is considered unstable; it may change at any time, in breaking or non-breaking ways,
248 …/ �� This code is considered unstable; it may change at any time, in breaking or non-breaking ways,
271 …/ �� This code is considered unstable; it may change at any time, in breaking or non-breaking ways,
295 …/ �� This code is considered unstable; it may change at any time, in breaking or non-breaking ways,
320 …/ �� This code is considered unstable; it may change at any time, in breaking or non-breaking ways,
|
| /external/curl/docs/ |
| D | HELP-US.md | 10 looking for ways to contribute and help out, this document aims to give a few
21 One of the best ways is to start working on any problems or issues you have
80 brainstorming on specific ways to do the implementation etc.
|
| /external/rust/android-crates-io/crates/rustix/src/mm/ |
| D | userfaultfd.rs | 6 //! observe and manipulate process memory in magical ways.
19 /// observe and manipulate process memory in magical ways.
|
| /external/selinux/secilc/docs/ |
| D | cil_introduction.md | 49 The design is aims to provide simplicity in several ways:
53 3. The statements are unambiguous and overlap in very well defined ways. This is in contrast to the…
55 …ules required the entire representation in memory as well. It is, in many ways, a natural result o…
57 In many ways, this design document describes what is different between the current language and CIL…
|
| /external/coreboot/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/ |
| D | MemoryMapDataHob.h | 250 UINT8 ways; // Interleave ways for SAD member
253 …UINT8 NmChWays; // Channel Interleave ways for SAD. Represents channelInterBitmap ways …
254 …UINT8 FmChWays; // Channel Interleave ways for SAD. Represents FMchannelInterBitmap way…
|
| /external/coreboot/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/ |
| D | MemoryMapDataHob.h | 247 UINT8 ways; // Interleave ways for SAD member
250 …UINT8 NmChWays; // Channel Interleave ways for SAD. Represents channelInterBitmap ways …
251 …UINT8 FmChWays; // Channel Interleave ways for SAD. Represents FMchannelInterBitmap way…
|
| /external/coreboot/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/ |
| D | MemoryMapDataHob.h | 247 UINT8 ways; // Interleave ways for SAD member
250 …UINT8 NmChWays; // Channel Interleave ways for SAD. Represents channelInterBitmap ways …
251 …UINT8 FmChWays; // Channel Interleave ways for SAD. Represents FMchannelInterBitmap way…
|
| /external/selinux/ |
| D | README.android | 1 This fork of Android differs in the following ways:
17 This fork differs from upstream libselinux in at least the following ways:
|