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1# Intel Common Code Block Publishing EFI_MP_SERVICES_PPI
2
3## Introduction
4
5This documentation is intended to document the purpose for creating EFI service
6Interface inside coreboot space to perform CPU feature programming on Application
7Processors for Intel 9th Gen (Cannon Lake) and beyond CPUs.
8
9Today coreboot is capable enough to handle multi-processor initialization on IA platforms.
10
11The multi-processor initialization code has to take care of lots of duties:
12
131. Bringing all cores out of reset
142. Load latest microcode on all cores
153. Sync latest MTRR snapshot between BSP and APs
164. Perform sets of CPU feature programming
17   * CPU Power & Thermal Management
18   * Overclocking
19   * Intel Trusted Execution Technology
20   * Intel Software Guard Extensions
21   * Intel Processor Trace etc.
22
23This above CPU feature programming lists are expected to grow with current and future
24CPU complexity and there might be some cases where certain feature programming mightbe
25closed source in nature.
26
27Platform code might need to compromise on those closed source nature of CPU programming
28if we don't plan to provide an alternate interface which can be used by coreboot to
29get-rid of such close source CPU programming.
30
31## Proposal
32
33As coreboot is doing CPU multi-processor initialization for IA platform before FSP-S
34initialization and having all possible information about cores in terms of maximum number
35of cores, APIC ids, stack size etc. It’s also possible for coreboot to extend its own
36support model and create a sets of APIs which later can be used by FSP to run CPU feature
37programming using coreboot published APIs.
38
39Due to the fact that FSP is using EFI infrastructure and need to relying on install/locate
40PPI to perform certain API call, hence coreboot has to created MP services APIs known as
41EFI_MP_SERVICES_PPI as per PI specification volume 1, section 8.3.9.
42More details here: [PI_Spec_1_6]
43
44### coreboot to publish EFI_MP_SERVICES_PPI APIs
45
46```{eval-rst}
47+------------------------------+------------------------------------------------------------------+
48| API                          | Description                                                      |
49+==============================+==================================================================+
50| PeiGetNumberOfProcessors     | Get the number of CPU's.                                         |
51+------------------------------+------------------------------------------------------------------+
52| PeiGetProcessorInfo          | Get information on a specific CPU.                               |
53+------------------------------+------------------------------------------------------------------+
54| PeiStartupAllAPs             | Activate all of the application processors.                      |
55+------------------------------+------------------------------------------------------------------+
56| PeiStartupThisAP             | Activate a specific application processor.                       |
57+------------------------------+------------------------------------------------------------------+
58| PeiSwitchBSP                 | Switch the boot strap processor.                                 |
59+------------------------------+------------------------------------------------------------------+
60| PeiEnableDisableAP           | Enable or disable an application processor.                      |
61+------------------------------+------------------------------------------------------------------+
62| PeiWhoAmI                    | Identify the currently executing processor.                      |
63+------------------------------+------------------------------------------------------------------+
64```
65
66## Code Flow
67
68Here is proposed design flow with coreboot has implemented EFI_MP_SERVICES_PPI API and FSP will make
69use of the same to perform some CPU feature programming.
70
71**coreboot-FSP MP init flow**
72![coreboot-fsp mp init flow][coreboot_publish_mp_service_api]
73
74[coreboot_publish_mp_service_api]: coreboot_publish_mp_service_api.png
75
76## Benefits
771. coreboot was using SkipMpInit=1 which will skip entire FSP CPU feature programming.
78With proposed model, coreboot will make use of SkipMpInit=0 which will allow to run all
79Silicon recommended CPU programming.
802. CPU feature programming inside FSP will be more transparent than before as it’s using
81coreboot interfaces to execute those programming.
823. coreboot will have more control over running those feature programming as API optimization
83handled by coreboot.
84
85[PI_Spec_1_6]: http://www.uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf
86