1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Pseudo-instruction MC lowering Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9bool LoongArchAsmPrinter:: 10emitPseudoExpansionLowering(MCStreamer &OutStreamer, 11 const MachineInstr *MI) { 12 switch (MI->getOpcode()) { 13 default: return false; 14 case LoongArch::PseudoAtomicStoreD: { 15 MCInst TmpInst; 16 MCOperand MCOp; 17 TmpInst.setOpcode(LoongArch::AMSWAP_DB_D); 18 // Operand: rd 19 TmpInst.addOperand(MCOperand::createReg(LoongArch::R0)); 20 // Operand: rk 21 lowerOperand(MI->getOperand(2), MCOp); 22 TmpInst.addOperand(MCOp); 23 // Operand: rj 24 lowerOperand(MI->getOperand(1), MCOp); 25 TmpInst.addOperand(MCOp); 26 EmitToStreamer(OutStreamer, TmpInst); 27 break; 28 } 29 case LoongArch::PseudoAtomicStoreW: { 30 MCInst TmpInst; 31 MCOperand MCOp; 32 TmpInst.setOpcode(LoongArch::AMSWAP_DB_W); 33 // Operand: rd 34 TmpInst.addOperand(MCOperand::createReg(LoongArch::R0)); 35 // Operand: rk 36 lowerOperand(MI->getOperand(2), MCOp); 37 TmpInst.addOperand(MCOp); 38 // Operand: rj 39 lowerOperand(MI->getOperand(1), MCOp); 40 TmpInst.addOperand(MCOp); 41 EmitToStreamer(OutStreamer, TmpInst); 42 break; 43 } 44 case LoongArch::PseudoBR: { 45 MCInst TmpInst; 46 MCOperand MCOp; 47 TmpInst.setOpcode(LoongArch::B); 48 // Operand: imm26 49 lowerOperand(MI->getOperand(0), MCOp); 50 TmpInst.addOperand(MCOp); 51 EmitToStreamer(OutStreamer, TmpInst); 52 break; 53 } 54 case LoongArch::PseudoBRIND: { 55 MCInst TmpInst; 56 MCOperand MCOp; 57 TmpInst.setOpcode(LoongArch::JIRL); 58 // Operand: rd 59 TmpInst.addOperand(MCOperand::createReg(LoongArch::R0)); 60 // Operand: rj 61 lowerOperand(MI->getOperand(0), MCOp); 62 TmpInst.addOperand(MCOp); 63 // Operand: imm16 64 lowerOperand(MI->getOperand(1), MCOp); 65 TmpInst.addOperand(MCOp); 66 EmitToStreamer(OutStreamer, TmpInst); 67 break; 68 } 69 case LoongArch::PseudoB_TAIL: { 70 MCInst TmpInst; 71 MCOperand MCOp; 72 TmpInst.setOpcode(LoongArch::B); 73 // Operand: imm26 74 lowerOperand(MI->getOperand(0), MCOp); 75 TmpInst.addOperand(MCOp); 76 EmitToStreamer(OutStreamer, TmpInst); 77 break; 78 } 79 case LoongArch::PseudoCALLIndirect: { 80 MCInst TmpInst; 81 MCOperand MCOp; 82 TmpInst.setOpcode(LoongArch::JIRL); 83 // Operand: rd 84 TmpInst.addOperand(MCOperand::createReg(LoongArch::R1)); 85 // Operand: rj 86 lowerOperand(MI->getOperand(0), MCOp); 87 TmpInst.addOperand(MCOp); 88 // Operand: imm16 89 TmpInst.addOperand(MCOperand::createImm(0)); 90 EmitToStreamer(OutStreamer, TmpInst); 91 break; 92 } 93 case LoongArch::PseudoJIRL_CALL: { 94 MCInst TmpInst; 95 MCOperand MCOp; 96 TmpInst.setOpcode(LoongArch::JIRL); 97 // Operand: rd 98 TmpInst.addOperand(MCOperand::createReg(LoongArch::R1)); 99 // Operand: rj 100 lowerOperand(MI->getOperand(0), MCOp); 101 TmpInst.addOperand(MCOp); 102 // Operand: imm16 103 lowerOperand(MI->getOperand(1), MCOp); 104 TmpInst.addOperand(MCOp); 105 EmitToStreamer(OutStreamer, TmpInst); 106 break; 107 } 108 case LoongArch::PseudoJIRL_TAIL: { 109 MCInst TmpInst; 110 MCOperand MCOp; 111 TmpInst.setOpcode(LoongArch::JIRL); 112 // Operand: rd 113 TmpInst.addOperand(MCOperand::createReg(LoongArch::R0)); 114 // Operand: rj 115 lowerOperand(MI->getOperand(0), MCOp); 116 TmpInst.addOperand(MCOp); 117 // Operand: imm16 118 lowerOperand(MI->getOperand(1), MCOp); 119 TmpInst.addOperand(MCOp); 120 EmitToStreamer(OutStreamer, TmpInst); 121 break; 122 } 123 case LoongArch::PseudoRET: { 124 MCInst TmpInst; 125 MCOperand MCOp; 126 TmpInst.setOpcode(LoongArch::JIRL); 127 // Operand: rd 128 TmpInst.addOperand(MCOperand::createReg(LoongArch::R0)); 129 // Operand: rj 130 TmpInst.addOperand(MCOperand::createReg(LoongArch::R1)); 131 // Operand: imm16 132 TmpInst.addOperand(MCOperand::createImm(0)); 133 EmitToStreamer(OutStreamer, TmpInst); 134 break; 135 } 136 case LoongArch::PseudoTAILIndirect: { 137 MCInst TmpInst; 138 MCOperand MCOp; 139 TmpInst.setOpcode(LoongArch::JIRL); 140 // Operand: rd 141 TmpInst.addOperand(MCOperand::createReg(LoongArch::R0)); 142 // Operand: rj 143 lowerOperand(MI->getOperand(0), MCOp); 144 TmpInst.addOperand(MCOp); 145 // Operand: imm16 146 TmpInst.addOperand(MCOperand::createImm(0)); 147 EmitToStreamer(OutStreamer, TmpInst); 148 break; 149 } 150 case LoongArch::PseudoUNIMP: { 151 MCInst TmpInst; 152 MCOperand MCOp; 153 TmpInst.setOpcode(LoongArch::AMSWAP_W); 154 // Operand: rd 155 TmpInst.addOperand(MCOperand::createReg(LoongArch::R0)); 156 // Operand: rk 157 TmpInst.addOperand(MCOperand::createReg(LoongArch::R1)); 158 // Operand: rj 159 TmpInst.addOperand(MCOperand::createReg(LoongArch::R0)); 160 EmitToStreamer(OutStreamer, TmpInst); 161 break; 162 } 163 } 164 return true; 165} 166 167