1 /*
2 * Copyright © 2016 Rob Clark <robclark@freedesktop.org>
3 * SPDX-License-Identifier: MIT
4 *
5 * Authors:
6 * Rob Clark <robclark@freedesktop.org>
7 */
8
9 #ifndef FD5_CONTEXT_H_
10 #define FD5_CONTEXT_H_
11
12 #include "util/u_upload_mgr.h"
13
14 #include "freedreno_context.h"
15
16 #include "ir3/ir3_shader.h"
17
18 struct fd5_context {
19 struct fd_context base;
20
21 /* This only needs to be 4 * num_of_pipes bytes (ie. 32 bytes). We
22 * could combine it with another allocation.
23 */
24 struct fd_bo *vsc_size_mem;
25
26 /* TODO not sure what this is for.. probably similar to
27 * CACHE_FLUSH_TS on kernel side, where value gets written
28 * to this address synchronized w/ 3d (ie. a way to
29 * synchronize when the CP is running far ahead)
30 */
31 struct fd_bo *blit_mem;
32
33 struct u_upload_mgr *border_color_uploader;
34 struct pipe_resource *border_color_buf;
35
36 /* storage for ctx->last.key: */
37 struct ir3_shader_key last_key;
38
39 /* cached state about current emitted shader program (3d): */
40 unsigned max_loc;
41 };
42
43 static inline struct fd5_context *
fd5_context(struct fd_context * ctx)44 fd5_context(struct fd_context *ctx)
45 {
46 return (struct fd5_context *)ctx;
47 }
48
49 struct pipe_context *fd5_context_create(struct pipe_screen *pscreen, void *priv,
50 unsigned flags);
51
52 /* helper for places where we need to stall CP to wait for previous draws: */
53 static inline void
fd5_emit_flush(struct fd_context * ctx,struct fd_ringbuffer * ring)54 fd5_emit_flush(struct fd_context *ctx, struct fd_ringbuffer *ring)
55 {
56 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
57 OUT_RING(ring, CACHE_FLUSH_TS);
58 OUT_RELOC(ring, fd5_context(ctx)->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
59 OUT_RING(ring, 0x00000000);
60
61 OUT_WFI5(ring);
62 }
63
64 #endif /* FD5_CONTEXT_H_ */
65