1 /*
2 * Copyright © 2019 Rob Clark <robclark@freedesktop.org>
3 * SPDX-License-Identifier: MIT
4 *
5 * Authors:
6 * Rob Clark <robclark@freedesktop.org>
7 */
8
9 #include "drm/freedreno_ringbuffer.h"
10 #define FD_BO_NO_HARDPIN 1
11
12 #include "pipe/p_state.h"
13 #include "util/u_dump.h"
14 #include "u_tracepoints.h"
15
16 #include "freedreno_resource.h"
17 #include "freedreno_tracepoints.h"
18
19 #include "fd6_barrier.h"
20 #include "fd6_compute.h"
21 #include "fd6_const.h"
22 #include "fd6_context.h"
23 #include "fd6_emit.h"
24 #include "fd6_pack.h"
25
26 template <chip CHIP>
27 static void
cs_program_emit_local_size(struct fd_context * ctx,struct fd_ringbuffer * ring,struct ir3_shader_variant * v,uint16_t local_size[3])28 cs_program_emit_local_size(struct fd_context *ctx, struct fd_ringbuffer *ring,
29 struct ir3_shader_variant *v, uint16_t local_size[3])
30 {
31 /*
32 * Devices that do not support double threadsize take the threadsize from
33 * A6XX_HLSQ_FS_CNTL_0_THREADSIZE instead of A6XX_HLSQ_CS_CNTL_1_THREADSIZE
34 * which is always set to THREAD128.
35 */
36 enum a6xx_threadsize thrsz = v->info.double_threadsize ? THREAD128 : THREAD64;
37 enum a6xx_threadsize thrsz_cs = ctx->screen->info->a6xx
38 .supports_double_threadsize ? thrsz : THREAD128;
39
40 if (CHIP == A7XX) {
41 unsigned tile_height = (local_size[1] % 8 == 0) ? 3
42 : (local_size[1] % 4 == 0) ? 5
43 : (local_size[1] % 2 == 0) ? 9
44 : 17;
45
46 OUT_REG(ring,
47 HLSQ_CS_CNTL_1(
48 CHIP,
49 .linearlocalidregid = INVALID_REG,
50 .threadsize = thrsz_cs,
51 .workgrouprastorderzfirsten = true,
52 .wgtilewidth = 4,
53 .wgtileheight = tile_height,
54 )
55 );
56
57 OUT_REG(ring,
58 A7XX_HLSQ_CS_LOCAL_SIZE(
59 .localsizex = local_size[0] - 1,
60 .localsizey = local_size[1] - 1,
61 .localsizez = local_size[2] - 1,
62 )
63 );
64 }
65 }
66
67 template <chip CHIP>
68 static void
cs_program_emit(struct fd_context * ctx,struct fd_ringbuffer * ring,struct ir3_shader_variant * v)69 cs_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
70 struct ir3_shader_variant *v)
71 assert_dt
72 {
73 OUT_REG(ring, HLSQ_INVALIDATE_CMD(CHIP, .vs_state = true, .hs_state = true,
74 .ds_state = true, .gs_state = true,
75 .fs_state = true, .cs_state = true,
76 .cs_ibo = true, .gfx_ibo = true, ));
77
78 OUT_REG(ring, HLSQ_CS_CNTL(
79 CHIP,
80 .constlen = v->constlen,
81 .enabled = true,
82 ));
83
84 OUT_PKT4(ring, REG_A6XX_SP_CS_CONFIG, 1);
85 OUT_RING(ring, A6XX_SP_CS_CONFIG_ENABLED |
86 COND(v->bindless_tex, A6XX_SP_CS_CONFIG_BINDLESS_TEX) |
87 COND(v->bindless_samp, A6XX_SP_CS_CONFIG_BINDLESS_SAMP) |
88 COND(v->bindless_ibo, A6XX_SP_CS_CONFIG_BINDLESS_IBO) |
89 COND(v->bindless_ubo, A6XX_SP_CS_CONFIG_BINDLESS_UBO) |
90 A6XX_SP_CS_CONFIG_NIBO(ir3_shader_nibo(v)) |
91 A6XX_SP_CS_CONFIG_NTEX(v->num_samp) |
92 A6XX_SP_CS_CONFIG_NSAMP(v->num_samp)); /* SP_CS_CONFIG */
93
94 uint32_t local_invocation_id = v->cs.local_invocation_id;
95 uint32_t work_group_id = v->cs.work_group_id;
96
97 /*
98 * Devices that do not support double threadsize take the threadsize from
99 * A6XX_HLSQ_FS_CNTL_0_THREADSIZE instead of A6XX_HLSQ_CS_CNTL_1_THREADSIZE
100 * which is always set to THREAD128.
101 */
102 enum a6xx_threadsize thrsz = v->info.double_threadsize ? THREAD128 : THREAD64;
103 enum a6xx_threadsize thrsz_cs = ctx->screen->info->a6xx
104 .supports_double_threadsize ? thrsz : THREAD128;
105
106 if (CHIP == A6XX) {
107 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL_0, 2);
108 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
109 A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
110 A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
111 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
112 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
113 A6XX_HLSQ_CS_CNTL_1_THREADSIZE(thrsz_cs));
114 if (!ctx->screen->info->a6xx.supports_double_threadsize) {
115 OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL_0, 1);
116 OUT_RING(ring, A6XX_HLSQ_FS_CNTL_0_THREADSIZE(thrsz));
117 }
118
119 if (ctx->screen->info->a6xx.has_lpac) {
120 OUT_PKT4(ring, REG_A6XX_SP_CS_CNTL_0, 2);
121 OUT_RING(ring, A6XX_SP_CS_CNTL_0_WGIDCONSTID(work_group_id) |
122 A6XX_SP_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
123 A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
124 A6XX_SP_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
125 OUT_RING(ring, A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
126 A6XX_SP_CS_CNTL_1_THREADSIZE(thrsz));
127 }
128 } else {
129 OUT_REG(ring, HLSQ_FS_CNTL_0(CHIP, .threadsize = THREAD64));
130 OUT_REG(ring,
131 A6XX_SP_CS_CNTL_0(
132 .wgidconstid = work_group_id,
133 .wgsizeconstid = INVALID_REG,
134 .wgoffsetconstid = INVALID_REG,
135 .localidregid = local_invocation_id,
136 )
137 );
138 OUT_REG(ring,
139 SP_CS_CNTL_1(
140 CHIP,
141 .linearlocalidregid = INVALID_REG,
142 .threadsize = thrsz_cs,
143 .workitemrastorder =
144 v->cs.force_linear_dispatch ? WORKITEMRASTORDER_LINEAR
145 : WORKITEMRASTORDER_TILED,
146 )
147 );
148 OUT_REG(ring, A7XX_SP_CS_UNKNOWN_A9BE(0)); // Sometimes is 0x08000000
149 }
150
151 if (!v->local_size_variable)
152 cs_program_emit_local_size<CHIP>(ctx, ring, v, v->local_size);
153
154 fd6_emit_shader<CHIP>(ctx, ring, v);
155 }
156
157 template <chip CHIP>
158 static void
fd6_launch_grid(struct fd_context * ctx,const struct pipe_grid_info * info)159 fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
160 {
161 struct fd6_compute_state *cs = (struct fd6_compute_state *)ctx->compute;
162 struct fd_ringbuffer *ring = ctx->batch->draw;
163
164 if (unlikely(!cs->v)) {
165 struct ir3_shader_state *hwcso = (struct ir3_shader_state *)cs->hwcso;
166 struct ir3_shader_key key = {};
167
168 cs->v = ir3_shader_variant(ir3_get_shader(hwcso), key, false, &ctx->debug);
169 if (!cs->v)
170 return;
171
172 cs->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
173 cs_program_emit<CHIP>(ctx, cs->stateobj, cs->v);
174
175 cs->user_consts_cmdstream_size = fd6_user_consts_cmdstream_size<CHIP>(cs->v);
176 }
177
178 trace_start_compute(&ctx->batch->trace, ring, !!info->indirect, info->work_dim,
179 info->block[0], info->block[1], info->block[2],
180 info->grid[0], info->grid[1], info->grid[2],
181 cs->v->shader_id);
182
183 if (ctx->batch->barrier)
184 fd6_barrier_flush<CHIP>(ctx->batch);
185
186 bool emit_instrlen_workaround =
187 cs->v->instrlen > ctx->screen->info->a6xx.instr_cache_size;
188
189 /* There appears to be a HW bug where in some rare circumstances it appears
190 * to accidentally use the FS instrlen instead of the CS instrlen, which
191 * affects all known gens. Based on various experiments it appears that the
192 * issue is that when prefetching a branch destination and there is a cache
193 * miss, when fetching from memory the HW bounds-checks the fetch against
194 * SP_CS_INSTRLEN, except when one of the two register contexts is active
195 * it accidentally fetches SP_FS_INSTRLEN from the other (inactive)
196 * context. To workaround it we set the FS instrlen here and do a dummy
197 * event to roll the context (because it fetches SP_FS_INSTRLEN from the
198 * "wrong" context). Because the bug seems to involve cache misses, we
199 * don't emit this if the entire CS program fits in cache, which will
200 * hopefully be the majority of cases.
201 *
202 * See https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19023
203 */
204 if (emit_instrlen_workaround) {
205 OUT_REG(ring, A6XX_SP_FS_INSTRLEN(cs->v->instrlen));
206 fd6_event_write<CHIP>(ctx, ring, FD_LABEL);
207 }
208
209 if (ctx->gen_dirty)
210 fd6_emit_cs_state<CHIP>(ctx, ring, cs);
211
212 if (ctx->gen_dirty & BIT(FD6_GROUP_CONST))
213 fd6_emit_cs_user_consts<CHIP>(ctx, ring, cs);
214
215 if (cs->v->need_driver_params || info->input)
216 fd6_emit_cs_driver_params<CHIP>(ctx, ring, cs, info);
217
218 OUT_PKT7(ring, CP_SET_MARKER, 1);
219 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
220
221 uint32_t shared_size =
222 MAX2(((int)(cs->v->cs.req_local_mem + info->variable_shared_mem) - 1) / 1024, 1);
223 OUT_PKT4(ring, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
224 OUT_RING(ring, A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(shared_size) |
225 A6XX_SP_CS_UNKNOWN_A9B1_UNK6);
226
227 if (CHIP == A6XX && ctx->screen->info->a6xx.has_lpac) {
228 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_UNKNOWN_B9D0, 1);
229 OUT_RING(ring, A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(shared_size) |
230 A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6);
231 }
232
233 const unsigned *local_size =
234 info->block; // v->shader->nir->info->workgroup_size;
235 const unsigned *num_groups = info->grid;
236 /* for some reason, mesa/st doesn't set info->work_dim, so just assume 3: */
237 const unsigned work_dim = info->work_dim ? info->work_dim : 3;
238
239 if (cs->v->local_size_variable) {
240 uint16_t wg[] = {local_size[0], local_size[1], local_size[2]};
241 cs_program_emit_local_size<CHIP>(ctx, ring, cs->v, wg);
242 }
243
244 OUT_REG(ring,
245 HLSQ_CS_NDRANGE_0(
246 CHIP,
247 .kerneldim = work_dim,
248 .localsizex = local_size[0] - 1,
249 .localsizey = local_size[1] - 1,
250 .localsizez = local_size[2] - 1,
251 ),
252 HLSQ_CS_NDRANGE_1(
253 CHIP,
254 .globalsize_x = local_size[0] * num_groups[0],
255 ),
256 HLSQ_CS_NDRANGE_2(CHIP, .globaloff_x = 0),
257 HLSQ_CS_NDRANGE_3(
258 CHIP,
259 .globalsize_y = local_size[1] * num_groups[1],
260 ),
261 HLSQ_CS_NDRANGE_4(CHIP, .globaloff_y = 0),
262 HLSQ_CS_NDRANGE_5(
263 CHIP,
264 .globalsize_z = local_size[2] * num_groups[2],
265 ),
266 HLSQ_CS_NDRANGE_6(CHIP, .globaloff_z = 0),
267 );
268
269 OUT_REG(ring,
270 HLSQ_CS_KERNEL_GROUP_X(CHIP, 1),
271 HLSQ_CS_KERNEL_GROUP_Y(CHIP, 1),
272 HLSQ_CS_KERNEL_GROUP_Z(CHIP, 1),
273 );
274
275 if (info->indirect) {
276 struct fd_resource *rsc = fd_resource(info->indirect);
277
278 OUT_PKT7(ring, CP_EXEC_CS_INDIRECT, 4);
279 OUT_RING(ring, 0x00000000);
280 OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0); /* ADDR_LO/HI */
281 OUT_RING(ring,
282 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
283 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
284 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
285 } else {
286 OUT_PKT7(ring, CP_EXEC_CS, 4);
287 OUT_RING(ring, 0x00000000);
288 OUT_RING(ring, CP_EXEC_CS_1_NGROUPS_X(info->grid[0]));
289 OUT_RING(ring, CP_EXEC_CS_2_NGROUPS_Y(info->grid[1]));
290 OUT_RING(ring, CP_EXEC_CS_3_NGROUPS_Z(info->grid[2]));
291 }
292
293 trace_end_compute(&ctx->batch->trace, ring);
294
295 fd_context_all_clean(ctx);
296 }
297
298 static void *
fd6_compute_state_create(struct pipe_context * pctx,const struct pipe_compute_state * cso)299 fd6_compute_state_create(struct pipe_context *pctx,
300 const struct pipe_compute_state *cso)
301 {
302 struct fd6_compute_state *hwcso =
303 (struct fd6_compute_state *)calloc(1, sizeof(*hwcso));
304 hwcso->hwcso = ir3_shader_compute_state_create(pctx, cso);
305 return hwcso;
306 }
307
308 static void
fd6_compute_state_delete(struct pipe_context * pctx,void * _hwcso)309 fd6_compute_state_delete(struct pipe_context *pctx, void *_hwcso)
310 {
311 struct fd6_compute_state *hwcso = (struct fd6_compute_state *)_hwcso;
312 ir3_shader_state_delete(pctx, hwcso->hwcso);
313 if (hwcso->stateobj)
314 fd_ringbuffer_del(hwcso->stateobj);
315 free(hwcso);
316 }
317
318 static void
fd6_get_compute_state_info(struct pipe_context * pctx,void * cso,struct pipe_compute_state_object_info * info)319 fd6_get_compute_state_info(struct pipe_context *pctx, void *cso, struct pipe_compute_state_object_info *info)
320 {
321 static struct ir3_shader_key key; /* static is implicitly zeroed */
322 struct fd6_compute_state *cs = (struct fd6_compute_state *)cso;
323 struct ir3_shader_state *hwcso = (struct ir3_shader_state *)cs->hwcso;
324 struct ir3_shader_variant *v = ir3_shader_variant(ir3_get_shader(hwcso), key, false, &pctx->debug);
325 struct fd_context *ctx = fd_context(pctx);
326 uint32_t threadsize_base = ctx->screen->info->threadsize_base;
327
328 info->max_threads = threadsize_base * ctx->screen->info->max_waves;
329 info->simd_sizes = threadsize_base;
330 info->preferred_simd_size = threadsize_base;
331
332 if (ctx->screen->info->a6xx.supports_double_threadsize &&
333 v->info.double_threadsize) {
334
335 info->max_threads *= 2;
336 info->simd_sizes |= (threadsize_base * 2);
337 info->preferred_simd_size *= 2;
338 }
339
340 info->private_memory = v->pvtmem_size;
341 }
342
343 template <chip CHIP>
344 void
fd6_compute_init(struct pipe_context * pctx)345 fd6_compute_init(struct pipe_context *pctx)
346 disable_thread_safety_analysis
347 {
348 struct fd_context *ctx = fd_context(pctx);
349
350 ctx->launch_grid = fd6_launch_grid<CHIP>;
351 pctx->create_compute_state = fd6_compute_state_create;
352 pctx->delete_compute_state = fd6_compute_state_delete;
353 pctx->get_compute_state_info = fd6_get_compute_state_info;
354 }
355 FD_GENX(fd6_compute_init);
356