1 /* 2 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 3 * Copyright (c) 2024, Altera Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef CLOCKMANAGER_H 9 #define CLOCKMANAGER_H 10 11 #include "socfpga_handoff.h" 12 13 /* Clock Manager Registers */ 14 #define CLKMGR_BASE 0x10D10000 15 #define CLKMGR_CTRL 0x00 16 #define CLKMGR_STAT 0x04 17 #define CLKMGR_TESTIOCTROL 0x08 18 #define CLKMGR_INTRGEN 0x0C 19 #define CLKMGR_INTRMSK 0x10 20 #define CLKMGR_INTRCLR 0x14 21 #define CLKMGR_INTRSTS 0x18 22 #define CLKMGR_INTRSTK 0x1C 23 #define CLKMGR_INTRRAW 0x20 24 25 /* Clock manager control related macros */ 26 #define CLKMGR(_reg) (CLKMGR_BASE + (CLKMGR_##_reg)) 27 #define CLKMGR_STAT_MAINPLLLOCKED BIT(8) 28 #define CLKMGR_STAT_PERPLLLOCKED BIT(16) 29 30 #define CLKMGR_INTRCLR_MAINLOCKLOST BIT(2) 31 #define CLKMGR_INTRCLR_PERLOCKLOST BIT(3) 32 33 #define CLKMGR_STAT_ALLPLLLOCKED (CLKMGR_STAT_MAINPLLLOCKED | \ 34 CLKMGR_STAT_PERPLLLOCKED) 35 36 /* Main PLL Group */ 37 #define CLKMGR_MAINPLL_BASE 0x10D10024 38 #define CLKMGR_MAINPLL_EN 0x00 39 #define CLKMGR_MAINPLL_ENS 0x04 40 #define CLKMGR_MAINPLL_ENR 0x08 41 #define CLKMGR_MAINPLL_BYPASS 0x0C 42 #define CLKMGR_MAINPLL_BYPASSS 0x10 43 #define CLKMGR_MAINPLL_BYPASSR 0x14 44 #define CLKMGR_MAINPLL_NOCCLK 0x1C 45 #define CLKMGR_MAINPLL_NOCDIV 0x20 46 #define CLKMGR_MAINPLL_PLLGLOB 0x24 47 #define CLKMGR_MAINPLL_FDBCK 0x28 48 #define CLKMGR_MAINPLL_MEM 0x2C 49 #define CLKMGR_MAINPLL_MEMSTAT 0x30 50 #define CLKMGR_MAINPLL_VCOCALIB 0x34 51 #define CLKMGR_MAINPLL_PLLC0 0x38 52 #define CLKMGR_MAINPLL_PLLC1 0x3C 53 #define CLKMGR_MAINPLL_PLLC2 0x40 54 #define CLKMGR_MAINPLL_PLLC3 0x44 55 #define CLKMGR_MAINPLL_PLLM 0x48 56 #define CLKMGR_MAINPLL_FHOP 0x4C 57 #define CLKMGR_MAINPLL_SSC 0x50 58 #define CLKMGR_MAINPLL_LOSTLOCK 0x54 59 60 #define CLKMGR_MAINPLL(_reg) (CLKMGR_MAINPLL_BASE + \ 61 (CLKMGR_MAINPLL_##_reg)) 62 63 #define CLKMGR_XPLL_LOSTLOCK_BYPASSCLEAR BIT(0) 64 #define CLKMGR_XPLLGLOB_CLR_LOSTLOCK_BYPASS BIT(29) 65 66 /* Peripheral PLL Group */ 67 #define CLKMGR_PERPLL_BASE 0x10D1007C 68 #define CLKMGR_PERPLL_EN 0x00 69 #define CLKMGR_PERPLL_ENS 0x04 70 #define CLKMGR_PERPLL_ENR 0x08 71 #define CLKMGR_PERPLL_BYPASS 0x0C 72 #define CLKMGR_PERPLL_BYPASSS 0x10 73 #define CLKMGR_PERPLL_BYPASSR 0x14 74 #define CLKMGR_PERPLL_EMACCTL 0x18 75 #define CLKMGR_PERPLL_GPIODIV 0x1C 76 #define CLKMGR_PERPLL_PLLGLOB 0x20 77 #define CLKMGR_PERPLL_FDBCK 0x24 78 #define CLKMGR_PERPLL_MEM 0x28 79 #define CLKMGR_PERPLL_MEMSTAT 0x2C 80 #define CLKMGR_PERPLL_VCOCALIB 0x30 81 #define CLKMGR_PERPLL_PLLC0 0x34 82 #define CLKMGR_PERPLL_PLLC1 0x38 83 #define CLKMGR_PERPLL_PLLC2 0x3C 84 #define CLKMGR_PERPLL_PLLC3 0x40 85 #define CLKMGR_PERPLL_PLLM 0x44 86 #define CLKMGR_PERPLL_FHOP 0x48 87 #define CLKMGR_PERPLL_SSC 0x4C 88 #define CLKMGR_PERPLL_LOSTLOCK 0x50 89 90 #define CLKMGR_PERPLL(_reg) (CLKMGR_PERPLL_BASE + \ 91 (CLKMGR_PERPLL_##_reg)) 92 93 /* Altera Group */ 94 #define CLKMGR_ALTERA_BASE 0x10D100D0 95 #define CLKMGR_ALTERA_JTAG 0x00 96 #define CLKMGR_ALTERA_EMACACTR 0x04 97 #define CLKMGR_ALTERA_EMACBCTR 0x08 98 #define CLKMGR_ALTERA_EMACPTPCTR 0x0C 99 #define CLKMGR_ALTERA_GPIODBCTR 0x10 100 #define CLKMGR_ALTERA_S2FUSER0CTR 0x18 101 #define CLKMGR_ALTERA_S2FUSER1CTR 0x1C 102 #define CLKMGR_ALTERA_PSIREFCTR 0x20 103 #define CLKMGR_ALTERA_EXTCNTRST 0x24 104 #define CLKMGR_ALTERA_USB31CTR 0x28 105 #define CLKMGR_ALTERA_DSUCTR 0x2C 106 #define CLKMGR_ALTERA_CORE01CTR 0x30 107 #define CLKMGR_ALTERA_CORE23CTR 0x34 108 #define CLKMGR_ALTERA_CORE2CTR 0x38 109 #define CLKMGR_ALTERA_CORE3CTR 0x3C 110 #define CLKMGR_ALTERA_SERIAL_CON_PLL_CTR 0x40 111 112 #define CLKMGR_ALTERA(_reg) (CLKMGR_ALTERA_BASE + \ 113 (CLKMGR_ALTERA_##_reg)) 114 115 #define CLKMGR_ALTERA_EXTCNTRST_EMACACNTRST BIT(0) 116 #define CLKMGR_ALTERA_EXTCNTRST_EMACBCNTRST BIT(1) 117 #define CLKMGR_ALTERA_EXTCNTRST_EMACPTPCNTRST BIT(2) 118 #define CLKMGR_ALTERA_EXTCNTRST_GPIODBCNTRST BIT(3) 119 #define CLKMGR_ALTERA_EXTCNTRST_S2FUSER0CNTRST BIT(5) 120 #define CLKMGR_ALTERA_EXTCNTRST_S2FUSER1CNTRST BIT(6) 121 #define CLKMGR_ALTERA_EXTCNTRST_PSIREFCNTRST BIT(7) 122 #define CLKMGR_ALTERA_EXTCNTRST_USB31REFCNTRST BIT(8) 123 #define CLKMGR_ALTERA_EXTCNTRST_DSUCNTRST BIT(10) 124 #define CLKMGR_ALTERA_EXTCNTRST_CORE01CNTRST BIT(11) 125 #define CLKMGR_ALTERA_EXTCNTRST_CORE2CNTRST BIT(12) 126 #define CLKMGR_ALTERA_EXTCNTRST_CORE3CNTRST BIT(13) 127 128 #define CLKMGR_ALTERA_EXTCNTRST_ALLCNTRST \ 129 (CLKMGR_ALTERA_EXTCNTRST_EMACACNTRST | \ 130 CLKMGR_ALTERA_EXTCNTRST_EMACBCNTRST | \ 131 CLKMGR_ALTERA_EXTCNTRST_EMACPTPCNTRST | \ 132 CLKMGR_ALTERA_EXTCNTRST_GPIODBCNTRST | \ 133 CLKMGR_ALTERA_EXTCNTRST_S2FUSER0CNTRST |\ 134 CLKMGR_ALTERA_EXTCNTRST_S2FUSER1CNTRST |\ 135 CLKMGR_ALTERA_EXTCNTRST_PSIREFCNTRST | \ 136 CLKMGR_ALTERA_EXTCNTRST_USB31REFCNTRST |\ 137 CLKMGR_ALTERA_EXTCNTRST_DSUCNTRST | \ 138 CLKMGR_ALTERA_EXTCNTRST_CORE01CNTRST | \ 139 CLKMGR_ALTERA_EXTCNTRST_CORE2CNTRST | \ 140 CLKMGR_ALTERA_EXTCNTRST_CORE3CNTRST) 141 142 #define CLKMGR_ALTERA_CORE0 0 143 #define CLKMGR_ALTERA_CORE1 1 144 #define CLKMGR_ALTERA_CORE2 2 145 #define CLKMGR_ALTERA_CORE3 3 146 147 /* PLL membus configuration macros */ 148 #define CLKMGR_MEM_REQ BIT(24) 149 #define CLKMGR_MEM_WR BIT(25) 150 #define CLKMGR_MEM_ERR BIT(26) 151 #define CLKMGR_MEM_WDAT_OFFSET 16 152 #define CLKMGR_MEM_ADDR_MASK GENMASK(15, 0) 153 #define CLKMGR_MEM_ADDR_START 0x00004000 154 #define CLKMGR_PLLCFG_SRC_SYNC_MODE 0x27 155 #define CLKMGR_PLLCFG_OVRSHOOT_FREQ_LOCK 0xB3 156 #define CLKMGR_PLLCFG_LOCK_SETTLE_TIME 0xE6 157 #define CLKMGR_PLLCFG_DUTYCYCLE_CLKSLICE0 0x03 158 #define CLKMGR_PLLCFG_DUTYCYCLE_CLKSLICE1 0x07 159 160 /* Clock Manager Macros */ 161 #define CLKMGR_CTRL_BOOTMODE_SET_MSK 0x00000001 162 #define CLKMGR_STAT_BUSY_E_BUSY 0x1 163 #define CLKMGR_STAT_BUSY(x) (((x) & 0x00000001) >> 0) 164 #define CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK 0x00000004 165 #define CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK 0x00000008 166 #define CLKMGR_INTOSC_HZ 460000000 167 #define CLKMGR_CTRL_BOOTMODE BIT(0) 168 #define CLKMGR_STAT_MAINPLL_LOCKED BIT(8) 169 #define CLKMGR_STAT_MAIN_TRANS BIT(9) 170 #define CLKMGR_STAT_PERPLL_LOCKED BIT(16) 171 #define CLKMGR_STAT_PERF_TRANS BIT(17) 172 #define CLKMGR_STAT_BOOTMODE BIT(24) 173 #define CLKMGR_STAT_BOOTCLKSRC BIT(25) 174 175 #define CLKMGR_STAT_ALLPLL_LOCKED_MASK (CLKMGR_STAT_MAINPLL_LOCKED | \ 176 CLKMGR_STAT_PERPLL_LOCKED) 177 /* Main PLL Macros */ 178 #define CLKMGR_MAINPLL_EN_RESET 0x0000005E 179 #define CLKMGR_MAINPLL_ENS_RESET 0x0000005E 180 #define CLKMGR_MAINPLL_PLLGLOB_PD_N BIT(0) 181 #define CLKMGR_MAINPLL_PLLGLOB_RST_N BIT(1) 182 #define CLKMGR_MAINPLL_PLLCX_EN BIT(27) 183 #define CLKMGR_MAINPLL_PLLCX_MUTE BIT(28) 184 185 #define CLKMGR_PERPLL_EN_SDMMCCLK BIT(5) 186 #define CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x0000FFFF) 187 #define CLKMGR_PERPLL_PLLGLOB_PD_N BIT(0) 188 #define CLKMGR_PERPLL_PLLGLOB_RST_N BIT(1) 189 #define CLKMGR_PERPLL_PLLCX_EN BIT(27) 190 #define CLKMGR_PERPLL_PLLCX_MUTE BIT(28) 191 192 /* Altera Macros */ 193 #define CLKMGR_ALTERA_EXTCNTRST_RESET 0xFF 194 195 /* Shared Macros */ 196 #define CLKMGR_PLLGLOB_PSRC(x) (((x) & 0x00030000) >> 16) 197 #define CLKMGR_PSRC_MAIN 0 198 #define CLKMGR_PSRC_PER 1 199 200 #define CLKMGR_PLLGLOB_PSRC_EOSC1 0x0 201 #define CLKMGR_PLLGLOB_PSRC_INTOSC 0x1 202 #define CLKMGR_PLLGLOB_PSRC_F2S 0x2 203 204 #define CLKMGR_PLLM_MDIV(x) ((x) & 0x000003FF) 205 #define CLKMGR_PLLGLOB_PD_SET_MSK 0x00000001 206 #define CLKMGR_PLLGLOB_RST_SET_MSK 0x00000002 207 208 #define CLKMGR_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003F00) >> 8) 209 #define CLKMGR_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000F00) >> 8) 210 #define CLKMGR_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12) 211 212 #define CLKMGR_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003FF) 213 #define CLKMGR_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00FF0000) 214 215 #define CLKMGR_CLR_LOSTLOCK_BYPASS 0x20000000 216 217 #define CLKMGR_CLKSRC_MASK GENMASK(18, 16) 218 #define CLKMGR_CLKSRC_OFFSET 16 219 #define CLKMGR_CLKSRC_MAIN 0 220 #define CLKMGR_CLKSRC_PER 1 221 #define CLKMGR_CLKSRC_OSC1 2 222 #define CLKMGR_CLKSRC_INTOSC 3 223 #define CLKMGR_CLKSRC_FPGA 4 224 #define CLKMGR_PLLCX_DIV_MSK GENMASK(10, 0) 225 226 #define GET_CLKMGR_CLKSRC(x) (((x) & CLKMGR_CLKSRC_MASK) >> \ 227 CLKMGR_CLKSRC_OFFSET) 228 229 #define CLKMGR_MAINPLL_NOCDIV_L4MP_MASK GENMASK(5, 4) 230 #define CLKMGR_MAINPLL_NOCDIV_L4MP_OFFSET 4 231 #define GET_CLKMGR_MAINPLL_NOCDIV_L4MP(x) (((x) & CLKMGR_MAINPLL_NOCDIV_L4MP_MASK) >> \ 232 CLKMGR_MAINPLL_NOCDIV_L4MP_OFFSET) 233 234 #define CLKMGR_MAINPLL_NOCDIV_L4SP_MASK GENMASK(7, 6) 235 #define CLKMGR_MAINPLL_NOCDIV_L4SP_OFFSET 6 236 #define GET_CLKMGR_MAINPLL_NOCDIV_L4SP(x) (((x) & CLKMGR_MAINPLL_NOCDIV_L4SP_MASK) >> \ 237 CLKMGR_MAINPLL_NOCDIV_L4SP_OFFSET) 238 239 #define CLKMGR_MAINPLL_NOCDIV_SPHY_MASK GENMASK(17, 16) 240 #define CLKMGR_MAINPLL_NOCDIV_SPHY_OFFSET 16 241 #define GET_CLKMGR_MAINPLL_NOCDIV_SPHY(x) (((x) & CLKMGR_MAINPLL_NOCDIV_SPHY_MASK) >> \ 242 CLKMGR_MAINPLL_NOCDIV_SPHY_OFFSET) 243 244 245 #define CLKMGR_MAINPLL_NOCDIV_L4SYSFREE_MASK GENMASK(3, 2) 246 #define CLKMGR_MAINPLL_NOCDIV_L4SYSFREE_OFFSET 2 247 #define GET_CLKMGR_MAINPLL_NOCDIV_L4SYSFREE(x) (((x) & CLKMGR_MAINPLL_NOCDIV_L4SYSFREE_MASK) >> \ 248 CLKMGR_MAINPLL_NOCDIV_L4SYSFREE_OFFSET) 249 250 #define CLKMGR_PERPLL_EMAC0_CLK_SRC_MASK BIT(26) 251 #define CLKMGR_PERPLL_EMAC0_CLK_SRC_OFFSET 26 252 #define GET_CLKMGR_PERPLL_EMAC0_CLK_SRC(x) (((x) & CLKMGR_PERPLL_EMAC0_CLK_SRC_MASK) >> \ 253 CLKMGR_PERPLL_EMAC0_CLK_SRC_OFFSET) 254 255 #define CLKMGR_ALTERA_EMACACTR_CLK_SRC_MASK GENMASK(18, 16) 256 #define CLKMGR_ALTERA_EMACACTR_CLK_SRC_OFFSET 16 257 #define GET_CLKMGR_EMACACTR_CLK_SRC(x) (((x) & CLKMGR_ALTERA_EMACACTR_CLK_SRC_MASK) >> \ 258 CLKMGR_ALTERA_EMACACTR_CLK_SRC_OFFSET) 259 260 #define CLKMGR_MPU_CLK_ID 0 261 #define CLKMGR_MPU_PERIPH_CLK_ID 1 262 #define CLKMGR_L4_MAIN_CLK_ID 2 263 #define CLKMGR_L4_MP_CLK_ID 3 264 #define CLKMGR_L4_SP_CLK_ID 4 265 #define CLKMGR_WDT_CLK_ID 5 266 #define CLKMGR_UART_CLK_ID 6 267 #define CLKMGR_EMAC0_CLK_ID 7 268 #define CLKMGR_EMAC1_CLK_ID 8 269 #define CLKMGR_EMAC2_CLK_ID 9 270 #define CLKMGR_EMAC_PTP_CLK_ID 10 271 #define CLKMGR_SDMMC_CLK_ID 11 272 273 #define CLKMGR_MAINPLL_BYPASS_ALL (0xF6) 274 #define CLKMGR_PERPLL_BYPASS_ALL (0xEF) 275 #define CLKMGR_PLLCX_STAT BIT(29) 276 #define GET_PLLCX_STAT(x) ((x) & CLKMGR_PLLCX_STAT) 277 278 #define CLKMGR_MAINPLL_TYPE (0) 279 #define CLKMGR_PERPLL_TYPE (1) 280 281 #define CLKMGR_MAX_RETRY_COUNT 1000 282 283 #define CLKMGR_PLLM_MDIV_MASK GENMASK(9, 0) 284 #define CLKMGR_PLLGLOB_PD_MASK BIT(0) 285 #define CLKMGR_PLLGLOB_RST_MASK BIT(1) 286 #define CLKMGR_PLLGLOB_AREFCLKDIV_MASK GENMASK(11, 8) 287 #define CLKMGR_PLLGLOB_DREFCLKDIV_MASK GENMASK(13, 12) 288 #define CLKMGR_PLLGLOB_REFCLKDIV_MASK GENMASK(13, 8) 289 #define CLKMGR_PLLGLOB_MODCLKDIV_MASK GENMASK(24, 27) 290 #define CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET 8 291 #define CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET 12 292 #define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8 293 #define CLKMGR_PLLGLOB_MODCLKDIV_OFFSET 24 294 #define CLKMGR_PLLGLOB_VCO_PSRC_MASK GENMASK(17, 16) 295 #define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16 296 #define CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK BIT(29) 297 298 #define CLKMGR_VCOCALIB_MSCNT_MASK GENMASK(23, 16) 299 #define CLKMGR_VCOCALIB_MSCNT_OFFSET 16 300 #define CLKMGR_VCOCALIB_HSCNT_MASK GENMASK(9, 0) 301 #define CLKMGR_VCOCALIB_MSCNT_CONST 100 302 #define CLKMGR_VCOCALIB_HSCNT_CONST 4 303 304 int config_clkmgr_handoff(handoff *hoff_ptr); 305 uint32_t clkmgr_get_rate(uint32_t clk_id); 306 307 /* PLL configuration data structure in power-down state */ 308 typedef struct pll_cfg { 309 uint32_t addr; 310 uint32_t data; 311 uint32_t mask; 312 } pll_cfg_t; 313 314 #endif 315