1# Blobs used in Intel Broadwell boards 2 3All Broadwell boards supported by coreboot require two proprietary blobs. 4In a coreboot image of a Broadwell board, the blobs are named `mrc.bin` and 5`refcode` in CBFS. 6 7`mrc.bin` is run in romstage to initialize the memory. It is placed at a fixed 8address in CBFS and is loaded at a fixed address in memory. 9 10`refcode` is run in ramstage to initialize the system agent and the PCH. It is 11a relocatable ELF object. 12 13## Obtaining the blobs 14 15Both `mrc.bin` and `refcode` can be obtained from a coreboot image of a Broadwell 16board, for example a Purism Librem 13 v1 coreboot image from [MrChromebox]. 17 18 cbfstool coreboot_*.rom extract -f broadwell-mrc.bin -n mrc.bin 19 cbfstool coreboot_*.rom extract -m x86 -f broadwell-refcode.elf -n fallback/refcode 20 21## SPD Addresses 22 23The SPD addresses in Broadwell `pei_data` struct are similar to [Haswell]. 24 25## Intel GbE support 26 27Unlike Haswell boards, the `pei_data` struct of Broadwell doesn't have `gbe_enable` 28field. For boards with an Intel GbE device, a modification of `refcode` is needed, 29otherwise `refcode` will disable the Intel GbE device and the OS cannot find it 30in the list of PCI devices. 31 32For the refcode binary extracted from Purism Librem 13 v1 (SHA256: 338a919ffece61ba21664b1028b0ebbfabcd727d90c1ae2f72b48152b8774323a4, 34.program section starts at file offset 0x2040), we can see the 35following code sequence: 36 37 1e06b: c6 43 0c 00 movb $0x0,0xc(%ebx) 38 1e06f: c6 83 7e 03 00 00 00 movb $0x0,0x37e(%ebx) 39 1e076: c6 83 70 03 00 00 01 movb $0x1,0x370(%ebx) 40 1e07d: 66 89 43 0a mov %ax,0xa(%ebx) 41 1e081: c6 83 da 01 00 00 01 movb $0x1,0x1da(%ebx) 42 1e088: c6 83 86 03 00 00 01 movb $0x1,0x386(%ebx) 43 44The code at 0x1e06f sets the field that is to enable the GbE to the 45hardcoded 0 value. Change the byte at 0x1e075 (file offset 0x200b5) 46to 0x01 to make the refcode support Intel GbE: 47 48 cp refcode.elf refcode_gbe.elf 49 printf '\x01' | dd of=refcode_gbe.elf bs=1 seek=131253 count=1 conv=notrunc 50 51## Use Broadwell SoC code for Haswell ULT boards 52 53Haswell ULT boards can use Broadwell SoC code. To use Broadwell code for Haswell ULT 54boards, `devicetree.cb` file and `pei_data` code need to be ported to Broadwell, and 55build the code with Broadwell `mrc.bin` and `refcode` instead of using Haswell `mrc.bin`. 56 57Broadwell SoC code doesn't support non-ULT Haswell or non-ULT Broadwell boards. 58 59[MrChromebox]: https://mrchromebox.tech/ 60[Haswell]: ../../../northbridge/intel/haswell/mrc.bin.md 61