1 /*
2 * Copyright 2009 Nicolai Haehnle.
3 * Copyright 2011 Tom Stellard <tstellar@gmail.com>
4 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Author: Tom Stellard <thomas.stellard@amd.com>
6 * SPDX-License-Identifier: MIT
7 */
8
9 #ifndef RADEON_REGALLOC_H
10 #define RADEON_REGALLOC_H
11
12 #include "util/ralloc.h"
13 #include "util/register_allocate.h"
14 #include "util/u_memory.h"
15
16 #include "radeon_variable.h"
17
18 struct ra_regs;
19
20 enum rc_reg_class {
21 RC_REG_CLASS_FP_SINGLE,
22 RC_REG_CLASS_FP_DOUBLE,
23 RC_REG_CLASS_FP_TRIPLE,
24 RC_REG_CLASS_FP_ALPHA,
25 RC_REG_CLASS_FP_SINGLE_PLUS_ALPHA,
26 RC_REG_CLASS_FP_DOUBLE_PLUS_ALPHA,
27 RC_REG_CLASS_FP_TRIPLE_PLUS_ALPHA,
28 RC_REG_CLASS_FP_X,
29 RC_REG_CLASS_FP_Y,
30 RC_REG_CLASS_FP_Z,
31 RC_REG_CLASS_FP_XY,
32 RC_REG_CLASS_FP_YZ,
33 RC_REG_CLASS_FP_XZ,
34 RC_REG_CLASS_FP_XW,
35 RC_REG_CLASS_FP_YW,
36 RC_REG_CLASS_FP_ZW,
37 RC_REG_CLASS_FP_XYW,
38 RC_REG_CLASS_FP_YZW,
39 RC_REG_CLASS_FP_XZW,
40 RC_REG_CLASS_FP_COUNT
41 };
42
43 enum rc_reg_class_vp {
44 RC_REG_CLASS_VP_SINGLE,
45 RC_REG_CLASS_VP_DOUBLE,
46 RC_REG_CLASS_VP_TRIPLE,
47 RC_REG_CLASS_VP_QUADRUPLE,
48 RC_REG_CLASS_VP_COUNT
49 };
50
51 struct rc_regalloc_state {
52 struct ra_regs *regs;
53 struct ra_class *classes[RC_REG_CLASS_FP_COUNT];
54 const struct rc_class *class_list;
55 };
56
57 struct register_info {
58 struct live_intervals Live[4];
59
60 unsigned int Used : 1;
61 unsigned int Allocated : 1;
62 unsigned int File : 3;
63 unsigned int Index : RC_REGISTER_INDEX_BITS;
64 unsigned int Writemask;
65 };
66
67 struct regalloc_state {
68 struct radeon_compiler *C;
69
70 struct register_info *Input;
71 unsigned int NumInputs;
72
73 struct register_info *Temporary;
74 unsigned int NumTemporaries;
75
76 unsigned int Simple;
77 int LoopEnd;
78 };
79
80 struct rc_class {
81 enum rc_reg_class ID;
82
83 unsigned int WritemaskCount;
84
85 /** List of writemasks that belong to this class */
86 unsigned int Writemasks[6];
87 };
88
89 int rc_find_class(const struct rc_class *classes, unsigned int writemask,
90 unsigned int max_writemask_count);
91
92 unsigned int rc_overlap_live_intervals_array(struct live_intervals *a, struct live_intervals *b);
93
94 static inline unsigned int
reg_get_index(int reg)95 reg_get_index(int reg)
96 {
97 return reg / RC_MASK_XYZW;
98 };
99
100 static inline unsigned int
reg_get_writemask(int reg)101 reg_get_writemask(int reg)
102 {
103 return (reg % RC_MASK_XYZW) + 1;
104 };
105
106 static inline int
get_reg_id(unsigned int index,unsigned int writemask)107 get_reg_id(unsigned int index, unsigned int writemask)
108 {
109 assert(writemask);
110 if (writemask == 0) {
111 return 0;
112 }
113 return (index * RC_MASK_XYZW) + (writemask - 1);
114 }
115
116 void rc_build_interference_graph(struct ra_graph *graph, struct rc_list *variables);
117
118 void rc_init_regalloc_state(struct rc_regalloc_state *s, enum rc_program_type prog);
119 void rc_destroy_regalloc_state(struct rc_regalloc_state *s);
120
121 #endif /* RADEON_REGALLOC_H */
122