1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <amdblocks/pci_devs.h>
4 #include <arch/hpet.h>
5 #include <cpu/amd/mtrr.h>
6 #include <cpu/x86/lapic_def.h>
7 #include <device/pci.h>
8 #include <northbridge/amd/agesa/agesa_helper.h>
9
amd_initcpuio(void)10 void amd_initcpuio(void)
11 {
12 /* Enable legacy video routing: D18F1xF4 VGA Enable */
13 pci_write_config32(_SOC_DEV(0x18, 1), 0xf4, 1);
14
15 /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
16 * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
17 * set to non-posted regions. Last address before processor local APIC
18 * at FEE00000, set NP (non-posted) bit.
19 */
20 pci_write_config32(_SOC_DEV(0x18, 1), 0x84,
21 ALIGN_DOWN(LAPIC_DEFAULT_BASE - 1, 64 * KiB) >> 8 | (1 << 7));
22 /* lowest NP address is HPET at FED00000 */
23 pci_write_config32(_SOC_DEV(0x18, 1), 0x80, (HPET_BASE_ADDRESS >> 8) | 3);
24
25 /* Map the remaining PCI hole as posted MMIO. */
26 pci_write_config32(_SOC_DEV(0x18, 1), 0x8c,
27 ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);
28 pci_write_config32(_SOC_DEV(0x18, 1), 0x88, (get_top_of_mem_below_4gb() >> 8) | 3);
29
30 /* Send all IO (0000-FFFF) to southbridge. */
31 pci_write_config32(_SOC_DEV(0x18, 1), 0xc4, 0x0000f000);
32 pci_write_config32(_SOC_DEV(0x18, 1), 0xc0, 0x00000003);
33 }
34