1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/pci.h>
4 #include <device/pci_ids.h>
5 #include <console/console.h>
6 #include <soc/pci_devs.h>
7 #include <soc/ramstage.h>
8
9 /**
10 * Read the base address registers for a given device.
11 *
12 * @param dev Pointer to the dev structure.
13 * @param howmany How many registers to read.
14 */
pci_read_bases(struct device * dev,unsigned int howmany)15 static void pci_read_bases(struct device *dev, unsigned int howmany)
16 {
17 unsigned long index;
18
19 for (index = PCI_BASE_ADDRESS_0;
20 (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) {
21 struct resource *resource;
22 resource = pci_get_resource(dev, index);
23 /**
24 * Workaround for Denverton-NS silicon (Rev A0/A1 for CSME/IE,
25 * Rev B0 for CSME only)
26 * CSME&IEs KT IO bar must be 16-byte aligned
27 */
28 if ((resource->flags & IORESOURCE_IO) &&
29 (resource->align != 4)) {
30 printk(BIOS_DEBUG,
31 "CSME&IEs KT IO bar must be 16-byte aligned!\n");
32 resource->align = 4;
33 resource->gran = 4;
34 resource->size = 16;
35 }
36 index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4;
37 }
38
39 compact_resources(dev);
40 }
41
pci_csme_ie_kt_read_resources(struct device * dev)42 static void pci_csme_ie_kt_read_resources(struct device *dev)
43 {
44 /**
45 * CSME/IE KT has 2 BARs to check:
46 * 0x10 - KT IO BAR
47 * 0x14 - KT Memory BAR
48 * CSME/IE KT has no Expansion ROM BAR to check:
49 * 0x30 - KT Host XRBAR, READ ONLY
50 */
51 pci_read_bases(dev, 2);
52 }
53
54 static struct device_operations csme_ie_kt_ops = {
55 .read_resources = pci_csme_ie_kt_read_resources,
56 .set_resources = pci_dev_set_resources,
57 .enable_resources = pci_dev_enable_resources,
58 .ops_pci = &soc_pci_ops,
59 };
60
61 static const unsigned short pci_device_ids[] = {
62 PCI_DID_INTEL_DNV_ME_KT,
63 PCI_DID_INTEL_DNV_IE_KT,
64 0
65 };
66
67 static const struct pci_driver csme_ie_kt __pci_driver = {
68 .ops = &csme_ie_kt_ops,
69 .vendor = PCI_VID_INTEL,
70 .devices = pci_device_ids,
71 };
72