1chip soc/intel/alderlake 2 3 # GPE configuration 4 # Note that GPE events called out in ASL code rely on this 5 # route. i.e. If this route changes then the affected GPE 6 # offset bits also need to be changed. 7 register "pmc_gpe0_dw0" = "GPP_B" 8 register "pmc_gpe0_dw1" = "GPP_D" 9 register "pmc_gpe0_dw2" = "GPP_E" 10 11 # FSP configuration 12 13 # Enable CNVi BT 14 register "cnvi_bt_core" = "true" 15 16 # Sagv Configuration 17 register "sagv" = "SaGv_Enabled" 18 19 # Enable DPTF 20 register "dptf_enable" = "1" 21 22 # eMMC HS400 23 register "emmc_enable_hs400_mode" = "1" 24 25 register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 26 register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-C Port2 27 register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # FPS connector 28 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN 29 register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 30 register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # USB3/2 Type A port2 31 register "usb2_ports[6]" = "USB2_PORT_MID(OC1)" # USB3/2 Type A port3 32 register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type A/ M.2 WLAN 33 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth 34 35 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 36 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port2 37 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port3 38 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN 39 40 # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f 41 register "gen1_dec" = "0x00fc0801" 42 register "gen2_dec" = "0x000c0201" 43 # EC memory map range is 0x900-0x9ff 44 register "gen3_dec" = "0x00fc0901" 45 46 # Enable PCH PCIE RP 7 using CLK 3 47 register "pch_pcie_rp[PCH_RP(7)]" = "{ 48 .clk_src = 3, 49 .clk_req = 3, 50 .flags = PCIE_RP_CLK_REQ_DETECT, 51 }" 52 53 # Enable PCH PCIE RP 9 using CLK 0 54 register "pch_pcie_rp[PCH_RP(9)]" = "{ 55 .clk_src = 0, 56 .clk_req = 0, 57 .flags = PCIE_RP_CLK_REQ_DETECT, 58 }" 59 60 register "sata_salp_support" = "0" 61 62 # Enable EDP in PortA 63 register "ddi_portA_config" = "1" 64 # Enable HDMI in Port B 65 register "ddi_ports_config" = "{ 66 [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, 67 }" 68 69 # TCSS USB3 70 register "tcss_aux_ori" = "4" 71 register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_E20, .pad_auxn_dc = GPP_E21}" 72 73 register "s0ix_enable" = "1" 74 75 register "serial_io_i2c_mode" = "{ 76 [PchSerialIoIndexI2C0] = PchSerialIoPci, 77 [PchSerialIoIndexI2C1] = PchSerialIoPci, 78 [PchSerialIoIndexI2C2] = PchSerialIoPci, 79 [PchSerialIoIndexI2C3] = PchSerialIoPci, 80 [PchSerialIoIndexI2C4] = PchSerialIoDisabled, 81 [PchSerialIoIndexI2C5] = PchSerialIoPci, 82 }" 83 84 register "serial_io_gspi_mode" = "{ 85 [PchSerialIoIndexGSPI0] = PchSerialIoPci, 86 [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, 87 [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, 88 [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, 89 }" 90 91 register "serial_io_gspi_cs_mode" = "{ 92 [PchSerialIoIndexGSPI0] = 0, 93 [PchSerialIoIndexGSPI1] = 0, 94 [PchSerialIoIndexGSPI2] = 0, 95 [PchSerialIoIndexGSPI3] = 0, 96 }" 97 98 register "serial_io_gspi_cs_state" = "{ 99 [PchSerialIoIndexGSPI0] = 0, 100 [PchSerialIoIndexGSPI1] = 0, 101 [PchSerialIoIndexGSPI2] = 0, 102 [PchSerialIoIndexGSPI3] = 0, 103 }" 104 105 register "serial_io_uart_mode" = "{ 106 [PchSerialIoIndexUART0] = PchSerialIoSkipInit, 107 [PchSerialIoIndexUART1] = PchSerialIoDisabled, 108 [PchSerialIoIndexUART2] = PchSerialIoDisabled, 109 }" 110 111 # HD Audio 112 register "pch_hda_dsp_enable" = "1" 113 register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" 114 register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" 115 register "pch_hda_idisp_codec_enable" = "1" 116 117 register "cnvi_bt_audio_offload" = "true" 118 119 # Intel Common SoC Config 120 register "common_soc_config" = "{ 121 .i2c[0] = { 122 .speed = I2C_SPEED_FAST, 123 }, 124 .i2c[1] = { 125 .speed = I2C_SPEED_FAST, 126 }, 127 .i2c[2] = { 128 .speed = I2C_SPEED_FAST, 129 }, 130 .i2c[3] = { 131 .speed = I2C_SPEED_FAST, 132 }, 133 .i2c[5] = { 134 .speed = I2C_SPEED_FAST, 135 }, 136 }" 137 138 # Configure external V1P05/Vnn/VnnSx Rails 139 register "ext_fivr_settings" = "{ 140 .configure_ext_fivr = 1, 141 .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, 142 .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, 143 .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, 144 .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, 145 .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, 146 .v1p05_voltage_mv = 1050, 147 .vnn_voltage_mv = 780, 148 .vnn_sx_voltage_mv = 1050, 149 .v1p05_icc_max_ma = 500, 150 .vnn_icc_max_ma = 500, 151 }" 152 153 device domain 0 on 154 device ref igpu on end 155 device ref dtt on 156 chip drivers/intel/dptf 157 158 ## sensor information 159 register "options.tsr[0].desc" = ""Ambient"" 160 register "options.tsr[1].desc" = ""Battery"" 161 register "options.tsr[2].desc" = ""DDR"" 162 register "options.tsr[3].desc" = ""Skin"" 163 register "options.tsr[4].desc" = ""VR"" 164 165 ## Active Policy 166 # TODO: below values are initial reference values only 167 register "policies.active" = "{ 168 [0] = { 169 .target = DPTF_CPU, 170 .thresholds = { 171 TEMP_PCT(95, 90), 172 TEMP_PCT(90, 80), 173 } 174 }, 175 [1] = { 176 .target = DPTF_TEMP_SENSOR_0, 177 .thresholds = { 178 TEMP_PCT(80, 90), 179 TEMP_PCT(70, 80), 180 } 181 } 182 }" 183 184 ## Passive Policy 185 # TODO: below values are initial reference values only 186 register "policies.passive" = "{ 187 [0] = DPTF_PASSIVE(CPU, CPU, 95, 10000), 188 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 50000), 189 [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 50000), 190 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 50000), 191 [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 85, 50000), 192 [5] = DPTF_PASSIVE(CPU, TEMP_SENSOR_4, 85, 50000), 193 }" 194 195 ## Critical Policy 196 # TODO: below values are initial reference values only 197 register "policies.critical" = "{ 198 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), 199 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), 200 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), 201 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), 202 [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN), 203 [5] = DPTF_CRITICAL(TEMP_SENSOR_4, 95, SHUTDOWN), 204 }" 205 206 ## Power Limits Control 207 register "controls.power_limits" = "{ 208 .pl1 = { 209 .min_power = 3000, 210 .max_power = 15000, 211 .time_window_min = 28 * MSECS_PER_SEC, 212 .time_window_max = 32 * MSECS_PER_SEC, 213 .granularity = 200, 214 }, 215 .pl2 = { 216 .min_power = 25000, 217 .max_power = 35000, 218 .time_window_min = 28 * MSECS_PER_SEC, 219 .time_window_max = 32 * MSECS_PER_SEC, 220 .granularity = 1000, 221 } 222 }" 223 224 ## Charger Performance Control (Control, mA) 225 register "controls.charger_perf" = "{ 226 [0] = { 255, 3000 }, 227 [1] = { 24, 1500 }, 228 [2] = { 16, 1000 }, 229 [3] = { 8, 500 } 230 }" 231 232 ## Fan Performance Control (Percent, Speed, Noise, Power) 233 register "controls.fan_perf" = "{ 234 [0] = { 90, 6700, 220, 2200, }, 235 [1] = { 80, 5800, 180, 1800, }, 236 [2] = { 70, 5000, 145, 1450, }, 237 [3] = { 60, 4900, 115, 1150, }, 238 [4] = { 50, 3838, 90, 900, }, 239 [5] = { 40, 2904, 55, 550, }, 240 [6] = { 30, 2337, 30, 300, }, 241 [7] = { 20, 1608, 15, 150, }, 242 [8] = { 10, 800, 10, 100, }, 243 [9] = { 0, 0, 0, 50, } 244 }" 245 246 ## Fan options 247 register "options.fan.fine_grained_control" = "1" 248 register "options.fan.step_size" = "2" 249 250 device generic 0 alias dptf_policy on end 251 end 252 end 253 device ref ipu on 254 chip drivers/intel/mipi_camera 255 register "acpi_uid" = "0x50000" 256 register "acpi_name" = ""IPU0"" 257 register "device_type" = "INTEL_ACPI_CAMERA_CIO2" 258 259 register "cio2_num_ports" = "2" 260 register "cio2_lanes_used" = "{2,2}" 261 register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1"" 262 register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0"" 263 register "cio2_prt[0]" = "2" 264 register "cio2_prt[1]" = "1" 265 device generic 0 on end 266 end 267 end 268 device ref crashlog off end 269 device ref tcss_xhci on end 270 device ref xhci on 271 chip drivers/usb/acpi 272 register "desc" = ""Root Hub"" 273 register "type" = "UPC_TYPE_HUB" 274 device ref xhci_root_hub on 275 chip drivers/usb/acpi 276 register "desc" = ""Bluetooth"" 277 register "type" = "UPC_TYPE_INTERNAL" 278 device ref usb2_port10 on end 279 end 280 end 281 end 282 end 283 device ref cnvi_wifi on 284 chip drivers/wifi/generic 285 register "wake" = "GPE0_PME_B0" 286 device generic 0 on end 287 end 288 end 289 device ref i2c0 on end 290 device ref i2c1 on 291 chip drivers/intel/mipi_camera 292 register "acpi_hid" = ""OVTI5675"" 293 register "acpi_uid" = "0" 294 register "acpi_name" = ""CAM0"" 295 register "chip_name" = ""Ov 5675 Camera"" 296 register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" 297 298 register "ssdb.lanes_used" = "2" 299 register "ssdb.vcm_type" = "0x0C" 300 register "vcm_name" = ""VCM0"" 301 register "num_freq_entries" = "1" 302 register "link_freq[0]" = "450000000" 303 register "remote_name" = ""IPU0"" 304 305 register "has_power_resource" = "1" 306 #Controls 307 register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0 308 register "clk_panel.clks[0].freq" = "1" #19.2 Mhz 309 register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable 310 register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset 311 312 #_ON 313 register "on_seq.ops_cnt" = "4" 314 register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" 315 register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)" 316 register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)" 317 register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)" 318 319 #_OFF 320 register "off_seq.ops_cnt" = "3" 321 register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" 322 register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" 323 register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" 324 325 device i2c 36 on end 326 end 327 chip drivers/intel/mipi_camera 328 register "acpi_uid" = "3" 329 register "acpi_name" = ""VCM0"" 330 register "chip_name" = ""DW AF VCM"" 331 register "device_type" = "INTEL_ACPI_CAMERA_VCM" 332 333 register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC"" 334 register "vcm_compat" = ""dongwoon,dw9714"" 335 336 device i2c 0C on end 337 end 338 end 339 device ref i2c2 on end 340 device ref i2c3 on end 341 device ref heci1 on end 342 device ref sata off end 343 device ref i2c5 on 344 chip drivers/intel/mipi_camera 345 register "acpi_hid" = ""OVTI5675"" 346 register "acpi_uid" = "0" 347 register "acpi_name" = ""CAM1"" 348 register "chip_name" = ""Ov 5675 Camera"" 349 register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" 350 351 register "ssdb.lanes_used" = "2" 352 register "num_freq_entries" = "1" 353 register "link_freq[0]" = "450000000" 354 register "remote_name" = ""IPU0"" 355 356 register "has_power_resource" = "1" 357 #Controls 358 register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1 359 register "clk_panel.clks[0].freq" = "1" #19.2 Mhz 360 register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable 361 register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset 362 363 #_ON 364 register "on_seq.ops_cnt" = "4" 365 register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" 366 register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)" 367 register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)" 368 register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)" 369 370 #_OFF 371 register "off_seq.ops_cnt" = "3" 372 register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" 373 register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" 374 register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" 375 376 device i2c 36 on end 377 end 378 end 379 device ref pcie_rp7 on end 380 device ref pcie_rp9 on end 381 device ref uart0 on end 382 device ref gspi0 on end 383 device ref p2sb on end 384 device ref emmc on end 385 device ref ish on end 386 device ref ufs on end 387 device ref hda on 388 chip drivers/intel/soundwire 389 device generic 0 on 390 chip drivers/soundwire/alc711 391 # SoundWire Link 0 ID 1 392 register "desc" = ""Headset Codec"" 393 device generic 0.1 on end 394 end 395 end 396 end 397 end 398 device ref smbus on end 399 end 400end 401