1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 3 #ifndef __REG_BASE_ADDR__ 4 #define __REG_BASE_ADDR__ 5 6 #include "soc/addressmap.h" 7 #include "emi_hw.h" 8 9 #ifndef __ETT__ 10 #define __ETT__ 0 11 #endif 12 13 //#define DRAM_BASE 0x40000000ULL 14 //#define DDR_BASE DRAM_BASE 15 #define CQ_DMA_BASE (IO_PHYS + 0x212000) 16 //#define CKSYS_BASE IO_PHYS 17 //#define EMI_APB_BASE 0x10219000 18 //#define EMI_BASE EMI_APB_BASE 19 //#define EMI_MPU_BASE 0x10226000 20 #define CHN0_EMI_BASE (IO_PHYS + 0x235000) 21 #define CHN1_EMI_BASE (IO_PHYS + 0x245000) 22 #define INFRA_DRAMC_REG_CONFIG (INFRACFG_AO_BASE + 0xB4) 23 //#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 24 //#define APMIXED_BASE (IO_PHYS + 0x0000C000) 25 26 #define MPLL_CON0 (APMIXED_BASE + 0x390) 27 #define MPLL_CON1 (APMIXED_BASE + 0x394) 28 #define MPLL_CON3 (APMIXED_BASE + 0x39C) 29 30 #define PLLON_CON0 (APMIXED_BASE + 0x050) 31 #define PLLON_CON1 (APMIXED_BASE + 0x054) 32 #define PLLON_CON2 (APMIXED_BASE + 0x058) 33 #define PLLON_CON3 (APMIXED_BASE + 0x05C) 34 35 /* TOPCKGEN Register */ 36 #define CLK_MISC_CFG_0 (CKSYS_BASE + 0x104) 37 #define CLK_MISC_CFG_1 (CKSYS_BASE + 0x108) 38 #define CLK_DBG_CFG (CKSYS_BASE + 0x10C) 39 #define CLK26CALI_0 (CKSYS_BASE + 0x220) 40 #define CLK26CALI_1 (CKSYS_BASE + 0x224) 41 42 #endif //__REG_BASE_ADDR__ 43