1 /*
2 * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <limits.h>
10 #include <stdint.h>
11 #include <stdio.h>
12
13 #include <arch.h>
14 #include <arch_helpers.h>
15 #include "clk-stm32-core.h"
16 #include <common/debug.h>
17 #include <common/fdt_wrappers.h>
18 #include <drivers/clk.h>
19 #include <drivers/delay_timer.h>
20 #include <drivers/st/stm32mp13_rcc.h>
21 #include <drivers/st/stm32mp1_clk.h>
22 #include <drivers/st/stm32mp_clkfunc.h>
23 #include <dt-bindings/clock/stm32mp13-clksrc.h>
24 #include <lib/mmio.h>
25 #include <lib/spinlock.h>
26 #include <lib/utils_def.h>
27 #include <libfdt.h>
28 #include <plat/common/platform.h>
29
30 #include <platform_def.h>
31
32 struct stm32_osci_dt_cfg {
33 unsigned long freq;
34 bool bypass;
35 bool digbyp;
36 bool css;
37 uint32_t drive;
38 };
39
40 enum pll_mn {
41 PLL_CFG_M,
42 PLL_CFG_N,
43 PLL_DIV_MN_NB
44 };
45
46 enum pll_pqr {
47 PLL_CFG_P,
48 PLL_CFG_Q,
49 PLL_CFG_R,
50 PLL_DIV_PQR_NB
51 };
52
53 enum pll_csg {
54 PLL_CSG_MOD_PER,
55 PLL_CSG_INC_STEP,
56 PLL_CSG_SSCG_MODE,
57 PLL_CSG_NB
58 };
59
60 struct stm32_pll_vco {
61 uint32_t status;
62 uint32_t src;
63 uint32_t div_mn[PLL_DIV_MN_NB];
64 uint32_t frac;
65 bool csg_enabled;
66 uint32_t csg[PLL_CSG_NB];
67 };
68
69 struct stm32_pll_output {
70 uint32_t output[PLL_DIV_PQR_NB];
71 };
72
73 struct stm32_pll_dt_cfg {
74 struct stm32_pll_vco vco;
75 struct stm32_pll_output output;
76 };
77
78 struct stm32_clk_platdata {
79 uint32_t nosci;
80 struct stm32_osci_dt_cfg *osci;
81 uint32_t npll;
82 struct stm32_pll_dt_cfg *pll;
83 uint32_t nclksrc;
84 uint32_t *clksrc;
85 uint32_t nclkdiv;
86 uint32_t *clkdiv;
87 };
88
89 enum stm32_clock {
90 /* ROOT CLOCKS */
91 _CK_OFF,
92 _CK_HSI,
93 _CK_HSE,
94 _CK_CSI,
95 _CK_LSI,
96 _CK_LSE,
97 _I2SCKIN,
98 _CSI_DIV122,
99 _HSE_DIV,
100 _HSE_DIV2,
101 _CK_PLL1,
102 _CK_PLL2,
103 _CK_PLL3,
104 _CK_PLL4,
105 _PLL1P,
106 _PLL1P_DIV,
107 _PLL2P,
108 _PLL2Q,
109 _PLL2R,
110 _PLL3P,
111 _PLL3Q,
112 _PLL3R,
113 _PLL4P,
114 _PLL4Q,
115 _PLL4R,
116 _PCLK1,
117 _PCLK2,
118 _PCLK3,
119 _PCLK4,
120 _PCLK5,
121 _PCLK6,
122 _CKMPU,
123 _CKAXI,
124 _CKMLAHB,
125 _CKPER,
126 _CKTIMG1,
127 _CKTIMG2,
128 _CKTIMG3,
129 _USB_PHY_48,
130 _MCO1_K,
131 _MCO2_K,
132 _TRACECK,
133 /* BUS and KERNEL CLOCKS */
134 _DDRC1,
135 _DDRC1LP,
136 _DDRPHYC,
137 _DDRPHYCLP,
138 _DDRCAPB,
139 _DDRCAPBLP,
140 _AXIDCG,
141 _DDRPHYCAPB,
142 _DDRPHYCAPBLP,
143 _SYSCFG,
144 _DDRPERFM,
145 _IWDG2APB,
146 _USBPHY_K,
147 _USBO_K,
148 _RTCAPB,
149 _TZC,
150 _ETZPC,
151 _IWDG1APB,
152 _BSEC,
153 _STGENC,
154 _USART1_K,
155 _USART2_K,
156 _I2C3_K,
157 _I2C4_K,
158 _I2C5_K,
159 _TIM12,
160 _TIM15,
161 _RTCCK,
162 _GPIOA,
163 _GPIOB,
164 _GPIOC,
165 _GPIOD,
166 _GPIOE,
167 _GPIOF,
168 _GPIOG,
169 _GPIOH,
170 _GPIOI,
171 _PKA,
172 _SAES_K,
173 _CRYP1,
174 _HASH1,
175 _RNG1_K,
176 _BKPSRAM,
177 _SDMMC1_K,
178 _SDMMC2_K,
179 _DBGCK,
180 _USART3_K,
181 _UART4_K,
182 _UART5_K,
183 _UART7_K,
184 _UART8_K,
185 _USART6_K,
186 _MCE,
187 _FMC_K,
188 _QSPI_K,
189
190 CK_LAST
191 };
192
193 /* PARENT CONFIG */
194 static const uint16_t RTC_src[] = {
195 _CK_OFF, _CK_LSE, _CK_LSI, _CK_HSE
196 };
197
198 static const uint16_t MCO1_src[] = {
199 _CK_HSI, _CK_HSE, _CK_CSI, _CK_LSI, _CK_LSE
200 };
201
202 static const uint16_t MCO2_src[] = {
203 _CKMPU, _CKAXI, _CKMLAHB, _PLL4P, _CK_HSE, _CK_HSI
204 };
205
206 static const uint16_t PLL12_src[] = {
207 _CK_HSI, _CK_HSE
208 };
209
210 static const uint16_t PLL3_src[] = {
211 _CK_HSI, _CK_HSE, _CK_CSI
212 };
213
214 static const uint16_t PLL4_src[] = {
215 _CK_HSI, _CK_HSE, _CK_CSI, _I2SCKIN
216 };
217
218 static const uint16_t MPU_src[] = {
219 _CK_HSI, _CK_HSE, _PLL1P, _PLL1P_DIV
220 };
221
222 static const uint16_t AXI_src[] = {
223 _CK_HSI, _CK_HSE, _PLL2P
224 };
225
226 static const uint16_t MLAHBS_src[] = {
227 _CK_HSI, _CK_HSE, _CK_CSI, _PLL3P
228 };
229
230 static const uint16_t CKPER_src[] = {
231 _CK_HSI, _CK_CSI, _CK_HSE, _CK_OFF
232 };
233
234 static const uint16_t I2C12_src[] = {
235 _PCLK1, _PLL4R, _CK_HSI, _CK_CSI
236 };
237
238 static const uint16_t I2C3_src[] = {
239 _PCLK6, _PLL4R, _CK_HSI, _CK_CSI
240 };
241
242 static const uint16_t I2C4_src[] = {
243 _PCLK6, _PLL4R, _CK_HSI, _CK_CSI
244 };
245
246 static const uint16_t I2C5_src[] = {
247 _PCLK6, _PLL4R, _CK_HSI, _CK_CSI
248 };
249
250 static const uint16_t SPI1_src[] = {
251 _PLL4P, _PLL3Q, _I2SCKIN, _CKPER, _PLL3R
252 };
253
254 static const uint16_t SPI23_src[] = {
255 _PLL4P, _PLL3Q, _I2SCKIN, _CKPER, _PLL3R
256 };
257
258 static const uint16_t SPI4_src[] = {
259 _PCLK6, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE, _I2SCKIN
260 };
261
262 static const uint16_t SPI5_src[] = {
263 _PCLK6, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE
264 };
265
266 static const uint16_t UART1_src[] = {
267 _PCLK6, _PLL3Q, _CK_HSI, _CK_CSI, _PLL4Q, _CK_HSE
268 };
269
270 static const uint16_t UART2_src[] = {
271 _PCLK6, _PLL3Q, _CK_HSI, _CK_CSI, _PLL4Q, _CK_HSE
272 };
273
274 static const uint16_t UART35_src[] = {
275 _PCLK1, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE
276 };
277
278 static const uint16_t UART4_src[] = {
279 _PCLK1, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE
280 };
281
282 static const uint16_t UART6_src[] = {
283 _PCLK2, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE
284 };
285
286 static const uint16_t UART78_src[] = {
287 _PCLK1, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE
288 };
289
290 static const uint16_t LPTIM1_src[] = {
291 _PCLK1, _PLL4P, _PLL3Q, _CK_LSE, _CK_LSI, _CKPER
292 };
293
294 static const uint16_t LPTIM2_src[] = {
295 _PCLK3, _PLL4Q, _CKPER, _CK_LSE, _CK_LSI
296 };
297
298 static const uint16_t LPTIM3_src[] = {
299 _PCLK3, _PLL4Q, _CKPER, _CK_LSE, _CK_LSI
300 };
301
302 static const uint16_t LPTIM45_src[] = {
303 _PCLK3, _PLL4P, _PLL3Q, _CK_LSE, _CK_LSI, _CKPER
304 };
305
306 static const uint16_t SAI1_src[] = {
307 _PLL4Q, _PLL3Q, _I2SCKIN, _CKPER, _PLL3R
308 };
309
310 static const uint16_t SAI2_src[] = {
311 _PLL4Q, _PLL3Q, _I2SCKIN, _CKPER, _NO_ID, _PLL3R
312 };
313
314 static const uint16_t FDCAN_src[] = {
315 _CK_HSE, _PLL3Q, _PLL4Q, _PLL4R
316 };
317
318 static const uint16_t SPDIF_src[] = {
319 _PLL4P, _PLL3Q, _CK_HSI
320 };
321
322 static const uint16_t ADC1_src[] = {
323 _PLL4R, _CKPER, _PLL3Q
324 };
325
326 static const uint16_t ADC2_src[] = {
327 _PLL4R, _CKPER, _PLL3Q
328 };
329
330 static const uint16_t SDMMC1_src[] = {
331 _CKAXI, _PLL3R, _PLL4P, _CK_HSI
332 };
333
334 static const uint16_t SDMMC2_src[] = {
335 _CKAXI, _PLL3R, _PLL4P, _CK_HSI
336 };
337
338 static const uint16_t ETH1_src[] = {
339 _PLL4P, _PLL3Q
340 };
341
342 static const uint16_t ETH2_src[] = {
343 _PLL4P, _PLL3Q
344 };
345
346 static const uint16_t USBPHY_src[] = {
347 _CK_HSE, _PLL4R, _HSE_DIV2
348 };
349
350 static const uint16_t USBO_src[] = {
351 _PLL4R, _USB_PHY_48
352 };
353
354 static const uint16_t QSPI_src[] = {
355 _CKAXI, _PLL3R, _PLL4P, _CKPER
356 };
357
358 static const uint16_t FMC_src[] = {
359 _CKAXI, _PLL3R, _PLL4P, _CKPER
360 };
361
362 /* Position 2 of RNG1 mux is reserved */
363 static const uint16_t RNG1_src[] = {
364 _CK_CSI, _PLL4R, _CK_OFF, _CK_LSI
365 };
366
367 static const uint16_t STGEN_src[] = {
368 _CK_HSI, _CK_HSE
369 };
370
371 static const uint16_t DCMIPP_src[] = {
372 _CKAXI, _PLL2Q, _PLL4P, _CKPER
373 };
374
375 static const uint16_t SAES_src[] = {
376 _CKAXI, _CKPER, _PLL4R, _CK_LSI
377 };
378
379 #define MUX_CFG(id, src, _offset, _shift, _witdh)[id] = {\
380 .id_parents = src,\
381 .num_parents = ARRAY_SIZE(src),\
382 .mux = &(struct mux_cfg) {\
383 .offset = (_offset),\
384 .shift = (_shift),\
385 .width = (_witdh),\
386 .bitrdy = MUX_NO_BIT_RDY,\
387 },\
388 }
389
390 #define MUX_RDY_CFG(id, src, _offset, _shift, _witdh)[id] = {\
391 .id_parents = src,\
392 .num_parents = ARRAY_SIZE(src),\
393 .mux = &(struct mux_cfg) {\
394 .offset = (_offset),\
395 .shift = (_shift),\
396 .width = (_witdh),\
397 .bitrdy = 31,\
398 },\
399 }
400
401 static const struct parent_cfg parent_mp13[MUX_MAX] = {
402 MUX_CFG(MUX_ADC1, ADC1_src, RCC_ADC12CKSELR, 0, 2),
403 MUX_CFG(MUX_ADC2, ADC2_src, RCC_ADC12CKSELR, 2, 2),
404 MUX_RDY_CFG(MUX_AXI, AXI_src, RCC_ASSCKSELR, 0, 3),
405 MUX_CFG(MUX_CKPER, CKPER_src, RCC_CPERCKSELR, 0, 2),
406 MUX_CFG(MUX_DCMIPP, DCMIPP_src, RCC_DCMIPPCKSELR, 0, 2),
407 MUX_CFG(MUX_ETH1, ETH1_src, RCC_ETH12CKSELR, 0, 2),
408 MUX_CFG(MUX_ETH2, ETH2_src, RCC_ETH12CKSELR, 8, 2),
409 MUX_CFG(MUX_FDCAN, FDCAN_src, RCC_FDCANCKSELR, 0, 2),
410 MUX_CFG(MUX_FMC, FMC_src, RCC_FMCCKSELR, 0, 2),
411 MUX_CFG(MUX_I2C12, I2C12_src, RCC_I2C12CKSELR, 0, 3),
412 MUX_CFG(MUX_I2C3, I2C3_src, RCC_I2C345CKSELR, 0, 3),
413 MUX_CFG(MUX_I2C4, I2C4_src, RCC_I2C345CKSELR, 3, 3),
414 MUX_CFG(MUX_I2C5, I2C5_src, RCC_I2C345CKSELR, 6, 3),
415 MUX_CFG(MUX_LPTIM1, LPTIM1_src, RCC_LPTIM1CKSELR, 0, 3),
416 MUX_CFG(MUX_LPTIM2, LPTIM2_src, RCC_LPTIM23CKSELR, 0, 3),
417 MUX_CFG(MUX_LPTIM3, LPTIM3_src, RCC_LPTIM23CKSELR, 3, 3),
418 MUX_CFG(MUX_LPTIM45, LPTIM45_src, RCC_LPTIM45CKSELR, 0, 3),
419 MUX_CFG(MUX_MCO1, MCO1_src, RCC_MCO1CFGR, 0, 3),
420 MUX_CFG(MUX_MCO2, MCO2_src, RCC_MCO2CFGR, 0, 3),
421 MUX_RDY_CFG(MUX_MLAHB, MLAHBS_src, RCC_MSSCKSELR, 0, 2),
422 MUX_RDY_CFG(MUX_MPU, MPU_src, RCC_MPCKSELR, 0, 2),
423 MUX_RDY_CFG(MUX_PLL12, PLL12_src, RCC_RCK12SELR, 0, 2),
424 MUX_RDY_CFG(MUX_PLL3, PLL3_src, RCC_RCK3SELR, 0, 2),
425 MUX_RDY_CFG(MUX_PLL4, PLL4_src, RCC_RCK4SELR, 0, 2),
426 MUX_CFG(MUX_QSPI, QSPI_src, RCC_QSPICKSELR, 0, 2),
427 MUX_CFG(MUX_RNG1, RNG1_src, RCC_RNG1CKSELR, 0, 2),
428 MUX_CFG(MUX_RTC, RTC_src, RCC_BDCR, 16, 2),
429 MUX_CFG(MUX_SAES, SAES_src, RCC_SAESCKSELR, 0, 2),
430 MUX_CFG(MUX_SAI1, SAI1_src, RCC_SAI1CKSELR, 0, 3),
431 MUX_CFG(MUX_SAI2, SAI2_src, RCC_SAI2CKSELR, 0, 3),
432 MUX_CFG(MUX_SDMMC1, SDMMC1_src, RCC_SDMMC12CKSELR, 0, 3),
433 MUX_CFG(MUX_SDMMC2, SDMMC2_src, RCC_SDMMC12CKSELR, 3, 3),
434 MUX_CFG(MUX_SPDIF, SPDIF_src, RCC_SPDIFCKSELR, 0, 2),
435 MUX_CFG(MUX_SPI1, SPI1_src, RCC_SPI2S1CKSELR, 0, 3),
436 MUX_CFG(MUX_SPI23, SPI23_src, RCC_SPI2S23CKSELR, 0, 3),
437 MUX_CFG(MUX_SPI4, SPI4_src, RCC_SPI45CKSELR, 0, 3),
438 MUX_CFG(MUX_SPI5, SPI5_src, RCC_SPI45CKSELR, 3, 3),
439 MUX_CFG(MUX_STGEN, STGEN_src, RCC_STGENCKSELR, 0, 2),
440 MUX_CFG(MUX_UART1, UART1_src, RCC_UART12CKSELR, 0, 3),
441 MUX_CFG(MUX_UART2, UART2_src, RCC_UART12CKSELR, 3, 3),
442 MUX_CFG(MUX_UART35, UART35_src, RCC_UART35CKSELR, 0, 3),
443 MUX_CFG(MUX_UART4, UART4_src, RCC_UART4CKSELR, 0, 3),
444 MUX_CFG(MUX_UART6, UART6_src, RCC_UART6CKSELR, 0, 3),
445 MUX_CFG(MUX_UART78, UART78_src, RCC_UART78CKSELR, 0, 3),
446 MUX_CFG(MUX_USBO, USBO_src, RCC_USBCKSELR, 4, 1),
447 MUX_CFG(MUX_USBPHY, USBPHY_src, RCC_USBCKSELR, 0, 2),
448 };
449
450 /*
451 * GATE CONFIG
452 */
453
454 enum enum_gate_cfg {
455 GATE_ZERO, /* reserved for no gate */
456 GATE_LSE,
457 GATE_RTCCK,
458 GATE_LSI,
459 GATE_HSI,
460 GATE_CSI,
461 GATE_HSE,
462 GATE_LSI_RDY,
463 GATE_CSI_RDY,
464 GATE_LSE_RDY,
465 GATE_HSE_RDY,
466 GATE_HSI_RDY,
467 GATE_MCO1,
468 GATE_MCO2,
469 GATE_DBGCK,
470 GATE_TRACECK,
471 GATE_PLL1,
472 GATE_PLL1_DIVP,
473 GATE_PLL1_DIVQ,
474 GATE_PLL1_DIVR,
475 GATE_PLL2,
476 GATE_PLL2_DIVP,
477 GATE_PLL2_DIVQ,
478 GATE_PLL2_DIVR,
479 GATE_PLL3,
480 GATE_PLL3_DIVP,
481 GATE_PLL3_DIVQ,
482 GATE_PLL3_DIVR,
483 GATE_PLL4,
484 GATE_PLL4_DIVP,
485 GATE_PLL4_DIVQ,
486 GATE_PLL4_DIVR,
487 GATE_DDRC1,
488 GATE_DDRC1LP,
489 GATE_DDRPHYC,
490 GATE_DDRPHYCLP,
491 GATE_DDRCAPB,
492 GATE_DDRCAPBLP,
493 GATE_AXIDCG,
494 GATE_DDRPHYCAPB,
495 GATE_DDRPHYCAPBLP,
496 GATE_TIM2,
497 GATE_TIM3,
498 GATE_TIM4,
499 GATE_TIM5,
500 GATE_TIM6,
501 GATE_TIM7,
502 GATE_LPTIM1,
503 GATE_SPI2,
504 GATE_SPI3,
505 GATE_USART3,
506 GATE_UART4,
507 GATE_UART5,
508 GATE_UART7,
509 GATE_UART8,
510 GATE_I2C1,
511 GATE_I2C2,
512 GATE_SPDIF,
513 GATE_TIM1,
514 GATE_TIM8,
515 GATE_SPI1,
516 GATE_USART6,
517 GATE_SAI1,
518 GATE_SAI2,
519 GATE_DFSDM,
520 GATE_ADFSDM,
521 GATE_FDCAN,
522 GATE_LPTIM2,
523 GATE_LPTIM3,
524 GATE_LPTIM4,
525 GATE_LPTIM5,
526 GATE_VREF,
527 GATE_DTS,
528 GATE_PMBCTRL,
529 GATE_HDP,
530 GATE_SYSCFG,
531 GATE_DCMIPP,
532 GATE_DDRPERFM,
533 GATE_IWDG2APB,
534 GATE_USBPHY,
535 GATE_STGENRO,
536 GATE_LTDC,
537 GATE_RTCAPB,
538 GATE_TZC,
539 GATE_ETZPC,
540 GATE_IWDG1APB,
541 GATE_BSEC,
542 GATE_STGENC,
543 GATE_USART1,
544 GATE_USART2,
545 GATE_SPI4,
546 GATE_SPI5,
547 GATE_I2C3,
548 GATE_I2C4,
549 GATE_I2C5,
550 GATE_TIM12,
551 GATE_TIM13,
552 GATE_TIM14,
553 GATE_TIM15,
554 GATE_TIM16,
555 GATE_TIM17,
556 GATE_DMA1,
557 GATE_DMA2,
558 GATE_DMAMUX1,
559 GATE_DMA3,
560 GATE_DMAMUX2,
561 GATE_ADC1,
562 GATE_ADC2,
563 GATE_USBO,
564 GATE_TSC,
565 GATE_GPIOA,
566 GATE_GPIOB,
567 GATE_GPIOC,
568 GATE_GPIOD,
569 GATE_GPIOE,
570 GATE_GPIOF,
571 GATE_GPIOG,
572 GATE_GPIOH,
573 GATE_GPIOI,
574 GATE_PKA,
575 GATE_SAES,
576 GATE_CRYP1,
577 GATE_HASH1,
578 GATE_RNG1,
579 GATE_BKPSRAM,
580 GATE_AXIMC,
581 GATE_MCE,
582 GATE_ETH1CK,
583 GATE_ETH1TX,
584 GATE_ETH1RX,
585 GATE_ETH1MAC,
586 GATE_FMC,
587 GATE_QSPI,
588 GATE_SDMMC1,
589 GATE_SDMMC2,
590 GATE_CRC1,
591 GATE_USBH,
592 GATE_ETH2CK,
593 GATE_ETH2TX,
594 GATE_ETH2RX,
595 GATE_ETH2MAC,
596 GATE_MDMA,
597
598 LAST_GATE
599 };
600
601 #define GATE_CFG(id, _offset, _bit_idx, _offset_clr)[id] = {\
602 .offset = (_offset),\
603 .bit_idx = (_bit_idx),\
604 .set_clr = (_offset_clr),\
605 }
606
607 static const struct gate_cfg gates_mp13[LAST_GATE] = {
608 GATE_CFG(GATE_LSE, RCC_BDCR, 0, 0),
609 GATE_CFG(GATE_RTCCK, RCC_BDCR, 20, 0),
610 GATE_CFG(GATE_LSI, RCC_RDLSICR, 0, 0),
611 GATE_CFG(GATE_HSI, RCC_OCENSETR, 0, 1),
612 GATE_CFG(GATE_CSI, RCC_OCENSETR, 4, 1),
613 GATE_CFG(GATE_HSE, RCC_OCENSETR, 8, 1),
614 GATE_CFG(GATE_LSI_RDY, RCC_RDLSICR, 1, 0),
615 GATE_CFG(GATE_CSI_RDY, RCC_OCRDYR, 4, 0),
616 GATE_CFG(GATE_LSE_RDY, RCC_BDCR, 2, 0),
617 GATE_CFG(GATE_HSE_RDY, RCC_OCRDYR, 8, 0),
618 GATE_CFG(GATE_HSI_RDY, RCC_OCRDYR, 0, 0),
619 GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 12, 0),
620 GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 12, 0),
621 GATE_CFG(GATE_DBGCK, RCC_DBGCFGR, 8, 0),
622 GATE_CFG(GATE_TRACECK, RCC_DBGCFGR, 9, 0),
623 GATE_CFG(GATE_PLL1, RCC_PLL1CR, 0, 0),
624 GATE_CFG(GATE_PLL1_DIVP, RCC_PLL1CR, 4, 0),
625 GATE_CFG(GATE_PLL1_DIVQ, RCC_PLL1CR, 5, 0),
626 GATE_CFG(GATE_PLL1_DIVR, RCC_PLL1CR, 6, 0),
627 GATE_CFG(GATE_PLL2, RCC_PLL2CR, 0, 0),
628 GATE_CFG(GATE_PLL2_DIVP, RCC_PLL2CR, 4, 0),
629 GATE_CFG(GATE_PLL2_DIVQ, RCC_PLL2CR, 5, 0),
630 GATE_CFG(GATE_PLL2_DIVR, RCC_PLL2CR, 6, 0),
631 GATE_CFG(GATE_PLL3, RCC_PLL3CR, 0, 0),
632 GATE_CFG(GATE_PLL3_DIVP, RCC_PLL3CR, 4, 0),
633 GATE_CFG(GATE_PLL3_DIVQ, RCC_PLL3CR, 5, 0),
634 GATE_CFG(GATE_PLL3_DIVR, RCC_PLL3CR, 6, 0),
635 GATE_CFG(GATE_PLL4, RCC_PLL4CR, 0, 0),
636 GATE_CFG(GATE_PLL4_DIVP, RCC_PLL4CR, 4, 0),
637 GATE_CFG(GATE_PLL4_DIVQ, RCC_PLL4CR, 5, 0),
638 GATE_CFG(GATE_PLL4_DIVR, RCC_PLL4CR, 6, 0),
639 GATE_CFG(GATE_DDRC1, RCC_DDRITFCR, 0, 0),
640 GATE_CFG(GATE_DDRC1LP, RCC_DDRITFCR, 1, 0),
641 GATE_CFG(GATE_DDRPHYC, RCC_DDRITFCR, 4, 0),
642 GATE_CFG(GATE_DDRPHYCLP, RCC_DDRITFCR, 5, 0),
643 GATE_CFG(GATE_DDRCAPB, RCC_DDRITFCR, 6, 0),
644 GATE_CFG(GATE_DDRCAPBLP, RCC_DDRITFCR, 7, 0),
645 GATE_CFG(GATE_AXIDCG, RCC_DDRITFCR, 8, 0),
646 GATE_CFG(GATE_DDRPHYCAPB, RCC_DDRITFCR, 9, 0),
647 GATE_CFG(GATE_DDRPHYCAPBLP, RCC_DDRITFCR, 10, 0),
648 GATE_CFG(GATE_TIM2, RCC_MP_APB1ENSETR, 0, 1),
649 GATE_CFG(GATE_TIM3, RCC_MP_APB1ENSETR, 1, 1),
650 GATE_CFG(GATE_TIM4, RCC_MP_APB1ENSETR, 2, 1),
651 GATE_CFG(GATE_TIM5, RCC_MP_APB1ENSETR, 3, 1),
652 GATE_CFG(GATE_TIM6, RCC_MP_APB1ENSETR, 4, 1),
653 GATE_CFG(GATE_TIM7, RCC_MP_APB1ENSETR, 5, 1),
654 GATE_CFG(GATE_LPTIM1, RCC_MP_APB1ENSETR, 9, 1),
655 GATE_CFG(GATE_SPI2, RCC_MP_APB1ENSETR, 11, 1),
656 GATE_CFG(GATE_SPI3, RCC_MP_APB1ENSETR, 12, 1),
657 GATE_CFG(GATE_USART3, RCC_MP_APB1ENSETR, 15, 1),
658 GATE_CFG(GATE_UART4, RCC_MP_APB1ENSETR, 16, 1),
659 GATE_CFG(GATE_UART5, RCC_MP_APB1ENSETR, 17, 1),
660 GATE_CFG(GATE_UART7, RCC_MP_APB1ENSETR, 18, 1),
661 GATE_CFG(GATE_UART8, RCC_MP_APB1ENSETR, 19, 1),
662 GATE_CFG(GATE_I2C1, RCC_MP_APB1ENSETR, 21, 1),
663 GATE_CFG(GATE_I2C2, RCC_MP_APB1ENSETR, 22, 1),
664 GATE_CFG(GATE_SPDIF, RCC_MP_APB1ENSETR, 26, 1),
665 GATE_CFG(GATE_TIM1, RCC_MP_APB2ENSETR, 0, 1),
666 GATE_CFG(GATE_TIM8, RCC_MP_APB2ENSETR, 1, 1),
667 GATE_CFG(GATE_SPI1, RCC_MP_APB2ENSETR, 8, 1),
668 GATE_CFG(GATE_USART6, RCC_MP_APB2ENSETR, 13, 1),
669 GATE_CFG(GATE_SAI1, RCC_MP_APB2ENSETR, 16, 1),
670 GATE_CFG(GATE_SAI2, RCC_MP_APB2ENSETR, 17, 1),
671 GATE_CFG(GATE_DFSDM, RCC_MP_APB2ENSETR, 20, 1),
672 GATE_CFG(GATE_ADFSDM, RCC_MP_APB2ENSETR, 21, 1),
673 GATE_CFG(GATE_FDCAN, RCC_MP_APB2ENSETR, 24, 1),
674 GATE_CFG(GATE_LPTIM2, RCC_MP_APB3ENSETR, 0, 1),
675 GATE_CFG(GATE_LPTIM3, RCC_MP_APB3ENSETR, 1, 1),
676 GATE_CFG(GATE_LPTIM4, RCC_MP_APB3ENSETR, 2, 1),
677 GATE_CFG(GATE_LPTIM5, RCC_MP_APB3ENSETR, 3, 1),
678 GATE_CFG(GATE_VREF, RCC_MP_APB3ENSETR, 13, 1),
679 GATE_CFG(GATE_DTS, RCC_MP_APB3ENSETR, 16, 1),
680 GATE_CFG(GATE_PMBCTRL, RCC_MP_APB3ENSETR, 17, 1),
681 GATE_CFG(GATE_HDP, RCC_MP_APB3ENSETR, 20, 1),
682 GATE_CFG(GATE_SYSCFG, RCC_MP_S_APB3ENSETR, 0, 1),
683 GATE_CFG(GATE_DCMIPP, RCC_MP_APB4ENSETR, 1, 1),
684 GATE_CFG(GATE_DDRPERFM, RCC_MP_APB4ENSETR, 8, 1),
685 GATE_CFG(GATE_IWDG2APB, RCC_MP_APB4ENSETR, 15, 1),
686 GATE_CFG(GATE_USBPHY, RCC_MP_APB4ENSETR, 16, 1),
687 GATE_CFG(GATE_STGENRO, RCC_MP_APB4ENSETR, 20, 1),
688 GATE_CFG(GATE_LTDC, RCC_MP_S_APB4ENSETR, 0, 1),
689 GATE_CFG(GATE_RTCAPB, RCC_MP_APB5ENSETR, 8, 1),
690 GATE_CFG(GATE_TZC, RCC_MP_APB5ENSETR, 11, 1),
691 GATE_CFG(GATE_ETZPC, RCC_MP_APB5ENSETR, 13, 1),
692 GATE_CFG(GATE_IWDG1APB, RCC_MP_APB5ENSETR, 15, 1),
693 GATE_CFG(GATE_BSEC, RCC_MP_APB5ENSETR, 16, 1),
694 GATE_CFG(GATE_STGENC, RCC_MP_APB5ENSETR, 20, 1),
695 GATE_CFG(GATE_USART1, RCC_MP_APB6ENSETR, 0, 1),
696 GATE_CFG(GATE_USART2, RCC_MP_APB6ENSETR, 1, 1),
697 GATE_CFG(GATE_SPI4, RCC_MP_APB6ENSETR, 2, 1),
698 GATE_CFG(GATE_SPI5, RCC_MP_APB6ENSETR, 3, 1),
699 GATE_CFG(GATE_I2C3, RCC_MP_APB6ENSETR, 4, 1),
700 GATE_CFG(GATE_I2C4, RCC_MP_APB6ENSETR, 5, 1),
701 GATE_CFG(GATE_I2C5, RCC_MP_APB6ENSETR, 6, 1),
702 GATE_CFG(GATE_TIM12, RCC_MP_APB6ENSETR, 7, 1),
703 GATE_CFG(GATE_TIM13, RCC_MP_APB6ENSETR, 8, 1),
704 GATE_CFG(GATE_TIM14, RCC_MP_APB6ENSETR, 9, 1),
705 GATE_CFG(GATE_TIM15, RCC_MP_APB6ENSETR, 10, 1),
706 GATE_CFG(GATE_TIM16, RCC_MP_APB6ENSETR, 11, 1),
707 GATE_CFG(GATE_TIM17, RCC_MP_APB6ENSETR, 12, 1),
708 GATE_CFG(GATE_DMA1, RCC_MP_AHB2ENSETR, 0, 1),
709 GATE_CFG(GATE_DMA2, RCC_MP_AHB2ENSETR, 1, 1),
710 GATE_CFG(GATE_DMAMUX1, RCC_MP_AHB2ENSETR, 2, 1),
711 GATE_CFG(GATE_DMA3, RCC_MP_AHB2ENSETR, 3, 1),
712 GATE_CFG(GATE_DMAMUX2, RCC_MP_AHB2ENSETR, 4, 1),
713 GATE_CFG(GATE_ADC1, RCC_MP_AHB2ENSETR, 5, 1),
714 GATE_CFG(GATE_ADC2, RCC_MP_AHB2ENSETR, 6, 1),
715 GATE_CFG(GATE_USBO, RCC_MP_AHB2ENSETR, 8, 1),
716 GATE_CFG(GATE_TSC, RCC_MP_AHB4ENSETR, 15, 1),
717
718 GATE_CFG(GATE_GPIOA, RCC_MP_S_AHB4ENSETR, 0, 1),
719 GATE_CFG(GATE_GPIOB, RCC_MP_S_AHB4ENSETR, 1, 1),
720 GATE_CFG(GATE_GPIOC, RCC_MP_S_AHB4ENSETR, 2, 1),
721 GATE_CFG(GATE_GPIOD, RCC_MP_S_AHB4ENSETR, 3, 1),
722 GATE_CFG(GATE_GPIOE, RCC_MP_S_AHB4ENSETR, 4, 1),
723 GATE_CFG(GATE_GPIOF, RCC_MP_S_AHB4ENSETR, 5, 1),
724 GATE_CFG(GATE_GPIOG, RCC_MP_S_AHB4ENSETR, 6, 1),
725 GATE_CFG(GATE_GPIOH, RCC_MP_S_AHB4ENSETR, 7, 1),
726 GATE_CFG(GATE_GPIOI, RCC_MP_S_AHB4ENSETR, 8, 1),
727
728 GATE_CFG(GATE_PKA, RCC_MP_AHB5ENSETR, 2, 1),
729 GATE_CFG(GATE_SAES, RCC_MP_AHB5ENSETR, 3, 1),
730 GATE_CFG(GATE_CRYP1, RCC_MP_AHB5ENSETR, 4, 1),
731 GATE_CFG(GATE_HASH1, RCC_MP_AHB5ENSETR, 5, 1),
732 GATE_CFG(GATE_RNG1, RCC_MP_AHB5ENSETR, 6, 1),
733 GATE_CFG(GATE_BKPSRAM, RCC_MP_AHB5ENSETR, 8, 1),
734 GATE_CFG(GATE_AXIMC, RCC_MP_AHB5ENSETR, 16, 1),
735 GATE_CFG(GATE_MCE, RCC_MP_AHB6ENSETR, 1, 1),
736 GATE_CFG(GATE_ETH1CK, RCC_MP_AHB6ENSETR, 7, 1),
737 GATE_CFG(GATE_ETH1TX, RCC_MP_AHB6ENSETR, 8, 1),
738 GATE_CFG(GATE_ETH1RX, RCC_MP_AHB6ENSETR, 9, 1),
739 GATE_CFG(GATE_ETH1MAC, RCC_MP_AHB6ENSETR, 10, 1),
740 GATE_CFG(GATE_FMC, RCC_MP_AHB6ENSETR, 12, 1),
741 GATE_CFG(GATE_QSPI, RCC_MP_AHB6ENSETR, 14, 1),
742 GATE_CFG(GATE_SDMMC1, RCC_MP_AHB6ENSETR, 16, 1),
743 GATE_CFG(GATE_SDMMC2, RCC_MP_AHB6ENSETR, 17, 1),
744 GATE_CFG(GATE_CRC1, RCC_MP_AHB6ENSETR, 20, 1),
745 GATE_CFG(GATE_USBH, RCC_MP_AHB6ENSETR, 24, 1),
746 GATE_CFG(GATE_ETH2CK, RCC_MP_AHB6ENSETR, 27, 1),
747 GATE_CFG(GATE_ETH2TX, RCC_MP_AHB6ENSETR, 28, 1),
748 GATE_CFG(GATE_ETH2RX, RCC_MP_AHB6ENSETR, 29, 1),
749 GATE_CFG(GATE_ETH2MAC, RCC_MP_AHB6ENSETR, 30, 1),
750 GATE_CFG(GATE_MDMA, RCC_MP_S_AHB6ENSETR, 0, 1),
751 };
752
753 /*
754 * DIV CONFIG
755 */
756
757 static const struct clk_div_table axi_div_table[] = {
758 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
759 { 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 },
760 { 0 },
761 };
762
763 static const struct clk_div_table mlahb_div_table[] = {
764 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
765 { 4, 16 }, { 5, 32 }, { 6, 64 }, { 7, 128 },
766 { 8, 256 }, { 9, 512 }, { 10, 512}, { 11, 512 },
767 { 12, 512 }, { 13, 512 }, { 14, 512}, { 15, 512 },
768 { 0 },
769 };
770
771 static const struct clk_div_table apb_div_table[] = {
772 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
773 { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
774 { 0 },
775 };
776
777 #define DIV_CFG(id, _offset, _shift, _width, _flags, _table, _bitrdy)[id] = {\
778 .offset = _offset,\
779 .shift = _shift,\
780 .width = _width,\
781 .flags = _flags,\
782 .table = _table,\
783 .bitrdy = _bitrdy,\
784 }
785
786 static const struct div_cfg dividers_mp13[DIV_MAX] = {
787 DIV_CFG(DIV_PLL1DIVP, RCC_PLL1CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY),
788 DIV_CFG(DIV_PLL2DIVP, RCC_PLL2CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY),
789 DIV_CFG(DIV_PLL2DIVQ, RCC_PLL2CFGR2, 8, 7, 0, NULL, DIV_NO_BIT_RDY),
790 DIV_CFG(DIV_PLL2DIVR, RCC_PLL2CFGR2, 16, 7, 0, NULL, DIV_NO_BIT_RDY),
791 DIV_CFG(DIV_PLL3DIVP, RCC_PLL3CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY),
792 DIV_CFG(DIV_PLL3DIVQ, RCC_PLL3CFGR2, 8, 7, 0, NULL, DIV_NO_BIT_RDY),
793 DIV_CFG(DIV_PLL3DIVR, RCC_PLL3CFGR2, 16, 7, 0, NULL, DIV_NO_BIT_RDY),
794 DIV_CFG(DIV_PLL4DIVP, RCC_PLL4CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY),
795 DIV_CFG(DIV_PLL4DIVQ, RCC_PLL4CFGR2, 8, 7, 0, NULL, DIV_NO_BIT_RDY),
796 DIV_CFG(DIV_PLL4DIVR, RCC_PLL4CFGR2, 16, 7, 0, NULL, DIV_NO_BIT_RDY),
797 DIV_CFG(DIV_MPU, RCC_MPCKDIVR, 0, 4, 0, NULL, DIV_NO_BIT_RDY),
798 DIV_CFG(DIV_AXI, RCC_AXIDIVR, 0, 3, 0, axi_div_table, 31),
799 DIV_CFG(DIV_MLAHB, RCC_MLAHBDIVR, 0, 4, 0, mlahb_div_table, 31),
800 DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table, 31),
801 DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table, 31),
802 DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table, 31),
803 DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table, 31),
804 DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 0, apb_div_table, 31),
805 DIV_CFG(DIV_APB6, RCC_APB6DIVR, 0, 3, 0, apb_div_table, 31),
806 DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, DIV_NO_BIT_RDY),
807 DIV_CFG(DIV_MCO1, RCC_MCO1CFGR, 4, 4, 0, NULL, DIV_NO_BIT_RDY),
808 DIV_CFG(DIV_MCO2, RCC_MCO2CFGR, 4, 4, 0, NULL, DIV_NO_BIT_RDY),
809
810 DIV_CFG(DIV_HSI, RCC_HSICFGR, 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL, DIV_NO_BIT_RDY),
811 DIV_CFG(DIV_TRACE, RCC_DBGCFGR, 0, 3, CLK_DIVIDER_POWER_OF_TWO, NULL, DIV_NO_BIT_RDY),
812
813 DIV_CFG(DIV_ETH1PTP, RCC_ETH12CKSELR, 4, 4, 0, NULL, DIV_NO_BIT_RDY),
814 DIV_CFG(DIV_ETH2PTP, RCC_ETH12CKSELR, 12, 4, 0, NULL, DIV_NO_BIT_RDY),
815 };
816
817 #define MAX_HSI_HZ 64000000
818 #define USB_PHY_48_MHZ 48000000
819
820 #define TIMEOUT_US_200MS U(200000)
821 #define TIMEOUT_US_1S U(1000000)
822
823 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS
824 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS
825 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS
826 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS
827 #define OSCRDY_TIMEOUT TIMEOUT_US_1S
828
829 enum stm32_osc {
830 OSC_HSI,
831 OSC_HSE,
832 OSC_CSI,
833 OSC_LSI,
834 OSC_LSE,
835 OSC_I2SCKIN,
836 NB_OSCILLATOR
837 };
838
839 enum stm32mp1_pll_id {
840 _PLL1,
841 _PLL2,
842 _PLL3,
843 _PLL4,
844 _PLL_NB
845 };
846
847 enum stm32mp1_plltype {
848 PLL_800,
849 PLL_1600,
850 PLL_2000,
851 PLL_TYPE_NB
852 };
853
854 #define RCC_OFFSET_PLLXCR 0
855 #define RCC_OFFSET_PLLXCFGR1 4
856 #define RCC_OFFSET_PLLXCFGR2 8
857 #define RCC_OFFSET_PLLXFRACR 12
858 #define RCC_OFFSET_PLLXCSGR 16
859
860 struct stm32_clk_pll {
861 enum stm32mp1_plltype plltype;
862 uint16_t clk_id;
863 uint16_t reg_pllxcr;
864 };
865
866 struct stm32mp1_pll {
867 uint8_t refclk_min;
868 uint8_t refclk_max;
869 };
870
871 /* Define characteristic of PLL according type */
872 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
873 [PLL_800] = {
874 .refclk_min = 4,
875 .refclk_max = 16,
876 },
877 [PLL_1600] = {
878 .refclk_min = 8,
879 .refclk_max = 16,
880 },
881 [PLL_2000] = {
882 .refclk_min = 8,
883 .refclk_max = 16,
884 },
885 };
886
887 #if STM32MP_USB_PROGRAMMER
888 static bool pll4_bootrom;
889 #endif
890
891 /* RCC clock device driver private */
892 static uint8_t refcounts_mp13[CK_LAST];
893
894 static const struct stm32_clk_pll *clk_st32_pll_data(unsigned int idx);
895
896 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
clk_oscillator_check_bypass(struct stm32_clk_priv * priv,int idx,bool digbyp,bool bypass)897 static void clk_oscillator_check_bypass(struct stm32_clk_priv *priv, int idx,
898 bool digbyp, bool bypass)
899 {
900 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, idx);
901 struct stm32_clk_bypass *bypass_data = osc_data->bypass;
902 uintptr_t address;
903
904 if (bypass_data == NULL) {
905 return;
906 }
907
908 address = priv->base + bypass_data->offset;
909 if ((mmio_read_32(address) & RCC_OCENR_HSEBYP) &&
910 (!(digbyp || bypass))) {
911 panic();
912 }
913 }
914 #endif
915
stm32_enable_oscillator_hse(struct stm32_clk_priv * priv)916 static void stm32_enable_oscillator_hse(struct stm32_clk_priv *priv)
917 {
918 struct stm32_clk_platdata *pdata = priv->pdata;
919 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_HSE];
920 bool digbyp = osci->digbyp;
921 bool bypass = osci->bypass;
922 bool css = osci->css;
923
924 if (_clk_stm32_get_rate(priv, _CK_HSE) == 0U) {
925 return;
926 }
927
928 clk_oscillator_set_bypass(priv, _CK_HSE, digbyp, bypass);
929
930 _clk_stm32_enable(priv, _CK_HSE);
931
932 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
933 clk_oscillator_check_bypass(priv, _CK_HSE, digbyp, bypass);
934 #endif
935
936 clk_oscillator_set_css(priv, _CK_HSE, css);
937 }
938
stm32_enable_oscillator_lse(struct stm32_clk_priv * priv)939 static void stm32_enable_oscillator_lse(struct stm32_clk_priv *priv)
940 {
941 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, _CK_LSE);
942 struct stm32_clk_platdata *pdata = priv->pdata;
943 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE];
944 bool digbyp = osci->digbyp;
945 bool bypass = osci->bypass;
946 uint8_t drive = osci->drive;
947
948 if (_clk_stm32_get_rate(priv, _CK_LSE) == 0U) {
949 return;
950 }
951
952 /* Do not reconfigure LSE if already enabled */
953 if (_clk_stm32_gate_is_enabled(priv, osc_data->gate_id)) {
954 return;
955 }
956
957 clk_oscillator_set_bypass(priv, _CK_LSE, digbyp, bypass);
958
959 clk_oscillator_set_drive(priv, _CK_LSE, drive);
960
961 _clk_stm32_gate_enable(priv, osc_data->gate_id);
962 }
963
stm32mp1_set_hsidiv(uint8_t hsidiv)964 static int stm32mp1_set_hsidiv(uint8_t hsidiv)
965 {
966 uint64_t timeout;
967 uintptr_t rcc_base = stm32mp_rcc_base();
968 uintptr_t address = rcc_base + RCC_OCRDYR;
969
970 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR,
971 RCC_HSICFGR_HSIDIV_MASK,
972 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv);
973
974 timeout = timeout_init_us(HSIDIV_TIMEOUT);
975 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) {
976 if (timeout_elapsed(timeout)) {
977 EARLY_ERROR("HSIDIV failed @ 0x%lx: 0x%x\n",
978 address, mmio_read_32(address));
979 return -ETIMEDOUT;
980 }
981 }
982
983 return 0;
984 }
985
stm32mp1_hsidiv(unsigned long hsifreq)986 static int stm32mp1_hsidiv(unsigned long hsifreq)
987 {
988 uint8_t hsidiv;
989 uint32_t hsidivfreq = MAX_HSI_HZ;
990
991 for (hsidiv = 0; hsidiv < 4U; hsidiv++) {
992 if (hsidivfreq == hsifreq) {
993 break;
994 }
995
996 hsidivfreq /= 2U;
997 }
998
999 if (hsidiv == 4U) {
1000 EARLY_ERROR("Invalid clk-hsi frequency\n");
1001 return -EINVAL;
1002 }
1003
1004 if (hsidiv != 0U) {
1005 return stm32mp1_set_hsidiv(hsidiv);
1006 }
1007
1008 return 0;
1009 }
1010
stm32_clk_oscillators_lse_set_css(struct stm32_clk_priv * priv)1011 static int stm32_clk_oscillators_lse_set_css(struct stm32_clk_priv *priv)
1012 {
1013 struct stm32_clk_platdata *pdata = priv->pdata;
1014 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE];
1015
1016 clk_oscillator_set_css(priv, _CK_LSE, osci->css);
1017
1018 return 0;
1019 }
1020
stm32mp1_come_back_to_hsi(void)1021 static int stm32mp1_come_back_to_hsi(void)
1022 {
1023 int ret;
1024 struct stm32_clk_priv *priv = clk_stm32_get_priv();
1025
1026 /* Come back to HSI */
1027 ret = _clk_stm32_set_parent(priv, _CKMPU, _CK_HSI);
1028 if (ret != 0) {
1029 return ret;
1030 }
1031
1032 ret = _clk_stm32_set_parent(priv, _CKAXI, _CK_HSI);
1033 if (ret != 0) {
1034 return ret;
1035 }
1036
1037 ret = _clk_stm32_set_parent(priv, _CKMLAHB, _CK_HSI);
1038 if (ret != 0) {
1039 return ret;
1040 }
1041
1042 return 0;
1043 }
1044
stm32_clk_configure_clk_get_binding_id(struct stm32_clk_priv * priv,uint32_t data)1045 static int stm32_clk_configure_clk_get_binding_id(struct stm32_clk_priv *priv, uint32_t data)
1046 {
1047 unsigned long binding_id = ((unsigned long)data & CLK_ID_MASK) >> CLK_ID_SHIFT;
1048
1049 return clk_get_index(priv, binding_id);
1050 }
1051
stm32_clk_configure_clk(struct stm32_clk_priv * priv,uint32_t data)1052 static int stm32_clk_configure_clk(struct stm32_clk_priv *priv, uint32_t data)
1053 {
1054 int sel = (data & CLK_SEL_MASK) >> CLK_SEL_SHIFT;
1055 int enable = (data & CLK_ON_MASK) >> CLK_ON_SHIFT;
1056 int clk_id;
1057 int ret;
1058
1059 clk_id = stm32_clk_configure_clk_get_binding_id(priv, data);
1060 if (clk_id < 0) {
1061 return clk_id;
1062 }
1063
1064 ret = _clk_stm32_set_parent_by_index(priv, clk_id, sel);
1065 if (ret != 0) {
1066 return ret;
1067 }
1068
1069 if (enable != 0) {
1070 clk_stm32_enable_call_ops(priv, clk_id);
1071 } else {
1072 clk_stm32_disable_call_ops(priv, clk_id);
1073 }
1074
1075 return 0;
1076 }
1077
stm32_clk_configure_mux(struct stm32_clk_priv * priv,uint32_t data)1078 static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t data)
1079 {
1080 int mux = (data & MUX_ID_MASK) >> MUX_ID_SHIFT;
1081 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT;
1082
1083 return clk_mux_set_parent(priv, mux, sel);
1084 }
1085
stm32_clk_dividers_configure(struct stm32_clk_priv * priv)1086 static int stm32_clk_dividers_configure(struct stm32_clk_priv *priv)
1087 {
1088 struct stm32_clk_platdata *pdata = priv->pdata;
1089 uint32_t i;
1090
1091 for (i = 0; i < pdata->nclkdiv; i++) {
1092 int div_id, div_n;
1093 int val;
1094 int ret;
1095
1096 val = pdata->clkdiv[i] & CMD_DATA_MASK;
1097 div_id = (val & DIV_ID_MASK) >> DIV_ID_SHIFT;
1098 div_n = (val & DIV_DIVN_MASK) >> DIV_DIVN_SHIFT;
1099
1100 ret = clk_stm32_set_div(priv, div_id, div_n);
1101 if (ret != 0) {
1102 return ret;
1103 }
1104 }
1105
1106 return 0;
1107 }
1108
stm32_clk_source_configure(struct stm32_clk_priv * priv)1109 static int stm32_clk_source_configure(struct stm32_clk_priv *priv)
1110 {
1111 struct stm32_clk_platdata *pdata = priv->pdata;
1112 bool ckper_disabled = false;
1113 int clk_id;
1114 int ret;
1115 uint32_t i;
1116
1117 for (i = 0; i < pdata->nclksrc; i++) {
1118 uint32_t val = pdata->clksrc[i];
1119 uint32_t cmd, cmd_data;
1120
1121 if (val == (uint32_t)CLK_CKPER_DISABLED) {
1122 ckper_disabled = true;
1123 continue;
1124 }
1125
1126 if (val == (uint32_t)CLK_RTC_DISABLED) {
1127 continue;
1128 }
1129
1130 cmd = (val & CMD_MASK) >> CMD_SHIFT;
1131 cmd_data = val & ~CMD_MASK;
1132
1133 switch (cmd) {
1134 case CMD_MUX:
1135 ret = stm32_clk_configure_mux(priv, cmd_data);
1136 break;
1137
1138 case CMD_CLK:
1139 clk_id = stm32_clk_configure_clk_get_binding_id(priv, cmd_data);
1140
1141 if (clk_id == _RTCCK) {
1142 if ((_clk_stm32_is_enabled(priv, _RTCCK) == true)) {
1143 continue;
1144 }
1145 }
1146
1147 ret = stm32_clk_configure_clk(priv, cmd_data);
1148 break;
1149 default:
1150 ret = -EINVAL;
1151 break;
1152 }
1153
1154 if (ret != 0) {
1155 return ret;
1156 }
1157 }
1158
1159 /*
1160 * CKPER is source for some peripheral clocks
1161 * (FMC-NAND / QPSI-NOR) and switching source is allowed
1162 * only if previous clock is still ON
1163 * => deactivate CKPER only after switching clock
1164 */
1165 if (ckper_disabled) {
1166 ret = stm32_clk_configure_mux(priv, CLK_CKPER_DISABLED);
1167 if (ret != 0) {
1168 return ret;
1169 }
1170 }
1171
1172 return 0;
1173 }
1174
stm32_clk_stgen_configure(struct stm32_clk_priv * priv,int id)1175 static int stm32_clk_stgen_configure(struct stm32_clk_priv *priv, int id)
1176 {
1177 unsigned long stgen_freq;
1178
1179 stgen_freq = _clk_stm32_get_rate(priv, id);
1180
1181 stm32mp_stgen_config(stgen_freq);
1182
1183 return 0;
1184 }
1185
1186 #define CLK_PLL_CFG(_idx, _clk_id, _type, _reg)\
1187 [(_idx)] = {\
1188 .clk_id = (_clk_id),\
1189 .plltype = (_type),\
1190 .reg_pllxcr = (_reg),\
1191 }
1192
clk_stm32_pll_compute_cfgr1(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll,struct stm32_pll_vco * vco,uint32_t * value)1193 static int clk_stm32_pll_compute_cfgr1(struct stm32_clk_priv *priv,
1194 const struct stm32_clk_pll *pll,
1195 struct stm32_pll_vco *vco,
1196 uint32_t *value)
1197 {
1198 uint32_t divm = vco->div_mn[PLL_CFG_M];
1199 uint32_t divn = vco->div_mn[PLL_CFG_N];
1200 unsigned long prate = 0UL;
1201 unsigned long refclk = 0UL;
1202
1203 prate = _clk_stm32_get_parent_rate(priv, pll->clk_id);
1204 refclk = prate / (divm + 1U);
1205
1206 if ((refclk < (stm32mp1_pll[pll->plltype].refclk_min * 1000000U)) ||
1207 (refclk > (stm32mp1_pll[pll->plltype].refclk_max * 1000000U))) {
1208 return -EINVAL;
1209 }
1210
1211 *value = 0;
1212
1213 if ((pll->plltype == PLL_800) && (refclk >= 8000000U)) {
1214 *value = 1U << RCC_PLLNCFGR1_IFRGE_SHIFT;
1215 }
1216
1217 *value |= (divn << RCC_PLLNCFGR1_DIVN_SHIFT) & RCC_PLLNCFGR1_DIVN_MASK;
1218 *value |= (divm << RCC_PLLNCFGR1_DIVM_SHIFT) & RCC_PLLNCFGR1_DIVM_MASK;
1219
1220 return 0;
1221 }
1222
clk_stm32_pll_compute_cfgr2(struct stm32_pll_output * out)1223 static uint32_t clk_stm32_pll_compute_cfgr2(struct stm32_pll_output *out)
1224 {
1225 uint32_t value = 0;
1226
1227 value |= (out->output[PLL_CFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & RCC_PLLNCFGR2_DIVP_MASK;
1228 value |= (out->output[PLL_CFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & RCC_PLLNCFGR2_DIVQ_MASK;
1229 value |= (out->output[PLL_CFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & RCC_PLLNCFGR2_DIVR_MASK;
1230
1231 return value;
1232 }
1233
clk_stm32_pll_config_vco(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll,struct stm32_pll_vco * vco)1234 static void clk_stm32_pll_config_vco(struct stm32_clk_priv *priv,
1235 const struct stm32_clk_pll *pll,
1236 struct stm32_pll_vco *vco)
1237 {
1238 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1239 uint32_t value = 0;
1240
1241 if (clk_stm32_pll_compute_cfgr1(priv, pll, vco, &value) != 0) {
1242 EARLY_ERROR("Invalid Vref clock !\n");
1243 panic();
1244 }
1245
1246 /* Write N / M / IFREGE fields */
1247 mmio_write_32(pll_base + RCC_OFFSET_PLLXCFGR1, value);
1248
1249 /* Fractional configuration */
1250 mmio_write_32(pll_base + RCC_OFFSET_PLLXFRACR, 0);
1251
1252 /* Frac must be enabled only once its configuration is loaded */
1253 mmio_write_32(pll_base + RCC_OFFSET_PLLXFRACR, vco->frac << RCC_PLLNFRACR_FRACV_SHIFT);
1254 mmio_setbits_32(pll_base + RCC_OFFSET_PLLXFRACR, RCC_PLLNFRACR_FRACLE);
1255 }
1256
clk_stm32_pll_config_csg(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll,struct stm32_pll_vco * vco)1257 static void clk_stm32_pll_config_csg(struct stm32_clk_priv *priv,
1258 const struct stm32_clk_pll *pll,
1259 struct stm32_pll_vco *vco)
1260 {
1261 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1262 uint32_t mod_per = 0;
1263 uint32_t inc_step = 0;
1264 uint32_t sscg_mode = 0;
1265 uint32_t value = 0;
1266
1267 if (!vco->csg_enabled) {
1268 return;
1269 }
1270
1271 mod_per = vco->csg[PLL_CSG_MOD_PER];
1272 inc_step = vco->csg[PLL_CSG_INC_STEP];
1273 sscg_mode = vco->csg[PLL_CSG_SSCG_MODE];
1274
1275 value |= (mod_per << RCC_PLLNCSGR_MOD_PER_SHIFT) & RCC_PLLNCSGR_MOD_PER_MASK;
1276 value |= (inc_step << RCC_PLLNCSGR_INC_STEP_SHIFT) & RCC_PLLNCSGR_INC_STEP_MASK;
1277 value |= (sscg_mode << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & RCC_PLLNCSGR_SSCG_MODE_MASK;
1278
1279 mmio_write_32(pll_base + RCC_OFFSET_PLLXCSGR, value);
1280 mmio_setbits_32(pll_base + RCC_OFFSET_PLLXCR, RCC_PLLNCR_SSCG_CTRL);
1281 }
1282
clk_stm32_pll_config_out(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll,struct stm32_pll_output * out)1283 static void clk_stm32_pll_config_out(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll,
1284 struct stm32_pll_output *out)
1285 {
1286 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1287 uint32_t value = 0;
1288
1289 value = clk_stm32_pll_compute_cfgr2(out);
1290
1291 mmio_write_32(pll_base + RCC_OFFSET_PLLXCFGR2, value);
1292 }
1293
clk_stm32_pll_get_pdata(int pll_idx)1294 static inline struct stm32_pll_dt_cfg *clk_stm32_pll_get_pdata(int pll_idx)
1295 {
1296 struct stm32_clk_priv *priv = clk_stm32_get_priv();
1297 struct stm32_clk_platdata *pdata = priv->pdata;
1298
1299 return &pdata->pll[pll_idx];
1300 }
1301
1302 /* Define characteristic for PLL1 : PLL_2000 */
1303 #define POST_DIVM_MIN 8000000U
1304 #define POST_DIVM_MAX 16000000U
1305 #define DIVM_MIN 0U
1306 #define DIVM_MAX 63U
1307 #define DIVN_MIN 24U
1308 #define DIVN_MAX 99U
1309 #define DIVP_MIN 0U
1310 #define DIVP_MAX 127U
1311 #define FRAC_MAX 8192U
1312 #define VCO_MIN 992000000U
1313 #define VCO_MAX 2000000000U
1314
clk_compute_pll1_settings(uint32_t freq_khz)1315 static int clk_compute_pll1_settings(uint32_t freq_khz)
1316 {
1317 struct stm32_clk_priv *priv = clk_stm32_get_priv();
1318 struct stm32_pll_dt_cfg *pll1 = clk_stm32_pll_get_pdata(_PLL1);
1319 struct stm32_pll_dt_cfg *pll2 = clk_stm32_pll_get_pdata(_PLL2);
1320 unsigned long long best_diff = ULLONG_MAX;
1321 unsigned int divm;
1322 unsigned long input_freq = 0UL;
1323 uint32_t src = pll2->vco.src;
1324
1325 /* PLL1 share the same clock source than PLL2 */
1326 switch (src) {
1327 case CLK_PLL12_HSI:
1328 input_freq = _clk_stm32_get_rate(priv, _CK_HSI);
1329 break;
1330 case CLK_PLL12_HSE:
1331 input_freq = _clk_stm32_get_rate(priv, _CK_HSE);
1332 break;
1333 default:
1334 break;
1335 }
1336
1337 if (input_freq == 0UL) {
1338 panic();
1339 }
1340
1341 /* Following parameters have always the same value */
1342 pll1->output.output[PLL_CFG_Q] = 0U;
1343 pll1->output.output[PLL_CFG_R] = 0U;
1344
1345 for (divm = (DIVM_MAX + 1U); divm != DIVM_MIN; divm--) {
1346 unsigned long post_divm = input_freq / divm;
1347 unsigned int divp;
1348
1349 if ((post_divm < POST_DIVM_MIN) || (post_divm > POST_DIVM_MAX)) {
1350 continue;
1351 }
1352
1353 for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) {
1354 unsigned long long output_freq = freq_khz * 1000ULL;
1355 unsigned long long freq;
1356 unsigned long long divn;
1357 unsigned long long frac;
1358 unsigned int i;
1359
1360 freq = output_freq * divm * (divp + 1U);
1361
1362 divn = (freq / input_freq) - 1U;
1363 if ((divn < DIVN_MIN) || (divn > DIVN_MAX)) {
1364 continue;
1365 }
1366
1367 frac = ((freq * FRAC_MAX) / input_freq) - ((divn + 1U) * FRAC_MAX);
1368
1369 /* 2 loops to refine the fractional part */
1370 for (i = 2U; i != 0U; i--) {
1371 unsigned long long diff;
1372 unsigned long long vco;
1373
1374 if (frac > FRAC_MAX) {
1375 break;
1376 }
1377
1378 vco = (post_divm * (divn + 1U)) + ((post_divm * frac) / FRAC_MAX);
1379
1380 if ((vco < (VCO_MIN / 2U)) || (vco > (VCO_MAX / 2U))) {
1381 frac++;
1382 continue;
1383 }
1384
1385 freq = vco / (divp + 1U);
1386 if (output_freq < freq) {
1387 diff = freq - output_freq;
1388 } else {
1389 diff = output_freq - freq;
1390 }
1391
1392 if (diff < best_diff) {
1393 pll1->vco.src = src;
1394 pll1->vco.status = RCC_PLLNCR_DIVPEN | RCC_PLLNCR_PLLON;
1395 pll1->vco.div_mn[PLL_CFG_M] = divm - 1U;
1396 pll1->vco.div_mn[PLL_CFG_N] = (uint32_t)divn;
1397 pll1->vco.frac = (uint32_t)frac;
1398 pll1->output.output[PLL_CFG_P] = divp;
1399
1400 if (diff == 0U) {
1401 return 0;
1402 }
1403
1404 best_diff = diff;
1405 }
1406
1407 frac++;
1408 }
1409 }
1410 }
1411
1412 if (best_diff == ULLONG_MAX) {
1413 return -EINVAL;
1414 }
1415
1416 return 0;
1417 }
1418
_clk_stm32_pll_is_enabled(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1419 static bool _clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1420 {
1421 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1422
1423 return ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLON) != 0U);
1424 }
1425
_clk_stm32_pll_set_on(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1426 static void _clk_stm32_pll_set_on(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1427 {
1428 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1429
1430 /* Preserve RCC_PLLNCR_SSCG_CTRL value */
1431 mmio_clrsetbits_32(pll_base, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN,
1432 RCC_PLLNCR_PLLON);
1433 }
1434
_clk_stm32_pll_set_off(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1435 static void _clk_stm32_pll_set_off(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1436 {
1437 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1438
1439 /* Stop all output */
1440 mmio_clrbits_32(pll_base, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1441
1442 /* Stop PLL */
1443 mmio_clrbits_32(pll_base, RCC_PLLNCR_PLLON);
1444 }
1445
_clk_stm32_pll_wait_ready_on(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1446 static int _clk_stm32_pll_wait_ready_on(struct stm32_clk_priv *priv,
1447 const struct stm32_clk_pll *pll)
1448 {
1449 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1450 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT);
1451
1452 /* Wait PLL lock */
1453 while ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLRDY) == 0U) {
1454 if (timeout_elapsed(timeout)) {
1455 ERROR("PLL%d start failed @ 0x%x: 0x%x\n",
1456 pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcr, mmio_read_32(pll_base));
1457 return -EINVAL;
1458 }
1459 }
1460
1461 return 0;
1462 }
1463
_clk_stm32_pll_wait_ready_off(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1464 static int _clk_stm32_pll_wait_ready_off(struct stm32_clk_priv *priv,
1465 const struct stm32_clk_pll *pll)
1466 {
1467 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1468 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT);
1469
1470 /* Wait PLL lock */
1471 while ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLRDY) != 0U) {
1472 if (timeout_elapsed(timeout)) {
1473 ERROR("PLL%d stop failed @ 0x%x: 0x%x\n",
1474 pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcr, mmio_read_32(pll_base));
1475 return -EINVAL;
1476 }
1477 }
1478
1479 return 0;
1480 }
1481
_clk_stm32_pll_enable(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1482 static int _clk_stm32_pll_enable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1483 {
1484 if (_clk_stm32_pll_is_enabled(priv, pll)) {
1485 return 0;
1486 }
1487
1488 /* Preserve RCC_PLLNCR_SSCG_CTRL value */
1489 _clk_stm32_pll_set_on(priv, pll);
1490
1491 /* Wait PLL lock */
1492 return _clk_stm32_pll_wait_ready_on(priv, pll);
1493 }
1494
_clk_stm32_pll_disable(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1495 static void _clk_stm32_pll_disable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1496 {
1497 if (!_clk_stm32_pll_is_enabled(priv, pll)) {
1498 return;
1499 }
1500
1501 /* Stop all outputs and the PLL */
1502 _clk_stm32_pll_set_off(priv, pll);
1503
1504 /* Wait PLL stopped */
1505 _clk_stm32_pll_wait_ready_off(priv, pll);
1506 }
1507
_clk_stm32_pll_init(struct stm32_clk_priv * priv,int pll_idx,struct stm32_pll_dt_cfg * pll_conf)1508 static int _clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx,
1509 struct stm32_pll_dt_cfg *pll_conf)
1510 {
1511 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_idx);
1512 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1513 int ret = 0;
1514
1515 /* Configure PLLs source */
1516 ret = stm32_clk_configure_mux(priv, pll_conf->vco.src);
1517 if (ret != 0) {
1518 return ret;
1519 }
1520
1521 #if STM32MP_USB_PROGRAMMER
1522 if ((pll_idx == _PLL4) && pll4_bootrom) {
1523 clk_stm32_pll_config_out(priv, pll, &pll_conf->output);
1524
1525 mmio_setbits_32(pll_base,
1526 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1527
1528 return 0;
1529 }
1530 #endif
1531 /* Stop the PLL before */
1532 _clk_stm32_pll_disable(priv, pll);
1533
1534 clk_stm32_pll_config_vco(priv, pll, &pll_conf->vco);
1535 clk_stm32_pll_config_out(priv, pll, &pll_conf->output);
1536 clk_stm32_pll_config_csg(priv, pll, &pll_conf->vco);
1537
1538 ret = _clk_stm32_pll_enable(priv, pll);
1539 if (ret != 0) {
1540 return ret;
1541 }
1542
1543 mmio_setbits_32(pll_base, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1544
1545 return 0;
1546 }
1547
clk_stm32_pll_init(struct stm32_clk_priv * priv,int pll_idx)1548 static int clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx)
1549 {
1550 struct stm32_pll_dt_cfg *pll_conf = clk_stm32_pll_get_pdata(pll_idx);
1551
1552 if (pll_conf->vco.status != 0U) {
1553 return _clk_stm32_pll_init(priv, pll_idx, pll_conf);
1554 }
1555
1556 return 0;
1557 }
1558
stm32_clk_pll_configure(struct stm32_clk_priv * priv)1559 static int stm32_clk_pll_configure(struct stm32_clk_priv *priv)
1560 {
1561 int err = 0;
1562
1563 err = clk_stm32_pll_init(priv, _PLL1);
1564 if (err != 0) {
1565 return err;
1566 }
1567
1568 err = clk_stm32_pll_init(priv, _PLL2);
1569 if (err != 0) {
1570 return err;
1571 }
1572
1573 err = clk_stm32_pll_init(priv, _PLL3);
1574 if (err != 0) {
1575 return err;
1576 }
1577
1578 err = clk_stm32_pll_init(priv, _PLL4);
1579 if (err != 0) {
1580 return err;
1581 }
1582
1583 return 0;
1584 }
1585
stm32_clk_oscillators_wait_lse_ready(struct stm32_clk_priv * priv)1586 static int stm32_clk_oscillators_wait_lse_ready(struct stm32_clk_priv *priv)
1587 {
1588 int ret = 0;
1589
1590 if (_clk_stm32_get_rate(priv, _CK_LSE) != 0U) {
1591 ret = clk_oscillator_wait_ready_on(priv, _CK_LSE);
1592 }
1593
1594 return ret;
1595 }
1596
stm32_clk_oscillators_enable(struct stm32_clk_priv * priv)1597 static void stm32_clk_oscillators_enable(struct stm32_clk_priv *priv)
1598 {
1599 stm32_enable_oscillator_hse(priv);
1600 stm32_enable_oscillator_lse(priv);
1601 _clk_stm32_enable(priv, _CK_LSI);
1602 _clk_stm32_enable(priv, _CK_CSI);
1603 }
1604
stm32_clk_hsidiv_configure(struct stm32_clk_priv * priv)1605 static int stm32_clk_hsidiv_configure(struct stm32_clk_priv *priv)
1606 {
1607 return stm32mp1_hsidiv(_clk_stm32_get_rate(priv, _CK_HSI));
1608 }
1609
1610 #if STM32MP_USB_PROGRAMMER
stm32mp1_clk_is_pll4_used_by_bootrom(struct stm32_clk_priv * priv,int usbphy_p)1611 static bool stm32mp1_clk_is_pll4_used_by_bootrom(struct stm32_clk_priv *priv, int usbphy_p)
1612 {
1613 /* Don't initialize PLL4, when used by BOOTROM */
1614 if ((stm32mp_get_boot_itf_selected() ==
1615 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) &&
1616 (usbphy_p == _PLL4R)) {
1617 return true;
1618 }
1619
1620 return false;
1621 }
1622
stm32mp1_clk_check_usb_conflict(struct stm32_clk_priv * priv,int usbphy_p,int usbo_p)1623 static int stm32mp1_clk_check_usb_conflict(struct stm32_clk_priv *priv, int usbphy_p, int usbo_p)
1624 {
1625 int _usbo_p;
1626 int _usbphy_p;
1627
1628 if (!pll4_bootrom) {
1629 return 0;
1630 }
1631
1632 _usbo_p = _clk_stm32_get_parent(priv, _USBO_K);
1633 _usbphy_p = _clk_stm32_get_parent(priv, _USBPHY_K);
1634
1635 if ((_usbo_p != usbo_p) || (_usbphy_p != usbphy_p)) {
1636 return -FDT_ERR_BADVALUE;
1637 }
1638
1639 return 0;
1640 }
1641 #endif
1642
1643 static struct clk_oscillator_data stm32mp13_osc_data[NB_OSCILLATOR] = {
1644 OSCILLATOR(OSC_HSI, _CK_HSI, "clk-hsi", GATE_HSI, GATE_HSI_RDY,
1645 NULL, NULL, NULL),
1646
1647 OSCILLATOR(OSC_LSI, _CK_LSI, "clk-lsi", GATE_LSI, GATE_LSI_RDY,
1648 NULL, NULL, NULL),
1649
1650 OSCILLATOR(OSC_CSI, _CK_CSI, "clk-csi", GATE_CSI, GATE_CSI_RDY,
1651 NULL, NULL, NULL),
1652
1653 OSCILLATOR(OSC_LSE, _CK_LSE, "clk-lse", GATE_LSE, GATE_LSE_RDY,
1654 BYPASS(RCC_BDCR, 1, 3),
1655 CSS(RCC_BDCR, 8),
1656 DRIVE(RCC_BDCR, 4, 2, 2)),
1657
1658 OSCILLATOR(OSC_HSE, _CK_HSE, "clk-hse", GATE_HSE, GATE_HSE_RDY,
1659 BYPASS(RCC_OCENSETR, 10, 7),
1660 CSS(RCC_OCENSETR, 11),
1661 NULL),
1662
1663 OSCILLATOR(OSC_I2SCKIN, _I2SCKIN, "i2s_ckin", NO_GATE, NO_GATE,
1664 NULL, NULL, NULL),
1665 };
1666
clk_stm32_get_oscillator_name(enum stm32_osc id)1667 static const char *clk_stm32_get_oscillator_name(enum stm32_osc id)
1668 {
1669 if (id < NB_OSCILLATOR) {
1670 return stm32mp13_osc_data[id].name;
1671 }
1672
1673 return NULL;
1674 }
1675
1676 #define CLK_PLL_CFG(_idx, _clk_id, _type, _reg)\
1677 [(_idx)] = {\
1678 .clk_id = (_clk_id),\
1679 .plltype = (_type),\
1680 .reg_pllxcr = (_reg),\
1681 }
1682
1683 static const struct stm32_clk_pll stm32_mp13_clk_pll[_PLL_NB] = {
1684 CLK_PLL_CFG(_PLL1, _CK_PLL1, PLL_2000, RCC_PLL1CR),
1685 CLK_PLL_CFG(_PLL2, _CK_PLL2, PLL_1600, RCC_PLL2CR),
1686 CLK_PLL_CFG(_PLL3, _CK_PLL3, PLL_800, RCC_PLL3CR),
1687 CLK_PLL_CFG(_PLL4, _CK_PLL4, PLL_800, RCC_PLL4CR),
1688 };
1689
clk_st32_pll_data(unsigned int idx)1690 static const struct stm32_clk_pll *clk_st32_pll_data(unsigned int idx)
1691 {
1692 return &stm32_mp13_clk_pll[idx];
1693 }
1694
1695 struct stm32_pll_cfg {
1696 uint8_t pll_id;
1697 };
1698
clk_stm32_pll_recalc_rate(struct stm32_clk_priv * priv,int id,unsigned long prate)1699 static unsigned long clk_stm32_pll_recalc_rate(struct stm32_clk_priv *priv, int id,
1700 unsigned long prate)
1701 {
1702 const struct clk_stm32 *clk = _clk_get(priv, id);
1703 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg;
1704 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id);
1705 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1706 uint32_t cfgr1, fracr, divm, divn;
1707 unsigned long fvco;
1708
1709 cfgr1 = mmio_read_32(pll_base + RCC_OFFSET_PLLXCFGR1);
1710 fracr = mmio_read_32(pll_base + RCC_OFFSET_PLLXFRACR);
1711
1712 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
1713 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
1714
1715 /*
1716 * With FRACV :
1717 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
1718 * Without FRACV
1719 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
1720 */
1721 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) {
1722 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >>
1723 RCC_PLLNFRACR_FRACV_SHIFT;
1724 unsigned long long numerator, denominator;
1725
1726 numerator = (((unsigned long long)divn + 1U) << 13) + fracv;
1727 numerator = prate * numerator;
1728 denominator = ((unsigned long long)divm + 1U) << 13;
1729 fvco = (unsigned long)(numerator / denominator);
1730 } else {
1731 fvco = (unsigned long)(prate * (divn + 1U) / (divm + 1U));
1732 }
1733
1734 return fvco;
1735 };
1736
clk_stm32_pll_is_enabled(struct stm32_clk_priv * priv,int id)1737 static bool clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, int id)
1738 {
1739 const struct clk_stm32 *clk = _clk_get(priv, id);
1740 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg;
1741 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id);
1742
1743 return _clk_stm32_pll_is_enabled(priv, pll);
1744 }
1745
clk_stm32_pll_enable(struct stm32_clk_priv * priv,int id)1746 static int clk_stm32_pll_enable(struct stm32_clk_priv *priv, int id)
1747 {
1748 const struct clk_stm32 *clk = _clk_get(priv, id);
1749 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg;
1750 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id);
1751
1752 return _clk_stm32_pll_enable(priv, pll);
1753 }
1754
clk_stm32_pll_disable(struct stm32_clk_priv * priv,int id)1755 static void clk_stm32_pll_disable(struct stm32_clk_priv *priv, int id)
1756 {
1757 const struct clk_stm32 *clk = _clk_get(priv, id);
1758 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg;
1759 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id);
1760
1761 _clk_stm32_pll_disable(priv, pll);
1762 }
1763
1764 static const struct stm32_clk_ops clk_stm32_pll_ops = {
1765 .recalc_rate = clk_stm32_pll_recalc_rate,
1766 .enable = clk_stm32_pll_enable,
1767 .disable = clk_stm32_pll_disable,
1768 .is_enabled = clk_stm32_pll_is_enabled,
1769 };
1770
1771 #define CLK_PLL(idx, _idx, _parent, _gate, _pll_id, _flags)[idx] = {\
1772 .binding = _idx,\
1773 .parent = _parent,\
1774 .flags = (_flags),\
1775 .clock_cfg = &(struct stm32_pll_cfg) {\
1776 .pll_id = _pll_id,\
1777 },\
1778 .ops = STM32_PLL_OPS,\
1779 }
1780
1781 struct clk_stm32_composite_cfg {
1782 uint8_t gate_id;
1783 uint8_t div_id;
1784 };
1785
clk_stm32_composite_recalc_rate(struct stm32_clk_priv * priv,int idx,unsigned long prate)1786 static unsigned long clk_stm32_composite_recalc_rate(struct stm32_clk_priv *priv,
1787 int idx, unsigned long prate)
1788 {
1789 const struct clk_stm32 *clk = _clk_get(priv, idx);
1790 struct clk_stm32_composite_cfg *composite_cfg = clk->clock_cfg;
1791
1792 return _clk_stm32_divider_recalc(priv, composite_cfg->div_id, prate);
1793 };
1794
clk_stm32_composite_gate_is_enabled(struct stm32_clk_priv * priv,int idx)1795 static bool clk_stm32_composite_gate_is_enabled(struct stm32_clk_priv *priv, int idx)
1796 {
1797 const struct clk_stm32 *clk = _clk_get(priv, idx);
1798 struct clk_stm32_composite_cfg *composite_cfg = clk->clock_cfg;
1799
1800 return _clk_stm32_gate_is_enabled(priv, composite_cfg->gate_id);
1801 }
1802
clk_stm32_composite_gate_enable(struct stm32_clk_priv * priv,int idx)1803 static int clk_stm32_composite_gate_enable(struct stm32_clk_priv *priv, int idx)
1804 {
1805 const struct clk_stm32 *clk = _clk_get(priv, idx);
1806 struct clk_stm32_composite_cfg *composite_cfg = clk->clock_cfg;
1807
1808 return _clk_stm32_gate_enable(priv, composite_cfg->gate_id);
1809 }
1810
clk_stm32_composite_gate_disable(struct stm32_clk_priv * priv,int idx)1811 static void clk_stm32_composite_gate_disable(struct stm32_clk_priv *priv, int idx)
1812 {
1813 const struct clk_stm32 *clk = _clk_get(priv, idx);
1814 struct clk_stm32_composite_cfg *composite_cfg = clk->clock_cfg;
1815
1816 _clk_stm32_gate_disable(priv, composite_cfg->gate_id);
1817 }
1818
1819 static const struct stm32_clk_ops clk_stm32_composite_ops = {
1820 .recalc_rate = clk_stm32_composite_recalc_rate,
1821 .is_enabled = clk_stm32_composite_gate_is_enabled,
1822 .enable = clk_stm32_composite_gate_enable,
1823 .disable = clk_stm32_composite_gate_disable,
1824 };
1825
1826 #define STM32_COMPOSITE(idx, _binding, _parent, _flags, _gate_id,\
1827 _div_id)[idx] = {\
1828 .binding = (_binding),\
1829 .parent = (_parent),\
1830 .flags = (_flags),\
1831 .clock_cfg = &(struct clk_stm32_composite_cfg) {\
1832 .gate_id = (_gate_id),\
1833 .div_id = (_div_id),\
1834 },\
1835 .ops = STM32_COMPOSITE_OPS,\
1836 }
1837
1838 enum {
1839 STM32_PLL_OPS = STM32_LAST_OPS,
1840 STM32_COMPOSITE_OPS,
1841
1842 MP13_LAST_OPS
1843 };
1844
1845 static const struct stm32_clk_ops *ops_array_mp13[MP13_LAST_OPS] = {
1846 [NO_OPS] = NULL,
1847 [FIXED_FACTOR_OPS] = &clk_fixed_factor_ops,
1848 [GATE_OPS] = &clk_gate_ops,
1849 [STM32_MUX_OPS] = &clk_mux_ops,
1850 [STM32_DIVIDER_OPS] = &clk_stm32_divider_ops,
1851 [STM32_GATE_OPS] = &clk_stm32_gate_ops,
1852 [STM32_TIMER_OPS] = &clk_timer_ops,
1853 [STM32_FIXED_RATE_OPS] = &clk_stm32_fixed_rate_ops,
1854 [STM32_OSC_OPS] = &clk_stm32_osc_ops,
1855 [STM32_OSC_NOGATE_OPS] = &clk_stm32_osc_nogate_ops,
1856
1857 [STM32_PLL_OPS] = &clk_stm32_pll_ops,
1858 [STM32_COMPOSITE_OPS] = &clk_stm32_composite_ops
1859 };
1860
1861 static const struct clk_stm32 stm32mp13_clk[CK_LAST] = {
1862 /* ROOT CLOCKS */
1863 CLK_FIXED_RATE(_CK_OFF, _NO_ID, 0),
1864 CLK_OSC(_CK_HSE, CK_HSE, CLK_IS_ROOT, OSC_HSE),
1865 CLK_OSC(_CK_HSI, CK_HSI, CLK_IS_ROOT, OSC_HSI),
1866 CLK_OSC(_CK_CSI, CK_CSI, CLK_IS_ROOT, OSC_CSI),
1867 CLK_OSC(_CK_LSI, CK_LSI, CLK_IS_ROOT, OSC_LSI),
1868 CLK_OSC(_CK_LSE, CK_LSE, CLK_IS_ROOT, OSC_LSE),
1869
1870 CLK_OSC_FIXED(_I2SCKIN, _NO_ID, CLK_IS_ROOT, OSC_I2SCKIN),
1871
1872 CLK_FIXED_RATE(_USB_PHY_48, _NO_ID, USB_PHY_48_MHZ),
1873
1874 STM32_DIV(_HSE_DIV, _NO_ID, _CK_HSE, 0, DIV_RTC),
1875
1876 FIXED_FACTOR(_HSE_DIV2, CK_HSE_DIV2, _CK_HSE, 1, 2),
1877 FIXED_FACTOR(_CSI_DIV122, _NO_ID, _CK_CSI, 1, 122),
1878
1879 CLK_PLL(_CK_PLL1, PLL1, MUX(MUX_PLL12), GATE_PLL1, _PLL1, 0),
1880 CLK_PLL(_CK_PLL2, PLL2, MUX(MUX_PLL12), GATE_PLL2, _PLL2, 0),
1881 CLK_PLL(_CK_PLL3, PLL3, MUX(MUX_PLL3), GATE_PLL3, _PLL3, 0),
1882 CLK_PLL(_CK_PLL4, PLL4, MUX(MUX_PLL4), GATE_PLL4, _PLL4, 0),
1883
1884 STM32_COMPOSITE(_PLL1P, PLL1_P, _CK_PLL1, CLK_IS_CRITICAL, GATE_PLL1_DIVP, DIV_PLL1DIVP),
1885 STM32_DIV(_PLL1P_DIV, _NO_ID, _CK_PLL1, 0, DIV_MPU),
1886
1887 STM32_COMPOSITE(_PLL2P, PLL2_P, _CK_PLL2, CLK_IS_CRITICAL, GATE_PLL2_DIVP, DIV_PLL2DIVP),
1888 STM32_COMPOSITE(_PLL2Q, PLL2_Q, _CK_PLL2, 0, GATE_PLL2_DIVQ, DIV_PLL2DIVQ),
1889 STM32_COMPOSITE(_PLL2R, PLL2_R, _CK_PLL2, CLK_IS_CRITICAL, GATE_PLL2_DIVR, DIV_PLL2DIVR),
1890
1891 STM32_COMPOSITE(_PLL3P, PLL3_P, _CK_PLL3, 0, GATE_PLL3_DIVP, DIV_PLL3DIVP),
1892 STM32_COMPOSITE(_PLL3Q, PLL3_Q, _CK_PLL3, 0, GATE_PLL3_DIVQ, DIV_PLL3DIVQ),
1893 STM32_COMPOSITE(_PLL3R, PLL3_R, _CK_PLL3, 0, GATE_PLL3_DIVR, DIV_PLL3DIVR),
1894
1895 STM32_COMPOSITE(_PLL4P, PLL4_P, _CK_PLL4, 0, GATE_PLL4_DIVP, DIV_PLL4DIVP),
1896 STM32_COMPOSITE(_PLL4Q, PLL4_Q, _CK_PLL4, 0, GATE_PLL4_DIVQ, DIV_PLL4DIVQ),
1897 STM32_COMPOSITE(_PLL4R, PLL4_R, _CK_PLL4, 0, GATE_PLL4_DIVR, DIV_PLL4DIVR),
1898
1899 STM32_MUX(_CKMPU, CK_MPU, MUX_MPU, 0),
1900 STM32_DIV(_CKAXI, CK_AXI, MUX(MUX_AXI), 0, DIV_AXI),
1901 STM32_DIV(_CKMLAHB, CK_MLAHB, MUX(MUX_MLAHB), CLK_IS_CRITICAL, DIV_MLAHB),
1902 STM32_MUX(_CKPER, CK_PER, MUX(MUX_CKPER), 0),
1903
1904 STM32_DIV(_PCLK1, PCLK1, _CKMLAHB, 0, DIV_APB1),
1905 STM32_DIV(_PCLK2, PCLK2, _CKMLAHB, 0, DIV_APB2),
1906 STM32_DIV(_PCLK3, PCLK3, _CKMLAHB, 0, DIV_APB3),
1907 STM32_DIV(_PCLK4, PCLK4, _CKAXI, 0, DIV_APB4),
1908 STM32_DIV(_PCLK5, PCLK5, _CKAXI, 0, DIV_APB5),
1909 STM32_DIV(_PCLK6, PCLK6, _CKMLAHB, 0, DIV_APB6),
1910
1911 CK_TIMER(_CKTIMG1, CK_TIMG1, _PCLK1, 0, RCC_APB1DIVR, RCC_TIMG1PRER),
1912 CK_TIMER(_CKTIMG2, CK_TIMG2, _PCLK2, 0, RCC_APB2DIVR, RCC_TIMG2PRER),
1913 CK_TIMER(_CKTIMG3, CK_TIMG3, _PCLK6, 0, RCC_APB6DIVR, RCC_TIMG3PRER),
1914
1915 /* END ROOT CLOCKS */
1916
1917 STM32_GATE(_DDRC1, DDRC1, _CKAXI, CLK_IS_CRITICAL, GATE_DDRC1),
1918 STM32_GATE(_DDRC1LP, DDRC1LP, _CKAXI, CLK_IS_CRITICAL, GATE_DDRC1LP),
1919 STM32_GATE(_DDRPHYC, DDRPHYC, _PLL2R, CLK_IS_CRITICAL, GATE_DDRPHYC),
1920 STM32_GATE(_DDRPHYCLP, DDRPHYCLP, _PLL2R, CLK_IS_CRITICAL, GATE_DDRPHYCLP),
1921 STM32_GATE(_DDRCAPB, DDRCAPB, _PCLK4, CLK_IS_CRITICAL, GATE_DDRCAPB),
1922 STM32_GATE(_DDRCAPBLP, DDRCAPBLP, _PCLK4, CLK_IS_CRITICAL, GATE_DDRCAPBLP),
1923 STM32_GATE(_AXIDCG, AXIDCG, _CKAXI, CLK_IS_CRITICAL, GATE_AXIDCG),
1924 STM32_GATE(_DDRPHYCAPB, DDRPHYCAPB, _PCLK4, CLK_IS_CRITICAL, GATE_DDRPHYCAPB),
1925 STM32_GATE(_DDRPHYCAPBLP, DDRPHYCAPBLP, _PCLK4, CLK_IS_CRITICAL, GATE_DDRPHYCAPBLP),
1926
1927 STM32_GATE(_SYSCFG, SYSCFG, _PCLK3, 0, GATE_SYSCFG),
1928 STM32_GATE(_DDRPERFM, DDRPERFM, _PCLK4, 0, GATE_DDRPERFM),
1929 STM32_GATE(_IWDG2APB, IWDG2, _PCLK4, 0, GATE_IWDG2APB),
1930 STM32_GATE(_USBPHY_K, USBPHY_K, MUX(MUX_USBPHY), 0, GATE_USBPHY),
1931 STM32_GATE(_USBO_K, USBO_K, MUX(MUX_USBO), 0, GATE_USBO),
1932
1933 STM32_GATE(_RTCAPB, RTCAPB, _PCLK5, CLK_IS_CRITICAL, GATE_RTCAPB),
1934 STM32_GATE(_TZC, TZC, _PCLK5, CLK_IS_CRITICAL, GATE_TZC),
1935 STM32_GATE(_ETZPC, TZPC, _PCLK5, CLK_IS_CRITICAL, GATE_ETZPC),
1936 STM32_GATE(_IWDG1APB, IWDG1, _PCLK5, 0, GATE_IWDG1APB),
1937 STM32_GATE(_BSEC, BSEC, _PCLK5, CLK_IS_CRITICAL, GATE_BSEC),
1938 STM32_GATE(_STGENC, STGEN_K, MUX(MUX_STGEN), CLK_IS_CRITICAL, GATE_STGENC),
1939
1940 STM32_GATE(_USART1_K, USART1_K, MUX(MUX_UART1), 0, GATE_USART1),
1941 STM32_GATE(_USART2_K, USART2_K, MUX(MUX_UART2), 0, GATE_USART2),
1942 STM32_GATE(_I2C3_K, I2C3_K, MUX(MUX_I2C3), 0, GATE_I2C3),
1943 STM32_GATE(_I2C4_K, I2C4_K, MUX(MUX_I2C4), 0, GATE_I2C4),
1944 STM32_GATE(_I2C5_K, I2C5_K, MUX(MUX_I2C5), 0, GATE_I2C5),
1945 STM32_GATE(_TIM12, TIM12_K, _CKTIMG3, 0, GATE_TIM12),
1946 STM32_GATE(_TIM15, TIM15_K, _CKTIMG3, 0, GATE_TIM15),
1947
1948 STM32_GATE(_RTCCK, RTC, MUX(MUX_RTC), 0, GATE_RTCCK),
1949
1950 STM32_GATE(_GPIOA, GPIOA, _CKMLAHB, 0, GATE_GPIOA),
1951 STM32_GATE(_GPIOB, GPIOB, _CKMLAHB, 0, GATE_GPIOB),
1952 STM32_GATE(_GPIOC, GPIOC, _CKMLAHB, 0, GATE_GPIOC),
1953 STM32_GATE(_GPIOD, GPIOD, _CKMLAHB, 0, GATE_GPIOD),
1954 STM32_GATE(_GPIOE, GPIOE, _CKMLAHB, 0, GATE_GPIOE),
1955 STM32_GATE(_GPIOF, GPIOF, _CKMLAHB, 0, GATE_GPIOF),
1956 STM32_GATE(_GPIOG, GPIOG, _CKMLAHB, 0, GATE_GPIOG),
1957 STM32_GATE(_GPIOH, GPIOH, _CKMLAHB, 0, GATE_GPIOH),
1958 STM32_GATE(_GPIOI, GPIOI, _CKMLAHB, 0, GATE_GPIOI),
1959
1960 STM32_GATE(_PKA, PKA, _CKAXI, 0, GATE_PKA),
1961 STM32_GATE(_SAES_K, SAES_K, MUX(MUX_SAES), 0, GATE_SAES),
1962 STM32_GATE(_CRYP1, CRYP1, _PCLK5, 0, GATE_CRYP1),
1963 STM32_GATE(_HASH1, HASH1, _PCLK5, 0, GATE_HASH1),
1964
1965 STM32_GATE(_RNG1_K, RNG1_K, MUX(MUX_RNG1), 0, GATE_RNG1),
1966 STM32_GATE(_BKPSRAM, BKPSRAM, _PCLK5, CLK_IS_CRITICAL, GATE_BKPSRAM),
1967
1968 STM32_GATE(_SDMMC1_K, SDMMC1_K, MUX(MUX_SDMMC1), 0, GATE_SDMMC1),
1969 STM32_GATE(_SDMMC2_K, SDMMC2_K, MUX(MUX_SDMMC2), 0, GATE_SDMMC2),
1970 STM32_GATE(_DBGCK, CK_DBG, _CKAXI, 0, GATE_DBGCK),
1971
1972 STM32_GATE(_USART3_K, USART3_K, MUX(MUX_UART35), 0, GATE_USART3),
1973 STM32_GATE(_UART4_K, UART4_K, MUX(MUX_UART4), 0, GATE_UART4),
1974 STM32_GATE(_UART5_K, UART5_K, MUX(MUX_UART35), 0, GATE_UART5),
1975 STM32_GATE(_UART7_K, UART7_K, MUX(MUX_UART78), 0, GATE_UART7),
1976 STM32_GATE(_UART8_K, UART8_K, MUX(MUX_UART78), 0, GATE_UART8),
1977 STM32_GATE(_USART6_K, USART6_K, MUX(MUX_UART6), 0, GATE_USART6),
1978 STM32_GATE(_MCE, MCE, _CKAXI, CLK_IS_CRITICAL, GATE_MCE),
1979 STM32_GATE(_FMC_K, FMC_K, MUX(MUX_FMC), 0, GATE_FMC),
1980 STM32_GATE(_QSPI_K, QSPI_K, MUX(MUX_QSPI), 0, GATE_QSPI),
1981
1982 STM32_COMPOSITE(_MCO1_K, CK_MCO1, MUX(MUX_MCO1), 0, GATE_MCO1, DIV_MCO1),
1983 STM32_COMPOSITE(_MCO2_K, CK_MCO2, MUX(MUX_MCO2), 0, GATE_MCO2, DIV_MCO2),
1984 STM32_COMPOSITE(_TRACECK, CK_TRACE, _CKAXI, 0, GATE_TRACECK, DIV_TRACE),
1985 };
1986
1987 static struct stm32_pll_dt_cfg mp13_pll[_PLL_NB];
1988
1989 static struct stm32_osci_dt_cfg mp13_osci[NB_OSCILLATOR];
1990
1991 static uint32_t mp13_clksrc[MUX_MAX];
1992
1993 static uint32_t mp13_clkdiv[DIV_MAX];
1994
1995 static struct stm32_clk_platdata stm32mp13_clock_pdata = {
1996 .osci = mp13_osci,
1997 .nosci = NB_OSCILLATOR,
1998 .pll = mp13_pll,
1999 .npll = _PLL_NB,
2000 .clksrc = mp13_clksrc,
2001 .nclksrc = MUX_MAX,
2002 .clkdiv = mp13_clkdiv,
2003 .nclkdiv = DIV_MAX,
2004 };
2005
2006 static struct stm32_clk_priv stm32mp13_clock_data = {
2007 .base = RCC_BASE,
2008 .num = ARRAY_SIZE(stm32mp13_clk),
2009 .clks = stm32mp13_clk,
2010 .parents = parent_mp13,
2011 .nb_parents = ARRAY_SIZE(parent_mp13),
2012 .gates = gates_mp13,
2013 .nb_gates = ARRAY_SIZE(gates_mp13),
2014 .div = dividers_mp13,
2015 .nb_div = ARRAY_SIZE(dividers_mp13),
2016 .osci_data = stm32mp13_osc_data,
2017 .nb_osci_data = ARRAY_SIZE(stm32mp13_osc_data),
2018 .gate_refcounts = refcounts_mp13,
2019 .pdata = &stm32mp13_clock_pdata,
2020 .ops_array = ops_array_mp13,
2021 };
2022
stm32mp1_init_clock_tree(void)2023 static int stm32mp1_init_clock_tree(void)
2024 {
2025 struct stm32_clk_priv *priv = clk_stm32_get_priv();
2026 int ret;
2027
2028 #if STM32MP_USB_PROGRAMMER
2029 int usbphy_p = _clk_stm32_get_parent(priv, _USBPHY_K);
2030 int usbo_p = _clk_stm32_get_parent(priv, _USBO_K);
2031
2032 /* Don't initialize PLL4, when used by BOOTROM */
2033 pll4_bootrom = stm32mp1_clk_is_pll4_used_by_bootrom(priv, usbphy_p);
2034 #endif
2035
2036 /*
2037 * Switch ON oscillators found in device-tree.
2038 * Note: HSI already ON after BootROM stage.
2039 */
2040 stm32_clk_oscillators_enable(priv);
2041
2042 /* Come back to HSI */
2043 ret = stm32mp1_come_back_to_hsi();
2044 if (ret != 0) {
2045 return ret;
2046 }
2047
2048 ret = stm32_clk_hsidiv_configure(priv);
2049 if (ret != 0) {
2050 return ret;
2051 }
2052
2053 ret = stm32_clk_stgen_configure(priv, _STGENC);
2054 if (ret != 0) {
2055 panic();
2056 }
2057
2058 ret = stm32_clk_dividers_configure(priv);
2059 if (ret != 0) {
2060 panic();
2061 }
2062
2063 ret = stm32_clk_pll_configure(priv);
2064 if (ret != 0) {
2065 panic();
2066 }
2067
2068 /* Wait LSE ready before to use it */
2069 ret = stm32_clk_oscillators_wait_lse_ready(priv);
2070 if (ret != 0) {
2071 panic();
2072 }
2073
2074 /* Configure with expected clock source */
2075 ret = stm32_clk_source_configure(priv);
2076 if (ret != 0) {
2077 panic();
2078 }
2079
2080 /* Configure LSE css after RTC source configuration */
2081 ret = stm32_clk_oscillators_lse_set_css(priv);
2082 if (ret != 0) {
2083 panic();
2084 }
2085
2086 #if STM32MP_USB_PROGRAMMER
2087 ret = stm32mp1_clk_check_usb_conflict(priv, usbphy_p, usbo_p);
2088 if (ret != 0) {
2089 return ret;
2090 }
2091 #endif
2092 /* reconfigure STGEN with DT config */
2093 ret = stm32_clk_stgen_configure(priv, _STGENC);
2094 if (ret != 0) {
2095 panic();
2096 }
2097
2098 /* Software Self-Refresh mode (SSR) during DDR initilialization */
2099 mmio_clrsetbits_32(priv->base + RCC_DDRITFCR,
2100 RCC_DDRITFCR_DDRCKMOD_MASK,
2101 RCC_DDRITFCR_DDRCKMOD_SSR <<
2102 RCC_DDRITFCR_DDRCKMOD_SHIFT);
2103
2104 return 0;
2105 }
2106
clk_stm32_parse_oscillator_fdt(void * fdt,int node,const char * name,struct stm32_osci_dt_cfg * osci)2107 static int clk_stm32_parse_oscillator_fdt(void *fdt, int node, const char *name,
2108 struct stm32_osci_dt_cfg *osci)
2109 {
2110 int subnode = 0;
2111
2112 /* default value oscillator not found, freq=0 */
2113 osci->freq = 0;
2114
2115 fdt_for_each_subnode(subnode, fdt, node) {
2116 const char *cchar = NULL;
2117 const fdt32_t *cuint = NULL;
2118 int ret = 0;
2119
2120 cchar = fdt_get_name(fdt, subnode, &ret);
2121 if (cchar == NULL) {
2122 return ret;
2123 }
2124
2125 if (strncmp(cchar, name, (size_t)ret) ||
2126 fdt_get_status(subnode) == DT_DISABLED) {
2127 continue;
2128 }
2129
2130 cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret);
2131 if (cuint == NULL) {
2132 return ret;
2133 }
2134
2135 osci->freq = fdt32_to_cpu(*cuint);
2136
2137 if (fdt_getprop(fdt, subnode, "st,bypass", NULL) != NULL) {
2138 osci->bypass = true;
2139 }
2140
2141 if (fdt_getprop(fdt, subnode, "st,digbypass", NULL) != NULL) {
2142 osci->digbyp = true;
2143 }
2144
2145 if (fdt_getprop(fdt, subnode, "st,css", NULL) != NULL) {
2146 osci->css = true;
2147 }
2148
2149 osci->drive = fdt_read_uint32_default(fdt, subnode, "st,drive", LSEDRV_MEDIUM_HIGH);
2150
2151 return 0;
2152 }
2153
2154 return 0;
2155 }
2156
stm32_clk_parse_fdt_all_oscillator(void * fdt,struct stm32_clk_platdata * pdata)2157 static int stm32_clk_parse_fdt_all_oscillator(void *fdt, struct stm32_clk_platdata *pdata)
2158 {
2159 int fdt_err = 0;
2160 uint32_t i = 0;
2161 int node = 0;
2162
2163 node = fdt_path_offset(fdt, "/clocks");
2164 if (node < 0) {
2165 return -FDT_ERR_NOTFOUND;
2166 }
2167
2168 for (i = 0; i < pdata->nosci; i++) {
2169 const char *name = NULL;
2170
2171 name = clk_stm32_get_oscillator_name((enum stm32_osc)i);
2172 if (name == NULL) {
2173 continue;
2174 }
2175
2176 fdt_err = clk_stm32_parse_oscillator_fdt(fdt, node, name, &pdata->osci[i]);
2177 if (fdt_err < 0) {
2178 panic();
2179 }
2180 }
2181
2182 return 0;
2183 }
2184
2185 #define RCC_PLL_NAME_SIZE 12
2186
clk_stm32_load_vco_config(void * fdt,int subnode,struct stm32_pll_vco * vco)2187 static int clk_stm32_load_vco_config(void *fdt, int subnode, struct stm32_pll_vco *vco)
2188 {
2189 int err = 0;
2190
2191 err = fdt_read_uint32_array(fdt, subnode, "divmn", (int)PLL_DIV_MN_NB, vco->div_mn);
2192 if (err != 0) {
2193 return err;
2194 }
2195
2196 err = fdt_read_uint32_array(fdt, subnode, "csg", (int)PLL_CSG_NB, vco->csg);
2197
2198 vco->csg_enabled = (err == 0);
2199
2200 if (err == -FDT_ERR_NOTFOUND) {
2201 err = 0;
2202 }
2203
2204 if (err != 0) {
2205 return err;
2206 }
2207
2208 vco->status = RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN | RCC_PLLNCR_PLLON;
2209
2210 vco->frac = fdt_read_uint32_default(fdt, subnode, "frac", 0);
2211
2212 vco->src = fdt_read_uint32_default(fdt, subnode, "src", UINT32_MAX);
2213
2214 return 0;
2215 }
2216
clk_stm32_load_output_config(void * fdt,int subnode,struct stm32_pll_output * output)2217 static int clk_stm32_load_output_config(void *fdt, int subnode, struct stm32_pll_output *output)
2218 {
2219 int err = 0;
2220
2221 err = fdt_read_uint32_array(fdt, subnode, "st,pll_div_pqr", (int)PLL_DIV_PQR_NB,
2222 output->output);
2223 if (err != 0) {
2224 return err;
2225 }
2226
2227 return 0;
2228 }
2229
clk_stm32_parse_pll_fdt(void * fdt,int subnode,struct stm32_pll_dt_cfg * pll)2230 static int clk_stm32_parse_pll_fdt(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll)
2231 {
2232 const fdt32_t *cuint = NULL;
2233 int subnode_pll = 0;
2234 int subnode_vco = 0;
2235 int err = 0;
2236
2237 cuint = fdt_getprop(fdt, subnode, "st,pll", NULL);
2238 if (!cuint) {
2239 return -FDT_ERR_NOTFOUND;
2240 }
2241
2242 subnode_pll = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint));
2243 if (subnode_pll < 0) {
2244 return -FDT_ERR_NOTFOUND;
2245 }
2246
2247 cuint = fdt_getprop(fdt, subnode_pll, "st,pll_vco", NULL);
2248 if (!cuint) {
2249 return -FDT_ERR_NOTFOUND;
2250 }
2251
2252 subnode_vco = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint));
2253 if (subnode_vco < 0) {
2254 return -FDT_ERR_NOTFOUND;
2255 }
2256
2257 err = clk_stm32_load_vco_config(fdt, subnode_vco, &pll->vco);
2258 if (err != 0) {
2259 return err;
2260 }
2261
2262 err = clk_stm32_load_output_config(fdt, subnode_pll, &pll->output);
2263 if (err != 0) {
2264 return err;
2265 }
2266
2267 return 0;
2268 }
2269
stm32_clk_parse_fdt_all_pll(void * fdt,int node,struct stm32_clk_platdata * pdata)2270 static int stm32_clk_parse_fdt_all_pll(void *fdt, int node, struct stm32_clk_platdata *pdata)
2271 {
2272 size_t i = 0U;
2273
2274 /* PLL1 is not configurable with device tree */
2275 for (i = _PLL2; i < pdata->npll; i++) {
2276 struct stm32_pll_dt_cfg *pll = &pdata->pll[i];
2277 char name[RCC_PLL_NAME_SIZE];
2278 int subnode = 0;
2279 int err = 0;
2280
2281 snprintf(name, sizeof(name), "st,pll@%u", i);
2282
2283 subnode = fdt_subnode_offset(fdt, node, name);
2284 if (!fdt_check_node(subnode)) {
2285 continue;
2286 }
2287
2288 err = clk_stm32_parse_pll_fdt(fdt, subnode, pll);
2289 if (err != 0) {
2290 panic();
2291 }
2292 }
2293
2294 return 0;
2295 }
2296
stm32_clk_parse_fdt(struct stm32_clk_platdata * pdata)2297 static int stm32_clk_parse_fdt(struct stm32_clk_platdata *pdata)
2298 {
2299 void *fdt = NULL;
2300 int node;
2301 uint32_t err;
2302
2303 if (fdt_get_address(&fdt) == 0) {
2304 return -ENOENT;
2305 }
2306
2307 node = fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT);
2308 if (node < 0) {
2309 panic();
2310 }
2311
2312 err = stm32_clk_parse_fdt_all_oscillator(fdt, pdata);
2313 if (err != 0) {
2314 return err;
2315 }
2316
2317 err = stm32_clk_parse_fdt_all_pll(fdt, node, pdata);
2318 if (err != 0) {
2319 return err;
2320 }
2321
2322 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,clkdiv", pdata->clkdiv, &pdata->nclkdiv);
2323 if (err != 0) {
2324 return err;
2325 }
2326
2327 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,clksrc", pdata->clksrc, &pdata->nclksrc);
2328 if (err != 0) {
2329 return err;
2330 }
2331
2332 return 0;
2333 }
2334
stm32mp1_clk_rcc_regs_lock(void)2335 void stm32mp1_clk_rcc_regs_lock(void)
2336 {
2337 clk_stm32_rcc_regs_lock();
2338 }
2339
stm32mp1_clk_rcc_regs_unlock(void)2340 void stm32mp1_clk_rcc_regs_unlock(void)
2341 {
2342 clk_stm32_rcc_regs_unlock();
2343 }
2344
stm32mp1_clk_init(void)2345 int stm32mp1_clk_init(void)
2346 {
2347 int ret;
2348
2349 /* compute the PLL1 settings, not read in device tree */
2350 ret = clk_compute_pll1_settings(PLL1_NOMINAL_FREQ_IN_KHZ);
2351 if (ret != 0) {
2352 return ret;
2353 }
2354
2355 ret = stm32mp1_init_clock_tree();
2356 if (ret != 0) {
2357 return ret;
2358 }
2359
2360 clk_stm32_enable_critical_clocks();
2361
2362 return 0;
2363 }
2364
stm32mp1_clk_probe(void)2365 int stm32mp1_clk_probe(void)
2366 {
2367 uintptr_t base = RCC_BASE;
2368 int ret;
2369
2370 ret = stm32_clk_parse_fdt(&stm32mp13_clock_pdata);
2371 if (ret != 0) {
2372 return ret;
2373 }
2374
2375 ret = clk_stm32_init(&stm32mp13_clock_data, base);
2376
2377 return ret;
2378 }
2379