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1 /*
2  * Copyright (c) 2021-2024, STMicroelectronics - All Rights Reserved
3  *
4  * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
5  */
6 
7 #ifndef STM32MP2_DDR_REGS_H
8 #define STM32MP2_DDR_REGS_H
9 
10 #include <drivers/st/stm32mp_ddrctrl_regs.h>
11 #include <lib/utils_def.h>
12 
13 /* DDR Physical Interface Control (DDRPHYC) registers*/
14 struct stm32mp_ddrphy {
15 	uint32_t dummy;
16 } __packed;
17 
18 /* DDRPHY registers offsets */
19 #define DDRPHY_INITENG0_P0_SEQ0BDISABLEFLAG6	U(0x240004)
20 #define DDRPHY_INITENG0_P0_PHYINLPX		U(0x2400A0)
21 #define DDRPHY_DRTUB0_UCCLKHCLKENABLES		U(0x300200)
22 #define DDRPHY_APBONLY0_MICROCONTMUXSEL		U(0x340000)
23 
24 /* DDRPHY registers fields */
25 #define DDRPHY_INITENG0_P0_PHYINLPX_PHYINLP3			BIT(0)
26 #define DDRPHY_DRTUB0_UCCLKHCLKENABLES_UCCLKEN			BIT(0)
27 #define DDRPHY_DRTUB0_UCCLKHCLKENABLES_HCLKEN			BIT(1)
28 #define DDRPHY_APBONLY0_MICROCONTMUXSEL_MICROCONTMUXSEL		BIT(0)
29 
30 /* DDRDBG registers offsets */
31 #define DDRDBG_LP_DISABLE			U(0x0)
32 #define DDRDBG_BYPASS_PCLKEN			U(0x4)
33 
34 /* DDRDBG registers fields */
35 #define DDRDBG_LP_DISABLE_LPI_XPI_DISABLE	BIT(0)
36 #define DDRDBG_LP_DISABLE_LPI_DDRC_DISABLE	BIT(8)
37 
38 #endif /* STM32MP2_DDR_REGS_H */
39