1 /* 2 * Copyright (c) 2018-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP2_PWR_H 8 #define STM32MP2_PWR_H 9 10 #include <lib/utils_def.h> 11 12 #define PWR_CR1 U(0x00) 13 #define PWR_CR2 U(0x04) 14 #define PWR_CR3 U(0x08) 15 #define PWR_CR4 U(0x0C) 16 #define PWR_CR5 U(0x10) 17 #define PWR_CR6 U(0x14) 18 #define PWR_CR7 U(0x18) 19 #define PWR_CR8 U(0x1C) 20 #define PWR_CR9 U(0x20) 21 #define PWR_CR10 U(0x24) 22 #define PWR_CR11 U(0x28) 23 #define PWR_CR12 U(0x2C) 24 #define PWR_UCPDR U(0x30) 25 #define PWR_BDCR1 U(0x38) 26 #define PWR_BDCR2 U(0x3C) 27 #define PWR_CPU1CR U(0x40) 28 #define PWR_CPU2CR U(0x44) 29 #define PWR_CPU3CR U(0x48) 30 #define PWR_D1CR U(0x4C) 31 #define PWR_D2CR U(0x50) 32 #define PWR_D3CR U(0x54) 33 #define PWR_WKUPCR1 U(0x60) 34 #define PWR_WKUPCR2 U(0x64) 35 #define PWR_WKUPCR3 U(0x68) 36 #define PWR_WKUPCR4 U(0x6C) 37 #define PWR_WKUPCR5 U(0x70) 38 #define PWR_WKUPCR6 U(0x74) 39 #define PWR_D3WKUPENR U(0x98) 40 #define PWR_RSECCFGR U(0x100) 41 #define PWR_RPRIVCFGR U(0x104) 42 #define PWR_R0CIDCFGR U(0x108) 43 #define PWR_R1CIDCFGR U(0x10C) 44 #define PWR_R2CIDCFGR U(0x110) 45 #define PWR_R3CIDCFGR U(0x114) 46 #define PWR_R4CIDCFGR U(0x118) 47 #define PWR_R5CIDCFGR U(0x11C) 48 #define PWR_R6CIDCFGR U(0x120) 49 #define PWR_WIOSECCFGR U(0x180) 50 #define PWR_WIOPRIVCFGR U(0x184) 51 #define PWR_WIO1CIDCFGR U(0x188) 52 #define PWR_WIO1SEMCR U(0x18C) 53 #define PWR_WIO2CIDCFGR U(0x190) 54 #define PWR_WIO2SEMCR U(0x194) 55 #define PWR_WIO3CIDCFGR U(0x198) 56 #define PWR_WIO3SEMCR U(0x19C) 57 #define PWR_WIO4CIDCFGR U(0x1A0) 58 #define PWR_WIO4SEMCR U(0x1A4) 59 #define PWR_WIO5CIDCFGR U(0x1A8) 60 #define PWR_WIO5SEMCR U(0x1AC) 61 #define PWR_WIO6CIDCFGR U(0x1B0) 62 #define PWR_WIO6SEMCR U(0x1B4) 63 #define PWR_CPU1D1SR U(0x200) 64 #define PWR_CPU2D2SR U(0x204) 65 #define PWR_CPU3D3SR U(0x208) 66 #define PWR_DBGR U(0x308) 67 #define PWR_VERR U(0x3F4) 68 #define PWR_IPIDR U(0x3F8) 69 #define PWR_SIDR U(0x3FC) 70 71 /* PWR_CR1 register fields */ 72 #define PWR_CR1_VDDIO3VMEN BIT_32(0) 73 #define PWR_CR1_VDDIO4VMEN BIT_32(1) 74 #define PWR_CR1_USB33VMEN BIT_32(2) 75 #define PWR_CR1_UCPDVMEN BIT_32(3) 76 #define PWR_CR1_AVMEN BIT_32(4) 77 #define PWR_CR1_VDDIO3SV BIT_32(8) 78 #define PWR_CR1_VDDIO4SV BIT_32(9) 79 #define PWR_CR1_USB33SV BIT_32(10) 80 #define PWR_CR1_UCPDSV BIT_32(11) 81 #define PWR_CR1_ASV BIT_32(12) 82 #define PWR_CR1_VDDIO3RDY BIT_32(16) 83 #define PWR_CR1_VDDIO4RDY BIT_32(17) 84 #define PWR_CR1_USB33RDY BIT_32(18) 85 #define PWR_CR1_UCPDRDY BIT_32(19) 86 #define PWR_CR1_ARDY BIT_32(20) 87 #define PWR_CR1_VDDIOVRSEL BIT_32(24) 88 #define PWR_CR1_VDDIO3VRSEL BIT_32(25) 89 #define PWR_CR1_VDDIO4VRSEL BIT_32(26) 90 #define PWR_CR1_GPVMO BIT_32(31) 91 92 /* PWR_CR2 register fields */ 93 #define PWR_CR2_MONEN BIT_32(0) 94 #define PWR_CR2_VBATL BIT_32(8) 95 #define PWR_CR2_VBATH BIT_32(9) 96 #define PWR_CR2_TEMPL BIT_32(10) 97 #define PWR_CR2_TEMPH BIT_32(11) 98 99 /* PWR_CR3 register fields */ 100 #define PWR_CR3_PVDEN BIT_32(0) 101 #define PWR_CR3_PVDO BIT_32(8) 102 103 /* PWR_CR5 register fields */ 104 #define PWR_CR5_VCOREMONEN BIT_32(0) 105 #define PWR_CR5_VCOREL BIT_32(8) 106 #define PWR_CR5_VCOREH BIT_32(9) 107 108 /* PWR_CR6 register fields */ 109 #define PWR_CR6_VCPUMONEN BIT_32(0) 110 #define PWR_CR6_VCPULLS BIT_32(4) 111 #define PWR_CR6_VCPUL BIT_32(8) 112 #define PWR_CR6_VCPUH BIT_32(9) 113 114 /* PWR_CR7 register fields */ 115 #define PWR_CR7_VDDIO2VMEN BIT_32(0) 116 #define PWR_CR7_VDDIO2SV BIT_32(8) 117 #define PWR_CR7_VDDIO2RDY BIT_32(16) 118 #define PWR_CR7_VDDIO2VRSEL BIT_32(24) 119 #define PWR_CR7_VDDIO2VRSTBY BIT_32(25) 120 121 /* PWR_CR8 register fields */ 122 #define PWR_CR8_VDDIO1VMEN BIT_32(0) 123 #define PWR_CR8_VDDIO1SV BIT_32(8) 124 #define PWR_CR8_VDDIO1RDY BIT_32(16) 125 #define PWR_CR8_VDDIO1VRSEL BIT_32(24) 126 #define PWR_CR8_VDDIO1VRSTBY BIT_32(25) 127 128 /* PWR_CR9 register fields */ 129 #define PWR_CR9_BKPRBSEN BIT_32(0) 130 #define PWR_CR9_LPR1BSEN BIT_32(4) 131 132 /* PWR_CR10 register fields */ 133 #define PWR_CR10_RETRBSEN_MASK GENMASK_32(1, 0) 134 #define PWR_CR10_RETRBSEN_SHIFT U(0) 135 136 /* PWR_CR11 register fields */ 137 #define PWR_CR11_DDRRETDIS BIT_32(0) 138 139 /* PWR_CR12 register fields */ 140 #define PWR_CR12_GPUVMEN BIT_32(0) 141 #define PWR_CR12_GPULVTEN BIT_32(1) 142 #define PWR_CR12_GPUSV BIT_32(8) 143 #define PWR_CR12_VDDGPURDY BIT_32(16) 144 145 /* PWR_UCPDR register fields */ 146 #define PWR_UCPDR_UCPD_DBDIS BIT_32(0) 147 #define PWR_UCPDR_UCPD_STBY BIT_32(1) 148 149 /* PWR_BDCR1 register fields */ 150 #define PWR_BDCR1_DBD3P BIT_32(0) 151 152 /* PWR_BDCR2 register fields */ 153 #define PWR_BDCR2_DBP BIT_32(0) 154 155 /* PWR_CPU1CR register fields */ 156 #define PWR_CPU1CR_PDDS_D2 BIT_32(0) 157 #define PWR_CPU1CR_PDDS_D1 BIT_32(1) 158 #define PWR_CPU1CR_VBF BIT_32(4) 159 #define PWR_CPU1CR_STOPF BIT_32(5) 160 #define PWR_CPU1CR_SBF BIT_32(6) 161 #define PWR_CPU1CR_SBF_D1 BIT_32(7) 162 #define PWR_CPU1CR_SBF_D3 BIT_32(8) 163 #define PWR_CPU1CR_CSSF BIT_32(9) 164 #define PWR_CPU1CR_STANDBYWFIL2 BIT_32(15) 165 #define PWR_CPU1CR_LPDS_D1 BIT_32(16) 166 #define PWR_CPU1CR_LVDS_D1 BIT_32(17) 167 168 /* PWR_CPU2CR register fields */ 169 #define PWR_CPU2CR_PDDS_D2 BIT_32(0) 170 #define PWR_CPU2CR_VBF BIT_32(4) 171 #define PWR_CPU2CR_STOPF BIT_32(5) 172 #define PWR_CPU2CR_SBF BIT_32(6) 173 #define PWR_CPU2CR_SBF_D2 BIT_32(7) 174 #define PWR_CPU2CR_SBF_D3 BIT_32(8) 175 #define PWR_CPU2CR_CSSF BIT_32(9) 176 #define PWR_CPU2CR_DEEPSLEEP BIT_32(15) 177 #define PWR_CPU2CR_LPDS_D2 BIT_32(16) 178 #define PWR_CPU2CR_LVDS_D2 BIT_32(17) 179 180 /* PWR_CPU3CR register fields */ 181 #define PWR_CPU3CR_VBF BIT_32(4) 182 #define PWR_CPU3CR_SBF_D3 BIT_32(8) 183 #define PWR_CPU3CR_CSSF BIT_32(9) 184 #define PWR_CPU3CR_DEEPSLEEP BIT_32(15) 185 186 /* PWR_D1CR register fields */ 187 #define PWR_D1CR_LPCFG_D1 BIT_32(0) 188 #define PWR_D1CR_POPL_D1_MASK GENMASK_32(12, 8) 189 #define PWR_D1CR_POPL_D1_SHIFT U(8) 190 191 /* PWR_D2CR register fields */ 192 #define PWR_D2CR_LPCFG_D2 BIT_32(0) 193 #define PWR_D2CR_POPL_D2_MASK GENMASK_32(12, 8) 194 #define PWR_D2CR_POPL_D2_SHIFT U(8) 195 #define PWR_D2CR_LPLVDLY_D2_MASK GENMASK_32(18, 16) 196 #define PWR_D2CR_LPLVDLY_D2_SHIFT U(16) 197 #define PWR_D2CR_PODH_D2_MASK GENMASK_32(27, 24) 198 #define PWR_D2CR_PODH_D2_SHIFT U(24) 199 200 /* PWR_D3CR register fields */ 201 #define PWR_D3CR_PDDS_D3 BIT_32(0) 202 #define PWR_D3CR_D3RDY BIT_32(31) 203 204 /* PWR_WKUPCR1 register fields */ 205 #define PWR_WKUPCR1_WKUPC BIT_32(0) 206 #define PWR_WKUPCR1_WKUPP BIT_32(8) 207 #define PWR_WKUPCR1_WKUPPUPD_MASK GENMASK_32(13, 12) 208 #define PWR_WKUPCR1_WKUPPUPD_SHIFT U(12) 209 #define PWR_WKUPCR1_WKUPENCPU1 BIT_32(16) 210 #define PWR_WKUPCR1_WKUPENCPU2 BIT_32(17) 211 #define PWR_WKUPCR1_WKUPF BIT_32(31) 212 213 /* PWR_WKUPCR2 register fields */ 214 #define PWR_WKUPCR2_WKUPC BIT_32(0) 215 #define PWR_WKUPCR2_WKUPP BIT_32(8) 216 #define PWR_WKUPCR2_WKUPPUPD_MASK GENMASK_32(13, 12) 217 #define PWR_WKUPCR2_WKUPPUPD_SHIFT U(12) 218 #define PWR_WKUPCR2_WKUPENCPU1 BIT_32(16) 219 #define PWR_WKUPCR2_WKUPENCPU2 BIT_32(17) 220 #define PWR_WKUPCR2_WKUPF BIT_32(31) 221 222 /* PWR_WKUPCR3 register fields */ 223 #define PWR_WKUPCR3_WKUPC BIT_32(0) 224 #define PWR_WKUPCR3_WKUPP BIT_32(8) 225 #define PWR_WKUPCR3_WKUPPUPD_MASK GENMASK_32(13, 12) 226 #define PWR_WKUPCR3_WKUPPUPD_SHIFT U(12) 227 #define PWR_WKUPCR3_WKUPENCPU1 BIT_32(16) 228 #define PWR_WKUPCR3_WKUPENCPU2 BIT_32(17) 229 #define PWR_WKUPCR3_WKUPF BIT_32(31) 230 231 /* PWR_WKUPCR4 register fields */ 232 #define PWR_WKUPCR4_WKUPC BIT_32(0) 233 #define PWR_WKUPCR4_WKUPP BIT_32(8) 234 #define PWR_WKUPCR4_WKUPPUPD_MASK GENMASK_32(13, 12) 235 #define PWR_WKUPCR4_WKUPPUPD_SHIFT U(12) 236 #define PWR_WKUPCR4_WKUPENCPU1 BIT_32(16) 237 #define PWR_WKUPCR4_WKUPENCPU2 BIT_32(17) 238 #define PWR_WKUPCR4_WKUPF BIT_32(31) 239 240 /* PWR_WKUPCR5 register fields */ 241 #define PWR_WKUPCR5_WKUPC BIT_32(0) 242 #define PWR_WKUPCR5_WKUPP BIT_32(8) 243 #define PWR_WKUPCR5_WKUPPUPD_MASK GENMASK_32(13, 12) 244 #define PWR_WKUPCR5_WKUPPUPD_SHIFT U(12) 245 #define PWR_WKUPCR5_WKUPENCPU1 BIT_32(16) 246 #define PWR_WKUPCR5_WKUPENCPU2 BIT_32(17) 247 #define PWR_WKUPCR5_WKUPF BIT_32(31) 248 249 /* PWR_WKUPCR6 register fields */ 250 #define PWR_WKUPCR6_WKUPC BIT_32(0) 251 #define PWR_WKUPCR6_WKUPP BIT_32(8) 252 #define PWR_WKUPCR6_WKUPPUPD_MASK GENMASK_32(13, 12) 253 #define PWR_WKUPCR6_WKUPPUPD_SHIFT U(12) 254 #define PWR_WKUPCR6_WKUPENCPU1 BIT_32(16) 255 #define PWR_WKUPCR6_WKUPENCPU2 BIT_32(17) 256 #define PWR_WKUPCR6_WKUPF BIT_32(31) 257 258 /* PWR_D3WKUPENR register fields */ 259 #define PWR_D3WKUPENR_TAMP_WKUPEN_D3 BIT_32(0) 260 261 /* PWR_RSECCFGR register fields */ 262 #define PWR_RSECCFGR_RSEC0 BIT_32(0) 263 #define PWR_RSECCFGR_RSEC1 BIT_32(1) 264 #define PWR_RSECCFGR_RSEC2 BIT_32(2) 265 #define PWR_RSECCFGR_RSEC3 BIT_32(3) 266 #define PWR_RSECCFGR_RSEC4 BIT_32(4) 267 #define PWR_RSECCFGR_RSEC5 BIT_32(5) 268 #define PWR_RSECCFGR_RSEC6 BIT_32(6) 269 270 /* PWR_RPRIVCFGR register fields */ 271 #define PWR_RPRIVCFGR_RPRIV0 BIT_32(0) 272 #define PWR_RPRIVCFGR_RPRIV1 BIT_32(1) 273 #define PWR_RPRIVCFGR_RPRIV2 BIT_32(2) 274 #define PWR_RPRIVCFGR_RPRIV3 BIT_32(3) 275 #define PWR_RPRIVCFGR_RPRIV4 BIT_32(4) 276 #define PWR_RPRIVCFGR_RPRIV5 BIT_32(5) 277 #define PWR_RPRIVCFGR_RPRIV6 BIT_32(6) 278 279 /* PWR_R0CIDCFGR register fields */ 280 #define PWR_R0CIDCFGR_CFEN BIT_32(0) 281 #define PWR_R0CIDCFGR_SCID_MASK GENMASK_32(6, 4) 282 #define PWR_R0CIDCFGR_SCID_SHIFT U(4) 283 284 /* PWR_R1CIDCFGR register fields */ 285 #define PWR_R1CIDCFGR_CFEN BIT_32(0) 286 #define PWR_R1CIDCFGR_SCID_MASK GENMASK_32(6, 4) 287 #define PWR_R1CIDCFGR_SCID_SHIFT U(4) 288 289 /* PWR_R2CIDCFGR register fields */ 290 #define PWR_R2CIDCFGR_CFEN BIT_32(0) 291 #define PWR_R2CIDCFGR_SCID_MASK GENMASK_32(6, 4) 292 #define PWR_R2CIDCFGR_SCID_SHIFT U(4) 293 294 /* PWR_R3CIDCFGR register fields */ 295 #define PWR_R3CIDCFGR_CFEN BIT_32(0) 296 #define PWR_R3CIDCFGR_SCID_MASK GENMASK_32(6, 4) 297 #define PWR_R3CIDCFGR_SCID_SHIFT U(4) 298 299 /* PWR_R4CIDCFGR register fields */ 300 #define PWR_R4CIDCFGR_CFEN BIT_32(0) 301 #define PWR_R4CIDCFGR_SCID_MASK GENMASK_32(6, 4) 302 #define PWR_R4CIDCFGR_SCID_SHIFT U(4) 303 304 /* PWR_R5CIDCFGR register fields */ 305 #define PWR_R5CIDCFGR_CFEN BIT_32(0) 306 #define PWR_R5CIDCFGR_SCID_MASK GENMASK_32(6, 4) 307 #define PWR_R5CIDCFGR_SCID_SHIFT U(4) 308 309 /* PWR_R6CIDCFGR register fields */ 310 #define PWR_R6CIDCFGR_CFEN BIT_32(0) 311 #define PWR_R6CIDCFGR_SCID_MASK GENMASK_32(6, 4) 312 #define PWR_R6CIDCFGR_SCID_SHIFT U(4) 313 314 /* PWR_WIOSECCFGR register fields */ 315 #define PWR_WIOSECCFGR_WIOSEC1 BIT_32(0) 316 #define PWR_WIOSECCFGR_WIOSEC2 BIT_32(1) 317 #define PWR_WIOSECCFGR_WIOSEC3 BIT_32(2) 318 #define PWR_WIOSECCFGR_WIOSEC4 BIT_32(3) 319 #define PWR_WIOSECCFGR_WIOSEC5 BIT_32(4) 320 #define PWR_WIOSECCFGR_WIOSEC6 BIT_32(5) 321 322 /* PWR_WIOPRIVCFGR register fields */ 323 #define PWR_WIOPRIVCFGR_WIOPRIV1 BIT_32(0) 324 #define PWR_WIOPRIVCFGR_WIOPRIV2 BIT_32(1) 325 #define PWR_WIOPRIVCFGR_WIOPRIV3 BIT_32(2) 326 #define PWR_WIOPRIVCFGR_WIOPRIV4 BIT_32(3) 327 #define PWR_WIOPRIVCFGR_WIOPRIV5 BIT_32(4) 328 #define PWR_WIOPRIVCFGR_WIOPRIV6 BIT_32(5) 329 330 /* PWR_WIO1CIDCFGR register fields */ 331 #define PWR_WIO1CIDCFGR_CFEN BIT_32(0) 332 #define PWR_WIO1CIDCFGR_SEM_EN BIT_32(1) 333 #define PWR_WIO1CIDCFGR_SCID_MASK GENMASK_32(6, 4) 334 #define PWR_WIO1CIDCFGR_SCID_SHIFT U(4) 335 #define PWR_WIO1CIDCFGR_SEMWLC0 BIT_32(16) 336 #define PWR_WIO1CIDCFGR_SEMWLC1 BIT_32(17) 337 #define PWR_WIO1CIDCFGR_SEMWLC2 BIT_32(18) 338 #define PWR_WIO1CIDCFGR_SEMWLC3 BIT_32(19) 339 #define PWR_WIO1CIDCFGR_SEMWLC4 BIT_32(20) 340 #define PWR_WIO1CIDCFGR_SEMWLC5 BIT_32(21) 341 #define PWR_WIO1CIDCFGR_SEMWLC6 BIT_32(22) 342 #define PWR_WIO1CIDCFGR_SEMWLC7 BIT_32(23) 343 344 /* PWR_WIO1SEMCR register fields */ 345 #define PWR_WIO1SEMCR_SEM_MUTEX BIT_32(0) 346 #define PWR_WIO1SEMCR_SEMCID_MASK GENMASK_32(6, 4) 347 #define PWR_WIO1SEMCR_SEMCID_SHIFT U(4) 348 349 /* PWR_WIO2CIDCFGR register fields */ 350 #define PWR_WIO2CIDCFGR_CFEN BIT_32(0) 351 #define PWR_WIO2CIDCFGR_SEM_EN BIT_32(1) 352 #define PWR_WIO2CIDCFGR_SCID_MASK GENMASK_32(6, 4) 353 #define PWR_WIO2CIDCFGR_SCID_SHIFT U(4) 354 #define PWR_WIO2CIDCFGR_SEMWLC0 BIT_32(16) 355 #define PWR_WIO2CIDCFGR_SEMWLC1 BIT_32(17) 356 #define PWR_WIO2CIDCFGR_SEMWLC2 BIT_32(18) 357 #define PWR_WIO2CIDCFGR_SEMWLC3 BIT_32(19) 358 #define PWR_WIO2CIDCFGR_SEMWLC4 BIT_32(20) 359 #define PWR_WIO2CIDCFGR_SEMWLC5 BIT_32(21) 360 #define PWR_WIO2CIDCFGR_SEMWLC6 BIT_32(22) 361 #define PWR_WIO2CIDCFGR_SEMWLC7 BIT_32(23) 362 363 /* PWR_WIO2SEMCR register fields */ 364 #define PWR_WIO2SEMCR_SEM_MUTEX BIT_32(0) 365 #define PWR_WIO2SEMCR_SEMCID_MASK GENMASK_32(6, 4) 366 #define PWR_WIO2SEMCR_SEMCID_SHIFT U(4) 367 368 /* PWR_WIO3CIDCFGR register fields */ 369 #define PWR_WIO3CIDCFGR_CFEN BIT_32(0) 370 #define PWR_WIO3CIDCFGR_SEM_EN BIT_32(1) 371 #define PWR_WIO3CIDCFGR_SCID_MASK GENMASK_32(6, 4) 372 #define PWR_WIO3CIDCFGR_SCID_SHIFT U(4) 373 #define PWR_WIO3CIDCFGR_SEMWLC0 BIT_32(16) 374 #define PWR_WIO3CIDCFGR_SEMWLC1 BIT_32(17) 375 #define PWR_WIO3CIDCFGR_SEMWLC2 BIT_32(18) 376 #define PWR_WIO3CIDCFGR_SEMWLC3 BIT_32(19) 377 #define PWR_WIO3CIDCFGR_SEMWLC4 BIT_32(20) 378 #define PWR_WIO3CIDCFGR_SEMWLC5 BIT_32(21) 379 #define PWR_WIO3CIDCFGR_SEMWLC6 BIT_32(22) 380 #define PWR_WIO3CIDCFGR_SEMWLC7 BIT_32(23) 381 382 /* PWR_WIO3SEMCR register fields */ 383 #define PWR_WIO3SEMCR_SEM_MUTEX BIT_32(0) 384 #define PWR_WIO3SEMCR_SEMCID_MASK GENMASK_32(6, 4) 385 #define PWR_WIO3SEMCR_SEMCID_SHIFT U(4) 386 387 /* PWR_WIO4CIDCFGR register fields */ 388 #define PWR_WIO4CIDCFGR_CFEN BIT_32(0) 389 #define PWR_WIO4CIDCFGR_SEM_EN BIT_32(1) 390 #define PWR_WIO4CIDCFGR_SCID_MASK GENMASK_32(6, 4) 391 #define PWR_WIO4CIDCFGR_SCID_SHIFT U(4) 392 #define PWR_WIO4CIDCFGR_SEMWLC0 BIT_32(16) 393 #define PWR_WIO4CIDCFGR_SEMWLC1 BIT_32(17) 394 #define PWR_WIO4CIDCFGR_SEMWLC2 BIT_32(18) 395 #define PWR_WIO4CIDCFGR_SEMWLC3 BIT_32(19) 396 #define PWR_WIO4CIDCFGR_SEMWLC4 BIT_32(20) 397 #define PWR_WIO4CIDCFGR_SEMWLC5 BIT_32(21) 398 #define PWR_WIO4CIDCFGR_SEMWLC6 BIT_32(22) 399 #define PWR_WIO4CIDCFGR_SEMWLC7 BIT_32(23) 400 401 /* PWR_WIO4SEMCR register fields */ 402 #define PWR_WIO4SEMCR_SEM_MUTEX BIT_32(0) 403 #define PWR_WIO4SEMCR_SEMCID_MASK GENMASK_32(6, 4) 404 #define PWR_WIO4SEMCR_SEMCID_SHIFT U(4) 405 406 /* PWR_WIO5CIDCFGR register fields */ 407 #define PWR_WIO5CIDCFGR_CFEN BIT_32(0) 408 #define PWR_WIO5CIDCFGR_SEM_EN BIT_32(1) 409 #define PWR_WIO5CIDCFGR_SCID_MASK GENMASK_32(6, 4) 410 #define PWR_WIO5CIDCFGR_SCID_SHIFT U(4) 411 #define PWR_WIO5CIDCFGR_SEMWLC0 BIT_32(16) 412 #define PWR_WIO5CIDCFGR_SEMWLC1 BIT_32(17) 413 #define PWR_WIO5CIDCFGR_SEMWLC2 BIT_32(18) 414 #define PWR_WIO5CIDCFGR_SEMWLC3 BIT_32(19) 415 #define PWR_WIO5CIDCFGR_SEMWLC4 BIT_32(20) 416 #define PWR_WIO5CIDCFGR_SEMWLC5 BIT_32(21) 417 #define PWR_WIO5CIDCFGR_SEMWLC6 BIT_32(22) 418 #define PWR_WIO5CIDCFGR_SEMWLC7 BIT_32(23) 419 420 /* PWR_WIO5SEMCR register fields */ 421 #define PWR_WIO5SEMCR_SEM_MUTEX BIT_32(0) 422 #define PWR_WIO5SEMCR_SEMCID_MASK GENMASK_32(6, 4) 423 #define PWR_WIO5SEMCR_SEMCID_SHIFT U(4) 424 425 /* PWR_WIO6CIDCFGR register fields */ 426 #define PWR_WIO6CIDCFGR_CFEN BIT_32(0) 427 #define PWR_WIO6CIDCFGR_SEM_EN BIT_32(1) 428 #define PWR_WIO6CIDCFGR_SCID_MASK GENMASK_32(6, 4) 429 #define PWR_WIO6CIDCFGR_SCID_SHIFT U(4) 430 #define PWR_WIO6CIDCFGR_SEMWLC0 BIT_32(16) 431 #define PWR_WIO6CIDCFGR_SEMWLC1 BIT_32(17) 432 #define PWR_WIO6CIDCFGR_SEMWLC2 BIT_32(18) 433 #define PWR_WIO6CIDCFGR_SEMWLC3 BIT_32(19) 434 #define PWR_WIO6CIDCFGR_SEMWLC4 BIT_32(20) 435 #define PWR_WIO6CIDCFGR_SEMWLC5 BIT_32(21) 436 #define PWR_WIO6CIDCFGR_SEMWLC6 BIT_32(22) 437 #define PWR_WIO6CIDCFGR_SEMWLC7 BIT_32(23) 438 439 /* PWR_WIO6SEMCR register fields */ 440 #define PWR_WIO6SEMCR_SEM_MUTEX BIT_32(0) 441 #define PWR_WIO6SEMCR_SEMCID_MASK GENMASK_32(6, 4) 442 #define PWR_WIO6SEMCR_SEMCID_SHIFT U(4) 443 444 /* PWR_CPU1D1SR register fields */ 445 #define PWR_CPU1D1SR_HOLD_BOOT BIT_32(0) 446 #define PWR_CPU1D1SR_CSTATE_MASK GENMASK_32(3, 2) 447 #define PWR_CPU1D1SR_CSTATE_SHIFT U(2) 448 #define PWR_CPU1D1SR_DSTATE_MASK GENMASK_32(10, 8) 449 #define PWR_CPU1D1SR_DSTATE_SHIFT U(8) 450 451 /* PWR_CPU2D2SR register fields */ 452 #define PWR_CPU2D2SR_HOLD_BOOT BIT_32(0) 453 #define PWR_CPU2D2SR_WFBEN BIT_32(1) 454 #define PWR_CPU2D2SR_CSTATE_MASK GENMASK_32(3, 2) 455 #define PWR_CPU2D2SR_CSTATE_SHIFT U(2) 456 #define PWR_CPU2D2SR_DSTATE_MASK GENMASK_32(10, 8) 457 #define PWR_CPU2D2SR_DSTATE_SHIFT U(8) 458 459 /* PWR_CPU3D3SR register fields */ 460 #define PWR_CPU3D3SR_CSTATE_MASK GENMASK_32(3, 2) 461 #define PWR_CPU3D3SR_CSTATE_SHIFT U(2) 462 #define PWR_CPU3D3SR_DSTATE_MASK GENMASK_32(10, 8) 463 #define PWR_CPU3D3SR_DSTATE_SHIFT U(8) 464 465 /* PWR_DBGR register fields */ 466 #define PWR_DBGR_FD3S BIT_32(0) 467 #define PWR_DBGR_VDDIOKRETRAM BIT_32(16) 468 #define PWR_DBGR_VDDIOKBKPRAM BIT_32(17) 469 #define PWR_DBGR_VDDIOKD3 BIT_32(18) 470 #define PWR_DBGR_VDDIOKLPSRAM1 BIT_32(19) 471 472 /* PWR_VERR register fields */ 473 #define PWR_VERR_MINREV_MASK GENMASK_32(3, 0) 474 #define PWR_VERR_MINREV_SHIFT U(0) 475 #define PWR_VERR_MAJREV_MASK GENMASK_32(7, 4) 476 #define PWR_VERR_MAJREV_SHIFT U(4) 477 478 #endif /* STM32MP2_PWR_H */ 479