1 /* 2 * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #ifndef STM32MP_DDR_H 8 #define STM32MP_DDR_H 9 10 #include <platform_def.h> 11 12 enum stm32mp_ddr_base_type { 13 DDR_BASE, 14 DDRPHY_BASE, 15 NONE_BASE 16 }; 17 18 enum stm32mp_ddr_reg_type { 19 REG_REG, 20 REG_TIMING, 21 REG_PERF, 22 REG_MAP, 23 REGPHY_REG, 24 REGPHY_TIMING, 25 REG_TYPE_NB 26 }; 27 28 struct stm32mp_ddr_reg_desc { 29 uint16_t offset; /* Offset for base address */ 30 uint8_t par_offset; /* Offset for parameter array */ 31 #if !STM32MP13 && !STM32MP15 32 bool qd; /* quasi-dynamic register if true */ 33 #endif 34 }; 35 36 struct stm32mp_ddr_reg_info { 37 const char *name; 38 const struct stm32mp_ddr_reg_desc *desc; 39 uint8_t size; 40 enum stm32mp_ddr_base_type base; 41 }; 42 43 struct stm32mp_ddr_size { 44 uint64_t base; 45 uint64_t size; 46 }; 47 48 struct stm32mp_ddr_priv { 49 struct stm32mp_ddr_size info; 50 struct stm32mp_ddrctl *ctl; 51 struct stm32mp_ddrphy *phy; 52 uintptr_t pwr; 53 uintptr_t rcc; 54 }; 55 56 struct stm32mp_ddr_info { 57 const char *name; 58 uint32_t speed; /* in kHz */ 59 size_t size; /* Memory size in byte = col * row * width */ 60 }; 61 62 #define DDR_DELAY_1US 1U 63 #define DDR_DELAY_2US 2U 64 #define DDR_DELAY_10US 10U 65 #define DDR_DELAY_50US 50U 66 #define DDR_TIMEOUT_500US 500U 67 #define DDR_TIMEOUT_US_1S 1000000U 68 69 void stm32mp_ddr_set_reg(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_reg_type type, 70 const void *param, const struct stm32mp_ddr_reg_info *ddr_registers); 71 void stm32mp_ddr_start_sw_done(struct stm32mp_ddrctl *ctl); 72 void stm32mp_ddr_wait_sw_done_ack(struct stm32mp_ddrctl *ctl); 73 void stm32mp_ddr_enable_axi_port(struct stm32mp_ddrctl *ctl); 74 int stm32mp_ddr_disable_axi_port(struct stm32mp_ddrctl *ctl); 75 void stm32mp_ddr_enable_host_interface(struct stm32mp_ddrctl *ctl); 76 void stm32mp_ddr_disable_host_interface(struct stm32mp_ddrctl *ctl); 77 int stm32mp_ddr_sw_selfref_entry(struct stm32mp_ddrctl *ctl); 78 void stm32mp_ddr_sw_selfref_exit(struct stm32mp_ddrctl *ctl); 79 void stm32mp_ddr_set_qd3_update_conditions(struct stm32mp_ddrctl *ctl); 80 void stm32mp_ddr_unset_qd3_update_conditions(struct stm32mp_ddrctl *ctl); 81 void stm32mp_ddr_wait_refresh_update_done_ack(struct stm32mp_ddrctl *ctl); 82 int stm32mp_board_ddr_power_init(enum ddr_type ddr_type); 83 84 #endif /* STM32MP_DDR_H */ 85