1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <console/console.h>
4 #include <device/pci_def.h>
5 #include <device/pci_ops.h>
6 #include <southbridge/intel/lynxpoint/hsio/hsio.h>
7 #include <southbridge/intel/lynxpoint/pch.h>
8 #include <types.h>
9
is_9_series_pch_h(void)10 static inline bool is_9_series_pch_h(void)
11 {
12 const uint16_t devid = pci_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID);
13 return (devid & 0xfff0) == 0x8cc0;
14 }
15
early_sata_init(const uint8_t pch_revision)16 static void early_sata_init(const uint8_t pch_revision)
17 {
18 const bool is_mobile = get_pch_platform_type() != PCH_TYPE_DESKTOP;
19
20 const uint8_t lane_owner = pci_read_config8(PCH_PCIE_DEV(0), 0x410);
21 printk(BIOS_DEBUG, "HSIO lane owner: 0x%02x\n", lane_owner);
22
23 /* BWG Step 2 */
24 pci_update_config32(PCH_SATA_DEV, SATA_SCLKG, ~0x1ff, 0x183);
25
26 /* BWG Step 3: Set OOB Retry Mode */
27 pci_or_config16(PCH_SATA_DEV, SATA_PCS, 1 << 15);
28
29 /* BWG Step 4: Program the SATA mPHY tables */
30 if (pch_is_lp()) {
31 if (pch_revision >= LPT_LP_STEP_B0 && pch_revision <= LPT_LP_STEP_B2) {
32 program_hsio_sata_lpt_lp_bx(is_mobile);
33 } else {
34 printk(BIOS_ERR, "Unsupported PCH-LP stepping 0x%02x\n", pch_revision);
35 }
36 } else {
37 /** FIXME: Figure out HSIO settings for 9 series PCH-H **/
38 if (pch_revision >= LPT_H_STEP_C0 || is_9_series_pch_h()) {
39 program_hsio_sata_lpt_h_cx(is_mobile);
40 } else {
41 printk(BIOS_ERR, "Unsupported PCH-H stepping 0x%02x\n", pch_revision);
42 }
43 }
44
45 /** FIXME: Program SATA RxEq tables **/
46
47 /* BWG Step 5 */
48 /** FIXME: Only for desktop and mobile (skip this on workstation and server) **/
49 pci_or_config32(PCH_SATA_DEV, 0x98, BIT(22));
50
51 /* BWG Step 6 */
52 pci_or_config32(PCH_SATA_DEV, 0x98, BIT(19));
53
54 /* BWG Step 7 */
55 pci_update_config32(PCH_SATA_DEV, 0x98, ~(0x3f << 7), 0x04 << 7);
56
57 /* BWG Step 8 */
58 pci_or_config32(PCH_SATA_DEV, 0x98, BIT(20));
59
60 /* BWG Step 9 */
61 pci_update_config32(PCH_SATA_DEV, 0x98, ~(3 << 5), 1 << 5);
62
63 /* BWG Step 10 */
64 pci_or_config32(PCH_SATA_DEV, 0x98, BIT(18));
65
66 /* Enable SATA ports */
67 uint8_t sata_pcs = 0;
68 if (CONFIG(INTEL_LYNXPOINT_LP)) {
69 for (uint8_t i = 0; i < 4; i++) {
70 if ((lane_owner & BIT(7 - i)) == 0) {
71 sata_pcs |= BIT(i);
72 }
73 }
74 } else {
75 sata_pcs |= 0x0f;
76 for (uint8_t i = 4; i < 6; i++) {
77 if ((lane_owner & BIT(i)) == 0) {
78 sata_pcs |= BIT(i);
79 }
80 }
81 }
82 printk(BIOS_DEBUG, "SATA port enables: 0x%02x\n", sata_pcs);
83 pci_or_config8(PCH_SATA_DEV, SATA_PCS, sata_pcs);
84 }
85
early_pch_init_native(int s3resume)86 void early_pch_init_native(int s3resume)
87 {
88 const uint8_t pch_revision = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID);
89
90 RCBA16(DISPBDF) = 0x0010;
91 RCBA32_OR(FD2, PCH_ENABLE_DBDF);
92
93 /** FIXME: Check GEN_PMCON_3 and handle RTC failure? **/
94
95 RCBA32(PRSTS) = BIT(4);
96
97 early_sata_init(pch_revision);
98
99 pci_or_config8(PCH_LPC_DEV, 0xa6, 1 << 1);
100 pci_and_config8(PCH_LPC_DEV, 0xdc, ~(1 << 5 | 1 << 1));
101
102 /** TODO: Send GET HSIO VER and update ChipsetInit table? Is it needed? **/
103
104 /** FIXME: GbE handling? **/
105
106 pci_update_config32(PCH_LPC_DEV, 0xac, ~(1 << 20), 0);
107
108 for (uint8_t i = 0; i < 8; i++)
109 pci_update_config32(PCH_PCIE_DEV(i), 0x338, ~(1 << 26), 0);
110
111 pci_update_config8(PCH_PCIE_DEV(0), 0xf4, ~(3 << 5), 1 << 7);
112
113 pci_update_config8(PCH_EHCI1_DEV, 0x88, ~(1 << 2), 0);
114 if (!pch_is_lp())
115 pci_update_config8(PCH_EHCI2_DEV, 0x88, ~(1 << 2), 0);
116
117 /** FIXME: Disable SATA2 device? **/
118
119 if (pch_is_lp()) {
120 if (pch_revision >= LPT_LP_STEP_B0 && pch_revision <= LPT_LP_STEP_B2) {
121 program_hsio_xhci_lpt_lp_bx();
122 program_hsio_igbe_lpt_lp_bx();
123 } else {
124 printk(BIOS_ERR, "Unsupported PCH-LP stepping 0x%02x\n", pch_revision);
125 }
126 } else {
127 /** FIXME: Figure out HSIO settings for 9 series PCH-H **/
128 if (pch_revision >= LPT_H_STEP_C0 || is_9_series_pch_h()) {
129 program_hsio_xhci_lpt_h_cx();
130 program_hsio_igbe_lpt_h_cx();
131 } else {
132 printk(BIOS_ERR, "Unsupported PCH-H stepping 0x%02x\n", pch_revision);
133 }
134 }
135
136 early_thermal_init();
137 early_usb_init();
138 }
139
pch_dmi_setup_physical_layer(void)140 void pch_dmi_setup_physical_layer(void)
141 {
142 /** FIXME: We need to make sure the SA supports Gen2 as well **/
143 if ((RCBA32(0x21a4) & 0x0f) == 0x02) {
144 /* Set Gen 2 Common Clock N_FTS */
145 RCBA32_AND_OR(0x2340, ~0x00ff0000, 0x3a << 16);
146
147 /* Set Target Link Speed to DMI Gen2 */
148 RCBA8_AND_OR(DLCTL2, ~0x07, 0x02);
149 }
150 }
151
152 #define VC_ACTIVE (1U << 31)
153
154 #define VCNEGPND (1 << 1)
155
pch_dmi_tc_vc_mapping(const u32 vc0,const u32 vc1,const u32 vcp,const u32 vcm)156 void pch_dmi_tc_vc_mapping(const u32 vc0, const u32 vc1, const u32 vcp, const u32 vcm)
157 {
158 printk(BIOS_DEBUG, "Programming PCH DMI VC/TC mappings...\n");
159
160 RCBA32_AND_OR(CIR0050, ~(0xf << 20), 2 << 20);
161 if (vcp & VC_ACTIVE)
162 RCBA32_OR(CIR0050, 1 << 19 | 1 << 17);
163
164 RCBA32(CIR0050); /* Ensure posted write hits */
165
166 /* Use the same virtual channel mapping on both ends of the DMI link */
167 RCBA32(V0CTL) = vc0;
168 RCBA32(V1CTL) = vc1;
169 RCBA32(V1CTL); /* Ensure posted write hits */
170 RCBA32(VPCTL) = vcp;
171 RCBA32(VPCTL); /* Ensure posted write hits */
172 RCBA32(VMCTL) = vcm;
173
174 /* Lock the registers */
175 RCBA32_OR(CIR0050, 1U << 31);
176 RCBA32(CIR0050); /* Ensure posted write hits */
177
178 printk(BIOS_DEBUG, "Waiting for PCH DMI VC negotiation... ");
179 do {} while (RCBA16(V0STS) & VCNEGPND);
180 do {} while (RCBA16(V1STS) & VCNEGPND);
181 do {} while (RCBA16(VPSTS) & VCNEGPND);
182 do {} while (RCBA16(VMSTS) & VCNEGPND);
183 printk(BIOS_DEBUG, "done!\n");
184 }
185