1 /*
2 * Copyright © 2019 Google, Inc.
3 * SPDX-License-Identifier: MIT
4 */
5
6 #ifndef FREEDRENO_LAYOUT_H_
7 #define FREEDRENO_LAYOUT_H_
8
9 #include <stdbool.h>
10 #include <stdint.h>
11
12 #include "util/format/u_format.h"
13 #include "util/u_debug.h"
14 #include "util/u_math.h"
15
16 #include "common/freedreno_common.h"
17 #include "common/freedreno_dev_info.h"
18
19 BEGINC;
20
21 /* Shared freedreno mipmap layout helper
22 *
23 * It does *not* attempt to track surface transitions, in particular
24 * about UBWC state. Possibly it should, but
25 * (a) I'm not sure if in all cases we can transparently do in-
26 * place transitions (ie. a5xx textures with interleaved
27 * meta and pixel data
28 * (b) Even if we can, we probably can't assume that we have
29 * figured out yet how to do in-place transition for every
30 * generation.
31 */
32
33 /* Texture Layout on a3xx:
34 * -----------------------
35 *
36 * Each mipmap-level contains all of it's layers (ie. all cubmap
37 * faces, all 1d/2d array elements, etc). The texture sampler is
38 * programmed with the start address of each mipmap level, and hw
39 * derives the layer offset within the level.
40 *
41 *
42 * Texture Layout on a4xx+:
43 * -----------------------
44 *
45 * For cubemap and 2d array, each layer contains all of it's mipmap
46 * levels (layer_first layout).
47 *
48 * 3d textures are laid out as on a3xx.
49 *
50 * In either case, the slice represents the per-miplevel information,
51 * but in layer_first layout it only includes the first layer, and
52 * an additional offset of (rsc->layer_size * layer) must be added.
53 *
54 *
55 * UBWC Color Compressions (a5xx+):
56 * -------------------------------
57 *
58 * Color compression is only supported for tiled layouts. In general
59 * the meta "flag" buffer (ie. what holds the compression state for
60 * each block) can be separate from the color data, except for textures
61 * on a5xx where it needs to be interleaved with layers/levels of a
62 * texture.
63 */
64
65 #define FDL_MAX_MIP_LEVELS 15
66
67 struct fdl_slice {
68 uint32_t offset; /* offset of first layer in slice */
69 uint32_t size0; /* size of first layer in slice */
70 };
71
72 /* parameters for explicit (imported) layout */
73 struct fdl_explicit_layout {
74 uint32_t offset;
75 uint32_t pitch;
76 };
77
78 /**
79 * Metadata shared between vk and gallium driver for interop.
80 *
81 * NOTE: EXT_external_objects requires app to check device and driver
82 * UUIDs to ensure that the vk and gl driver are compatible. So for
83 * now we don't need any additional versioning of the metadata.
84 */
85 struct fdl_metadata {
86 uint64_t modifier;
87 };
88
89 /**
90 * Encapsulates the layout of a resource, including position of given 2d
91 * surface (layer, level) within. Or rather all the information needed
92 * to derive this.
93 */
94 struct fdl_layout {
95 struct fdl_slice slices[FDL_MAX_MIP_LEVELS];
96 struct fdl_slice ubwc_slices[FDL_MAX_MIP_LEVELS];
97 uint32_t pitch0;
98 uint32_t ubwc_width0;
99 uint64_t layer_size;
100 uint64_t ubwc_layer_size; /* in bytes */
101 bool ubwc : 1;
102 bool layer_first : 1; /* see above description */
103 bool tile_all : 1;
104 bool is_mutable : 1;
105
106 /* Note that for tiled textures, beyond a certain mipmap level (ie.
107 * when width is less than block size) things switch to linear. In
108 * general you should not directly look at fdl_layout::tile_mode,
109 * but instead use fdl_surface::tile_mode which will correctly take
110 * this into account.
111 */
112 uint32_t tile_mode : 2;
113 /* Bytes per pixel (where a "pixel" is a single row of a block in the case
114 * of compression), including each sample in the case of multisample
115 * layouts.
116 */
117 uint8_t cpp;
118
119 /**
120 * Left shift necessary to multiply by cpp. Invalid for NPOT cpp, please
121 * use fdl_cpp_shift() to sanity check you aren't hitting that case.
122 */
123 uint8_t cpp_shift;
124
125 uint32_t width0, height0, depth0;
126 uint32_t mip_levels;
127 uint32_t nr_samples;
128 enum pipe_format format;
129
130 uint64_t size; /* Size of the whole image, in bytes. */
131 uint32_t base_align; /* Alignment of the base address, in bytes. */
132 uint8_t pitchalign; /* log2(pitchalign) */
133 };
134
135 static inline uint32_t
fdl_cpp_shift(const struct fdl_layout * layout)136 fdl_cpp_shift(const struct fdl_layout *layout)
137 {
138 assert(util_is_power_of_two_or_zero(layout->cpp));
139 return layout->cpp_shift;
140 }
141
142 static inline uint32_t
fdl_pitch(const struct fdl_layout * layout,unsigned level)143 fdl_pitch(const struct fdl_layout *layout, unsigned level)
144 {
145 return align(u_minify(layout->pitch0, level), 1 << layout->pitchalign);
146 }
147
148 #define RGB_TILE_WIDTH_ALIGNMENT 64
149 #define RGB_TILE_HEIGHT_ALIGNMENT 16
150 #define UBWC_PLANE_SIZE_ALIGNMENT 4096
151
152 static inline uint32_t
fdl_ubwc_pitch(const struct fdl_layout * layout,unsigned level)153 fdl_ubwc_pitch(const struct fdl_layout *layout, unsigned level)
154 {
155 if (!layout->ubwc)
156 return 0;
157 return align(u_minify(layout->ubwc_width0, level), RGB_TILE_WIDTH_ALIGNMENT);
158 }
159
160 static inline uint32_t
fdl_layer_stride(const struct fdl_layout * layout,unsigned level)161 fdl_layer_stride(const struct fdl_layout *layout, unsigned level)
162 {
163 if (layout->layer_first)
164 return layout->layer_size;
165 else
166 return layout->slices[level].size0;
167 }
168
169 /* a2xx is special and needs PoT alignment for mipmaps: */
170 static inline uint32_t
fdl2_pitch(const struct fdl_layout * layout,unsigned level)171 fdl2_pitch(const struct fdl_layout *layout, unsigned level)
172 {
173 uint32_t pitch = fdl_pitch(layout, level);
174 if (level)
175 pitch = util_next_power_of_two(pitch);
176 return pitch;
177 }
178
179 static inline uint32_t
fdl2_pitch_pixels(const struct fdl_layout * layout,unsigned level)180 fdl2_pitch_pixels(const struct fdl_layout *layout, unsigned level)
181 {
182 return fdl2_pitch(layout, level) >> fdl_cpp_shift(layout);
183 }
184
185 static inline uint32_t
fdl_surface_offset(const struct fdl_layout * layout,unsigned level,unsigned layer)186 fdl_surface_offset(const struct fdl_layout *layout, unsigned level,
187 unsigned layer)
188 {
189 const struct fdl_slice *slice = &layout->slices[level];
190 return slice->offset + fdl_layer_stride(layout, level) * layer;
191 }
192
193 static inline uint32_t
fdl_ubwc_offset(const struct fdl_layout * layout,unsigned level,unsigned layer)194 fdl_ubwc_offset(const struct fdl_layout *layout, unsigned level, unsigned layer)
195 {
196 const struct fdl_slice *slice = &layout->ubwc_slices[level];
197 return slice->offset + layer * layout->ubwc_layer_size;
198 }
199
200 /* Minimum layout width to enable UBWC. */
201 #define FDL_MIN_UBWC_WIDTH 16
202
203 static inline bool
fdl_level_linear(const struct fdl_layout * layout,int level)204 fdl_level_linear(const struct fdl_layout *layout, int level)
205 {
206 if (layout->tile_all)
207 return false;
208
209 unsigned w = u_minify(layout->width0, level);
210 if (w < FDL_MIN_UBWC_WIDTH)
211 return true;
212
213 return false;
214 }
215
216 static inline uint32_t
fdl_tile_mode(const struct fdl_layout * layout,int level)217 fdl_tile_mode(const struct fdl_layout *layout, int level)
218 {
219 if (layout->tile_mode && fdl_level_linear(layout, level))
220 return 0; /* linear */
221 else
222 return layout->tile_mode;
223 }
224
225 static inline bool
fdl_ubwc_enabled(const struct fdl_layout * layout,int level)226 fdl_ubwc_enabled(const struct fdl_layout *layout, int level)
227 {
228 return layout->ubwc && !fdl_level_linear(layout, level);
229 }
230
231 const char *fdl_tile_mode_desc(const struct fdl_layout *layout, int level);
232
233 void fdl_layout_buffer(struct fdl_layout *layout, uint32_t size);
234
235 void fdl5_layout(struct fdl_layout *layout, enum pipe_format format,
236 uint32_t nr_samples, uint32_t width0, uint32_t height0,
237 uint32_t depth0, uint32_t mip_levels, uint32_t array_size,
238 bool is_3d);
239
240 bool fdl6_layout(struct fdl_layout *layout, const struct fd_dev_info *info,
241 enum pipe_format format, uint32_t nr_samples, uint32_t width0,
242 uint32_t height0, uint32_t depth0, uint32_t mip_levels,
243 uint32_t array_size, bool is_3d, bool is_mutable,
244 struct fdl_explicit_layout *plane_layout);
245
246 static inline void
fdl_set_pitchalign(struct fdl_layout * layout,unsigned pitchalign)247 fdl_set_pitchalign(struct fdl_layout *layout, unsigned pitchalign)
248 {
249 uint32_t nblocksx = util_format_get_nblocksx(layout->format, layout->width0);
250 layout->pitchalign = pitchalign;
251 layout->pitch0 = align(nblocksx * layout->cpp, 1 << pitchalign);
252 }
253
254 void fdl_dump_layout(struct fdl_layout *layout);
255
256 void fdl6_get_ubwc_blockwidth(const struct fdl_layout *layout,
257 uint32_t *blockwidth, uint32_t *blockheight);
258
259 enum fdl_view_type {
260 FDL_VIEW_TYPE_1D = 0,
261 FDL_VIEW_TYPE_2D = 1,
262 FDL_VIEW_TYPE_CUBE = 2,
263 FDL_VIEW_TYPE_3D = 3,
264 FDL_VIEW_TYPE_BUFFER = 4,
265 };
266
267 enum fdl_chroma_location {
268 FDL_CHROMA_LOCATION_COSITED_EVEN = 0,
269 FDL_CHROMA_LOCATION_MIDPOINT = 1,
270 };
271
272 struct fdl_view_args {
273 uint32_t chip;
274 uint64_t iova;
275 uint32_t base_miplevel;
276 uint32_t level_count;
277 uint32_t base_array_layer;
278 uint32_t layer_count;
279 float min_lod_clamp;
280 unsigned char swiz[4];
281 enum pipe_format format;
282 enum fdl_view_type type;
283 enum fdl_chroma_location chroma_offsets[2];
284 };
285
286 #define FDL6_TEX_CONST_DWORDS 16
287
288 struct fdl6_view {
289 uint64_t base_addr;
290 uint64_t ubwc_addr;
291 uint32_t layer_size;
292 uint32_t ubwc_layer_size;
293
294 uint32_t offset;
295
296 uint32_t width, height;
297 bool need_y2_align;
298
299 bool ubwc_enabled;
300
301 enum pipe_format format;
302
303 uint32_t descriptor[FDL6_TEX_CONST_DWORDS];
304
305 /* Descriptor for use as a storage image as opposed to a sampled image.
306 * This has a few differences for cube maps (e.g. type).
307 */
308 uint32_t storage_descriptor[FDL6_TEX_CONST_DWORDS];
309
310 uint32_t pitch;
311
312 /* pre-filled register values */
313 uint32_t FLAG_BUFFER_PITCH;
314
315 uint32_t RB_MRT_BUF_INFO;
316 uint32_t SP_FS_MRT_REG;
317
318 uint32_t SP_PS_2D_SRC_INFO;
319 uint32_t SP_PS_2D_SRC_SIZE;
320
321 uint32_t RB_2D_DST_INFO;
322
323 uint32_t RB_BLIT_DST_INFO;
324
325 uint32_t GRAS_LRZ_DEPTH_VIEW;
326 };
327
328 void
329 fdl6_view_init(struct fdl6_view *view, const struct fdl_layout **layouts,
330 const struct fdl_view_args *args, bool has_z24uint_s8uint);
331 void
332 fdl6_buffer_view_init(uint32_t *descriptor, enum pipe_format format,
333 const uint8_t *swiz, uint64_t iova, uint32_t size);
334
335 void
336 fdl6_format_swiz(enum pipe_format format, bool has_z24uint_s8uint,
337 unsigned char *format_swiz);
338
339 enum fdl_macrotile_mode {
340 FDL_MACROTILE_4_CHANNEL,
341 FDL_MACROTILE_8_CHANNEL,
342 /* Used internally by turnip */
343 FDL_MACROTILE_INVALID = ~0,
344 };
345
346 /* Parameters that affect UBWC swizzling. Note that because we don't handle
347 * compression, this isn't a complete set of knobs. See the documentation in
348 * fd6_tiled_memcpy.c for a description of each one.
349 */
350 struct fdl_ubwc_config {
351 unsigned highest_bank_bit;
352 unsigned bank_swizzle_levels;
353 enum fdl_macrotile_mode macrotile_mode;
354 };
355
356 void
357 fdl6_memcpy_linear_to_tiled(uint32_t x_start, uint32_t y_start,
358 uint32_t width, uint32_t height,
359 char *dst, const char *src,
360 const struct fdl_layout *dst_layout,
361 unsigned dst_miplevel,
362 uint32_t src_pitch,
363 const struct fdl_ubwc_config *config);
364
365 void
366 fdl6_memcpy_tiled_to_linear(uint32_t x_start, uint32_t y_start,
367 uint32_t width, uint32_t height,
368 char *dst, const char *src,
369 const struct fdl_layout *src_layout,
370 unsigned src_miplevel,
371 uint32_t dst_pitch,
372 const struct fdl_ubwc_config *config);
373
374 ENDC;
375
376 #endif /* FREEDRENO_LAYOUT_H_ */
377