1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <gpio.h>
4 #include <intelblocks/pcr.h>
5 #include <soc/pcr_ids.h>
6 #include <soc/pmc.h>
7
8 static const struct reset_mapping rst_map[] = {
9 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
10 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
11 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
12 };
13
14 static const struct reset_mapping rst_map_gpd[] = {
15 { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
16 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
17 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
18 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
19 };
20
21 /*
22 * The GPIO driver for Cannonlake on Windows/Linux expects 32 GPIOs per pad
23 * group, regardless of whether or not there is a physical pad for each
24 * exposed GPIO number.
25 *
26 * This results in the OS having a sparse GPIO map, and devices that need
27 * to export an ACPI GPIO must use the OS expected number.
28 *
29 * Not all pins are usable as GPIO and those groups do not have a pad base.
30 *
31 * This layout matches the Linux kernel pinctrl map for CNL-H at:
32 * linux/drivers/pinctrl/intel/pinctrl-cannonlake.c
33 */
34 static const struct pad_group cnl_community0_groups[] = {
35 INTEL_GPP_BASE(GPP_A0, GPP_A0, ESPI_CLK_LOOPBK, 0), /* GPP_A */
36 INTEL_GPP_BASE(GPP_A0, GPP_B0, GSPI1_CLK_LOOPBK, 32), /* GPP_B */
37 };
38
39 static const struct pad_group cnl_community1_groups[] = {
40 INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 64), /* GPP_C */
41 INTEL_GPP_BASE(GPP_C0, GPP_D0, GPP_D23, 96), /* GPP_D */
42 INTEL_GPP_BASE(GPP_C0, GPP_G0, GPP_G7, 128), /* GPP_G */
43 INTEL_GPP(GPP_C0, HDA_BCLK, I2S1_TXD), /* AZA */
44 INTEL_GPP_BASE(GPP_C0, CNV_BTEN, vISH_UART1_RTS_B, 160),/* VGPIO_0 */
45 INTEL_GPP(GPP_C0, vCNV_BT_I2S_BCLK, vSSP2_RXD), /* VGPIO_1 */
46 };
47
48 /* This community is not visible to the OS */
49 static const struct pad_group cnl_community2_groups[] = {
50 INTEL_GPP(GPD0, GPD0, DRAM_RESET_B), /* GPD */
51 };
52
53 static const struct pad_group cnl_community3_groups[] = {
54 INTEL_GPP_BASE(GPP_K0, GPP_K0, GPP_K23, 192), /* GPP_K */
55 INTEL_GPP_BASE(GPP_K0, GPP_H0, GPP_H23, 224), /* GPP_H */
56 INTEL_GPP_BASE(GPP_K0, GPP_E0, GPP_E12, 256), /* GPP_E */
57 INTEL_GPP_BASE(GPP_K0, GPP_F0, GPP_F23, 288), /* GPP_F */
58 INTEL_GPP(GPP_K0, SPI0_IO_2, SPI0_CLK_LOOPBK), /* SPI */
59 };
60
61 static const struct pad_group cnl_community4_groups[] = {
62 INTEL_GPP(HDACPU_SDI, HDACPU_SDI, TRIGGER_OUT), /* CPU */
63 INTEL_GPP(HDACPU_SDI, PCH_TDO, ITP_PMODE), /* JTAG */
64 INTEL_GPP_BASE(HDACPU_SDI, GPP_I0, GPP_I14, 320), /* GPP_I */
65 INTEL_GPP_BASE(HDACPU_SDI, GPP_J0, GPP_J11, 352), /* GPP_J */
66 };
67
68 static const struct pad_community cnl_communities[] = {
69 /* GPP A, B */
70 [COMM_0] = {
71 .port = PID_GPIOCOM0,
72 .first_pad = GPP_A0,
73 .last_pad = GSPI1_CLK_LOOPBK,
74 .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
75 .pad_cfg_base = PAD_CFG_BASE,
76 .host_own_reg_0 = HOSTSW_OWN_REG_0,
77 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
78 .gpi_int_en_reg_0 = GPI_INT_EN_0,
79 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
80 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
81 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
82 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
83 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
84 .name = "GPP_AB",
85 .acpi_path = "\\_SB.PCI0.GPIO",
86 .reset_map = rst_map,
87 .num_reset_vals = ARRAY_SIZE(rst_map),
88 .groups = cnl_community0_groups,
89 .num_groups = ARRAY_SIZE(cnl_community0_groups),
90 },
91 /* GPP C, D, G */
92 [COMM_1] = {
93 .port = PID_GPIOCOM1,
94 .first_pad = GPP_C0,
95 .last_pad = vSSP2_RXD,
96 .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
97 .pad_cfg_base = PAD_CFG_BASE,
98 .host_own_reg_0 = HOSTSW_OWN_REG_0,
99 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
100 .gpi_int_en_reg_0 = GPI_INT_EN_0,
101 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
102 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
103 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
104 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
105 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
106 .name = "GPP_CDG",
107 .acpi_path = "\\_SB.PCI0.GPIO",
108 .reset_map = rst_map,
109 .num_reset_vals = ARRAY_SIZE(rst_map),
110 .groups = cnl_community1_groups,
111 .num_groups = ARRAY_SIZE(cnl_community1_groups),
112 },
113 /* GPD */
114 [COMM_2] = {
115 .port = PID_GPIOCOM2,
116 .first_pad = GPD0,
117 .last_pad = DRAM_RESET_B,
118 .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
119 .pad_cfg_base = PAD_CFG_BASE,
120 .host_own_reg_0 = HOSTSW_OWN_REG_0,
121 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
122 .gpi_int_en_reg_0 = GPI_INT_EN_0,
123 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
124 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
125 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
126 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
127 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
128 .name = "GPD",
129 .acpi_path = "\\_SB.PCI0.GPIO",
130 .reset_map = rst_map_gpd,
131 .num_reset_vals = ARRAY_SIZE(rst_map_gpd),
132 .groups = cnl_community2_groups,
133 .num_groups = ARRAY_SIZE(cnl_community2_groups),
134 },
135 /* GPP K, H, E, F */
136 [COMM_3] = {
137 .port = PID_GPIOCOM3,
138 .first_pad = GPP_K0,
139 .last_pad = SPI0_CLK_LOOPBK,
140 .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
141 .pad_cfg_base = PAD_CFG_BASE,
142 .host_own_reg_0 = HOSTSW_OWN_REG_0,
143 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
144 .gpi_int_en_reg_0 = GPI_INT_EN_0,
145 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
146 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
147 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
148 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
149 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
150 .name = "GPP_KHEF",
151 .acpi_path = "\\_SB.PCI0.GPIO",
152 .reset_map = rst_map,
153 .num_reset_vals = ARRAY_SIZE(rst_map),
154 .groups = cnl_community3_groups,
155 .num_groups = ARRAY_SIZE(cnl_community3_groups),
156 },
157 /* GPP I, J */
158 [COMM_4] = {
159 .port = PID_GPIOCOM4,
160 .first_pad = HDACPU_SDI,
161 .last_pad = GPP_J11,
162 .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
163 .pad_cfg_base = PAD_CFG_BASE,
164 .host_own_reg_0 = HOSTSW_OWN_REG_0,
165 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
166 .gpi_int_en_reg_0 = GPI_INT_EN_0,
167 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
168 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
169 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
170 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
171 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
172 .name = "GPP_IJ",
173 .acpi_path = "\\_SB.PCI0.GPIO",
174 .reset_map = rst_map,
175 .num_reset_vals = ARRAY_SIZE(rst_map),
176 .groups = cnl_community4_groups,
177 .num_groups = ARRAY_SIZE(cnl_community4_groups),
178 }
179 };
180
soc_gpio_get_community(size_t * num_communities)181 const struct pad_community *soc_gpio_get_community(size_t *num_communities)
182 {
183 *num_communities = ARRAY_SIZE(cnl_communities);
184 return cnl_communities;
185 }
186
soc_pmc_gpio_routes(size_t * num)187 const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
188 {
189 static const struct pmc_to_gpio_route routes[] = {
190 { PMC_GPP_A, GPP_A },
191 { PMC_GPP_B, GPP_B },
192 { PMC_GPP_C, GPP_C },
193 { PMC_GPP_D, GPP_D },
194 { PMC_GPP_E, GPP_E },
195 { PMC_GPP_F, GPP_F },
196 { PMC_GPP_G, GPP_G },
197 { PMC_GPP_H, GPP_H },
198 { PMC_GPP_I, GPP_I },
199 { PMC_GPP_J, GPP_J },
200 { PMC_GPP_K, GPP_K },
201 { PMC_GPD, GPD },
202 };
203 *num = ARRAY_SIZE(routes);
204 return routes;
205 }
206