1commit 8845b72377a42443b249360b9cd3d6f1e8cfb097 2Author: Alexander Graf <agraf@suse.de> 3Date: Thu Dec 17 16:04:44 2009 +0100 4 5 Enable non page boundary BAR device assignment 6 7 While trying to get device passthrough working with an emulex hba, kvm 8 refused to pass it through because it has a BAR of 256 bytes: 9 10 Region 0: Memory at d2100000 (64-bit, non-prefetchable) [size=4K] 11 Region 2: Memory at d2101000 (64-bit, non-prefetchable) [size=256] 12 Region 4: I/O ports at b100 [size=256] 13 14 Since the page boundary is an arbitrary optimization to allow 1:1 mapping of 15 physical to virtual addresses, we can still take the old MMIO callback route. 16 17 So let's add a second code path that allows for size & 0xFFF != 0 sized regions 18 by looping it through userspace. 19 20 I verified that it works by passing through an e1000 with this additional patch 21 applied and the card acted the same way it did without this patch: 22 23 map_func = assigned_dev_iomem_map; 24 - if (cur_region->size & 0xFFF) { 25 + if (i != PCI_ROM_SLOT){ 26 fprintf(stderr, "PCI region %d at address 0x%llx " 27 28 Signed-off-by: Alexander Graf <agraf@suse.de> 29 Signed-off-by: Avi Kivity <avi@redhat.com> 30 31diff --git a/hw/device-assignment.c b/hw/device-assignment.c 32index 5422e9a..c99d986 100644 33--- a/hw/device-assignment.c 34+++ b/hw/device-assignment.c 35@@ -158,6 +158,105 @@ static uint32_t assigned_dev_ioport_readl(void *opaque, uint32_t addr) 36 return assigned_dev_ioport_rw(opaque, addr, 4, NULL); 37 } 38 39+static uint32_t slow_bar_readb(void *opaque, target_phys_addr_t addr) 40+{ 41+ AssignedDevRegion *d = opaque; 42+ uint8_t *in = d->u.r_virtbase + addr; 43+ uint32_t r; 44+ 45+ r = *in; 46+ DEBUG("slow_bar_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, r); 47+ 48+ return r; 49+} 50+ 51+static uint32_t slow_bar_readw(void *opaque, target_phys_addr_t addr) 52+{ 53+ AssignedDevRegion *d = opaque; 54+ uint16_t *in = d->u.r_virtbase + addr; 55+ uint32_t r; 56+ 57+ r = *in; 58+ DEBUG("slow_bar_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, r); 59+ 60+ return r; 61+} 62+ 63+static uint32_t slow_bar_readl(void *opaque, target_phys_addr_t addr) 64+{ 65+ AssignedDevRegion *d = opaque; 66+ uint32_t *in = d->u.r_virtbase + addr; 67+ uint32_t r; 68+ 69+ r = *in; 70+ DEBUG("slow_bar_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, r); 71+ 72+ return r; 73+} 74+ 75+static void slow_bar_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) 76+{ 77+ AssignedDevRegion *d = opaque; 78+ uint8_t *out = d->u.r_virtbase + addr; 79+ 80+ DEBUG("slow_bar_writeb addr=0x" TARGET_FMT_plx " val=0x%02x\n", addr, val); 81+ *out = val; 82+} 83+ 84+static void slow_bar_writew(void *opaque, target_phys_addr_t addr, uint32_t val) 85+{ 86+ AssignedDevRegion *d = opaque; 87+ uint16_t *out = d->u.r_virtbase + addr; 88+ 89+ DEBUG("slow_bar_writew addr=0x" TARGET_FMT_plx " val=0x%04x\n", addr, val); 90+ *out = val; 91+} 92+ 93+static void slow_bar_writel(void *opaque, target_phys_addr_t addr, uint32_t val) 94+{ 95+ AssignedDevRegion *d = opaque; 96+ uint32_t *out = d->u.r_virtbase + addr; 97+ 98+ DEBUG("slow_bar_writel addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, val); 99+ *out = val; 100+} 101+ 102+static CPUWriteMemoryFunc * const slow_bar_write[] = { 103+ &slow_bar_writeb, 104+ &slow_bar_writew, 105+ &slow_bar_writel 106+}; 107+ 108+static CPUReadMemoryFunc * const slow_bar_read[] = { 109+ &slow_bar_readb, 110+ &slow_bar_readw, 111+ &slow_bar_readl 112+}; 113+ 114+static void assigned_dev_iomem_map_slow(PCIDevice *pci_dev, int region_num, 115+ pcibus_t e_phys, pcibus_t e_size, 116+ int type) 117+{ 118+ AssignedDevice *r_dev = container_of(pci_dev, AssignedDevice, dev); 119+ AssignedDevRegion *region = &r_dev->v_addrs[region_num]; 120+ PCIRegion *real_region = &r_dev->real_device.regions[region_num]; 121+ int m; 122+ 123+ DEBUG("slow map type %i\n", type); 124+ m = cpu_register_io_memory(slow_bar_read, slow_bar_write, region); 125+ cpu_register_physical_memory(e_phys, e_size, m); 126+ 127+ /* MSI-X MMIO page */ 128+ if ((e_size > 0) && 129+ real_region->base_addr <= r_dev->msix_table_addr && 130+ real_region->base_addr + real_region->size >= r_dev->msix_table_addr) { 131+ int offset = r_dev->msix_table_addr - real_region->base_addr; 132+ 133+ cpu_register_physical_memory(e_phys + offset, 134+ TARGET_PAGE_SIZE, r_dev->mmio_index); 135+ } 136+} 137+ 138 static void assigned_dev_iomem_map(PCIDevice *pci_dev, int region_num, 139 pcibus_t e_phys, pcibus_t e_size, int type) 140 { 141@@ -456,15 +555,22 @@ static int assigned_dev_register_regions(PCIRegion *io_regions, 142 143 /* handle memory io regions */ 144 if (cur_region->type & IORESOURCE_MEM) { 145+ int slow_map = 0; 146 int t = cur_region->type & IORESOURCE_PREFETCH 147 ? PCI_BASE_ADDRESS_MEM_PREFETCH 148 : PCI_BASE_ADDRESS_SPACE_MEMORY; 149+ 150 if (cur_region->size & 0xFFF) { 151- fprintf(stderr, "Unable to assign device: PCI region %d " 152- "at address 0x%llx has size 0x%x, " 153- " which is not a multiple of 4K\n", 154+ fprintf(stderr, "PCI region %d at address 0x%llx " 155+ "has size 0x%x, which is not a multiple of 4K. " 156+ "You might experience some performance hit due to that.\n", 157 i, (unsigned long long)cur_region->base_addr, 158 cur_region->size); 159+ slow_map = 1; 160+ } 161+ 162+ if (slow_map && (i == PCI_ROM_SLOT)) { 163+ fprintf(stderr, "ROM not aligned - can't continue\n"); 164 return -1; 165 } 166 167@@ -480,7 +586,7 @@ static int assigned_dev_register_regions(PCIRegion *io_regions, 168 } else { 169 pci_dev->v_addrs[i].u.r_virtbase = 170 mmap(NULL, 171- (cur_region->size + 0xFFF) & 0xFFFFF000, 172+ cur_region->size, 173 PROT_WRITE | PROT_READ, MAP_SHARED, 174 cur_region->resource_fd, (off_t) 0); 175 } 176@@ -507,7 +613,8 @@ static int assigned_dev_register_regions(PCIRegion *io_regions, 177 178 pci_register_bar((PCIDevice *) pci_dev, i, 179 cur_region->size, t, 180- assigned_dev_iomem_map); 181+ slow_map ? assigned_dev_iomem_map_slow 182+ : assigned_dev_iomem_map); 183 continue; 184 } else { 185 /* handle port io regions */ 186