1 #ifndef __BDK_CSRS_OCX_H__
2 #define __BDK_CSRS_OCX_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***************
6 * Copyright (c) 2003-2017 Cavium Inc. (support@cavium.com). All rights
7 * reserved.
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26
27 * This Software, including technical data, may be subject to U.S. export control
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31
32 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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42 ***********************license end**************************************/
43
44
45 /**
46 * @file
47 *
48 * Configuration and status register (CSR) address and type definitions for
49 * Cavium OCX.
50 *
51 * This file is auto generated. Do not edit.
52 *
53 */
54
55 /**
56 * Enumeration ocx_bar_e
57 *
58 * OCX Base Address Register Enumeration
59 * Enumerates the base address registers.
60 */
61 #define BDK_OCX_BAR_E_OCX_PF_BAR0 (0x87e011000000ll)
62 #define BDK_OCX_BAR_E_OCX_PF_BAR0_SIZE 0x800000ull
63 #define BDK_OCX_BAR_E_OCX_PF_BAR4 (0x87e011f00000ll)
64 #define BDK_OCX_BAR_E_OCX_PF_BAR4_SIZE 0x100000ull
65
66 /**
67 * Enumeration ocx_int_vec_e
68 *
69 * OCX MSI-X Vector Enumeration
70 * Enumerates the MSI-X interrupt vectors.
71 */
72 #define BDK_OCX_INT_VEC_E_COM_INTS (3)
73 #define BDK_OCX_INT_VEC_E_LNK_INTSX(a) (0 + (a))
74
75 /**
76 * Register (RSL) ocx_com_bist_status
77 *
78 * OCX COM Memory BIST Status Register
79 * Contains status from last memory BIST for all RX FIFO memories. BIST status for TX FIFO
80 * memories and REPLAY memories are organized by link and are located in
81 * OCX_TLK()_BIST_STATUS.
82 */
83 union bdk_ocx_com_bist_status
84 {
85 uint64_t u;
86 struct bdk_ocx_com_bist_status_s
87 {
88 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
89 uint64_t reserved_36_63 : 28;
90 uint64_t status : 36; /**< [ 35: 0](RO/H) BIST status.
91 Internal:
92 \<35:34\> = Link 2 VC12 RX FIFOs.
93 \<33:32\> = Link 2 VC4/VC2 RX FIFOs.
94 \<31:30\> = Link 2 VC10/VC8/VC6 RX FIFOs. (Reserved in pass 2)
95 \<29:28\> = Link 1 VC12 RX FIFOs.
96 \<27:26\> = Link 1 VC4/VC2 RX FIFOs.
97 \<25:24\> = Link 1 VC10/VC8/VC6 RX FIFOs. (Reserved in pass 2)
98 \<23:22\> = Link 0 VC12 RX FIFOs.
99 \<21:20\> = Link 0 VC4/VC2 RX FIFOs.
100 \<19:18\> = Link 0 VC10/VC8/VC6 RX FIFOs. (Reserved in pass 2)
101 \<17:16\> = Link 2 VC1/VC0 RX FIFOs.
102 \<15:14\> = Link 2 VC5/VC3 RX FIFOs.
103 \<13:12\> = Link 2 VC11/VC9/VC7 RX FIFOs. (Reserved in pass 2)
104 \<11:10\> = Link 1 VC1/VC0 RX FIFOs.
105 \<9:8\> = Link 1 VC5/VC3 RX FIFOs.
106 \<7:6\> = Link 1 VC11/VC9/VC7 RX FIFOs. (Reserved in pass 2)
107 \<5:4\> = Link 0 VC1/VC0 RX FIFOs.
108 \<3:2\> = Link 0 VC5/VC3 RX FIFOs.
109 \<1:0\> = Link 0 VC11/VC9/VC7 RX FIFOs. (Reserved in pass 2) */
110 #else /* Word 0 - Little Endian */
111 uint64_t status : 36; /**< [ 35: 0](RO/H) BIST status.
112 Internal:
113 \<35:34\> = Link 2 VC12 RX FIFOs.
114 \<33:32\> = Link 2 VC4/VC2 RX FIFOs.
115 \<31:30\> = Link 2 VC10/VC8/VC6 RX FIFOs. (Reserved in pass 2)
116 \<29:28\> = Link 1 VC12 RX FIFOs.
117 \<27:26\> = Link 1 VC4/VC2 RX FIFOs.
118 \<25:24\> = Link 1 VC10/VC8/VC6 RX FIFOs. (Reserved in pass 2)
119 \<23:22\> = Link 0 VC12 RX FIFOs.
120 \<21:20\> = Link 0 VC4/VC2 RX FIFOs.
121 \<19:18\> = Link 0 VC10/VC8/VC6 RX FIFOs. (Reserved in pass 2)
122 \<17:16\> = Link 2 VC1/VC0 RX FIFOs.
123 \<15:14\> = Link 2 VC5/VC3 RX FIFOs.
124 \<13:12\> = Link 2 VC11/VC9/VC7 RX FIFOs. (Reserved in pass 2)
125 \<11:10\> = Link 1 VC1/VC0 RX FIFOs.
126 \<9:8\> = Link 1 VC5/VC3 RX FIFOs.
127 \<7:6\> = Link 1 VC11/VC9/VC7 RX FIFOs. (Reserved in pass 2)
128 \<5:4\> = Link 0 VC1/VC0 RX FIFOs.
129 \<3:2\> = Link 0 VC5/VC3 RX FIFOs.
130 \<1:0\> = Link 0 VC11/VC9/VC7 RX FIFOs. (Reserved in pass 2) */
131 uint64_t reserved_36_63 : 28;
132 #endif /* Word 0 - End */
133 } s;
134 /* struct bdk_ocx_com_bist_status_s cn; */
135 };
136 typedef union bdk_ocx_com_bist_status bdk_ocx_com_bist_status_t;
137
138 #define BDK_OCX_COM_BIST_STATUS BDK_OCX_COM_BIST_STATUS_FUNC()
139 static inline uint64_t BDK_OCX_COM_BIST_STATUS_FUNC(void) __attribute__ ((pure, always_inline));
BDK_OCX_COM_BIST_STATUS_FUNC(void)140 static inline uint64_t BDK_OCX_COM_BIST_STATUS_FUNC(void)
141 {
142 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX))
143 return 0x87e0110000f0ll;
144 __bdk_csr_fatal("OCX_COM_BIST_STATUS", 0, 0, 0, 0, 0);
145 }
146
147 #define typedef_BDK_OCX_COM_BIST_STATUS bdk_ocx_com_bist_status_t
148 #define bustype_BDK_OCX_COM_BIST_STATUS BDK_CSR_TYPE_RSL
149 #define basename_BDK_OCX_COM_BIST_STATUS "OCX_COM_BIST_STATUS"
150 #define device_bar_BDK_OCX_COM_BIST_STATUS 0x0 /* PF_BAR0 */
151 #define busnum_BDK_OCX_COM_BIST_STATUS 0
152 #define arguments_BDK_OCX_COM_BIST_STATUS -1,-1,-1,-1
153
154 /**
155 * Register (RSL) ocx_com_dual_sort
156 *
157 * OCX COM Dual Sort Register
158 */
159 union bdk_ocx_com_dual_sort
160 {
161 uint64_t u;
162 struct bdk_ocx_com_dual_sort_s
163 {
164 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
165 uint64_t reserved_2_63 : 62;
166 uint64_t sort : 2; /**< [ 1: 0](R/W) Sorting procedure for multiple links to same node:
167 0x0 = All to lowest link number.
168 0x1 = Split by top/bottom L2C buses. (top to lowest link number).
169 0x2 = IOC 1st, IOR 2nd, Mem VCs to either based on most room in TX FIFOs.
170 0x3 = Illegal. */
171 #else /* Word 0 - Little Endian */
172 uint64_t sort : 2; /**< [ 1: 0](R/W) Sorting procedure for multiple links to same node:
173 0x0 = All to lowest link number.
174 0x1 = Split by top/bottom L2C buses. (top to lowest link number).
175 0x2 = IOC 1st, IOR 2nd, Mem VCs to either based on most room in TX FIFOs.
176 0x3 = Illegal. */
177 uint64_t reserved_2_63 : 62;
178 #endif /* Word 0 - End */
179 } s;
180 /* struct bdk_ocx_com_dual_sort_s cn; */
181 };
182 typedef union bdk_ocx_com_dual_sort bdk_ocx_com_dual_sort_t;
183
184 #define BDK_OCX_COM_DUAL_SORT BDK_OCX_COM_DUAL_SORT_FUNC()
185 static inline uint64_t BDK_OCX_COM_DUAL_SORT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_OCX_COM_DUAL_SORT_FUNC(void)186 static inline uint64_t BDK_OCX_COM_DUAL_SORT_FUNC(void)
187 {
188 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX))
189 return 0x87e011000008ll;
190 __bdk_csr_fatal("OCX_COM_DUAL_SORT", 0, 0, 0, 0, 0);
191 }
192
193 #define typedef_BDK_OCX_COM_DUAL_SORT bdk_ocx_com_dual_sort_t
194 #define bustype_BDK_OCX_COM_DUAL_SORT BDK_CSR_TYPE_RSL
195 #define basename_BDK_OCX_COM_DUAL_SORT "OCX_COM_DUAL_SORT"
196 #define device_bar_BDK_OCX_COM_DUAL_SORT 0x0 /* PF_BAR0 */
197 #define busnum_BDK_OCX_COM_DUAL_SORT 0
198 #define arguments_BDK_OCX_COM_DUAL_SORT -1,-1,-1,-1
199
200 /**
201 * Register (RSL) ocx_com_int
202 *
203 * OCX COM Interrupt Register
204 */
205 union bdk_ocx_com_int
206 {
207 uint64_t u;
208 struct bdk_ocx_com_int_s
209 {
210 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
211 uint64_t reserved_55_63 : 9;
212 uint64_t io_badid : 1; /**< [ 54: 54](R/W1C/H) I/O request or response cannot be sent because a link was not found with a packet node ID
213 matching the OCX_COM_LINK(0..2)_CTL[ID] with OCX_COM_LINK(0..2)_CTL[VALID] bit set.
214 Transaction has been dropped. Should not occur during normal operation. This may indicate
215 a software/configuration failure and may be considered fatal. */
216 uint64_t mem_badid : 1; /**< [ 53: 53](R/W1C/H) Memory request or response cannot be sent because a link was not found with a packet node
217 ID matching the OCX_COM_LINK(0..2)_CTL[ID] with OCX_COM_LINK(0..2)_CTL[VALID] bit set.
218 Transaction has been dropped. Should not occur during normal operation. This may indicate
219 a software/configuration failure and may be considered fatal. */
220 uint64_t copr_badid : 1; /**< [ 52: 52](R/W1C/H) Scheduler add work or buffer pool return cannot be sent because a link was not found with
221 a node ID matching the OCX_COM_LINK(0..2)_CTL[ID] with OCX_COM_LINK(0..2)_CTL[VALID] bit
222 set.
223 Transaction has been dropped. Should not occur during normal operation. This may indicate
224 a software/configuration failure and may be considered fatal. */
225 uint64_t win_req_badid : 1; /**< [ 51: 51](R/W1C/H) Window request specified in SLI_WIN_RD_ADDR, SLI_WIN_WR_ADDR, OCX_WIN_CMD or OCX_PP_CMD
226 cannot be sent because a link was not found with a request node ID matching the
227 OCX_COM_LINK(0..2)_CTL[ID] with OCX_COM_LINK(0..2)_CTL[VALID] bit set. Transaction has
228 been
229 dropped. Should not occur during normal operation. This may indicate a
230 software/configuration failure and may be considered fatal. */
231 uint64_t win_req_tout : 1; /**< [ 50: 50](R/W1C/H) Window or core request was dropped because it could not be send during the period
232 specified by OCX_WIN_TIMER. Should not occur during normal operation. This may indicate a
233 software/configuration failure and may be considered fatal. */
234 uint64_t win_req_xmit : 1; /**< [ 49: 49](R/W1C/H) Window request specified in SLI_WIN_RD_ADDR, SLI_WIN_WR_ADDR, OCX_WIN_CMD or OCX_PP_CMD
235 has been scheduled for transmission. If the command was not expecting a response, then a
236 new command may be issued. */
237 uint64_t win_rsp : 1; /**< [ 48: 48](R/W1C/H) A response to a previous window request or core request has been received. A new command
238 may be issued. */
239 uint64_t reserved_24_47 : 24;
240 uint64_t rx_lane : 24; /**< [ 23: 0](R/W1C/H) SerDes RX lane interrupt. See OCX_LNE(0..23)_INT for more information. */
241 #else /* Word 0 - Little Endian */
242 uint64_t rx_lane : 24; /**< [ 23: 0](R/W1C/H) SerDes RX lane interrupt. See OCX_LNE(0..23)_INT for more information. */
243 uint64_t reserved_24_47 : 24;
244 uint64_t win_rsp : 1; /**< [ 48: 48](R/W1C/H) A response to a previous window request or core request has been received. A new command
245 may be issued. */
246 uint64_t win_req_xmit : 1; /**< [ 49: 49](R/W1C/H) Window request specified in SLI_WIN_RD_ADDR, SLI_WIN_WR_ADDR, OCX_WIN_CMD or OCX_PP_CMD
247 has been scheduled for transmission. If the command was not expecting a response, then a
248 new command may be issued. */
249 uint64_t win_req_tout : 1; /**< [ 50: 50](R/W1C/H) Window or core request was dropped because it could not be send during the period
250 specified by OCX_WIN_TIMER. Should not occur during normal operation. This may indicate a
251 software/configuration failure and may be considered fatal. */
252 uint64_t win_req_badid : 1; /**< [ 51: 51](R/W1C/H) Window request specified in SLI_WIN_RD_ADDR, SLI_WIN_WR_ADDR, OCX_WIN_CMD or OCX_PP_CMD
253 cannot be sent because a link was not found with a request node ID matching the
254 OCX_COM_LINK(0..2)_CTL[ID] with OCX_COM_LINK(0..2)_CTL[VALID] bit set. Transaction has
255 been
256 dropped. Should not occur during normal operation. This may indicate a
257 software/configuration failure and may be considered fatal. */
258 uint64_t copr_badid : 1; /**< [ 52: 52](R/W1C/H) Scheduler add work or buffer pool return cannot be sent because a link was not found with
259 a node ID matching the OCX_COM_LINK(0..2)_CTL[ID] with OCX_COM_LINK(0..2)_CTL[VALID] bit
260 set.
261 Transaction has been dropped. Should not occur during normal operation. This may indicate
262 a software/configuration failure and may be considered fatal. */
263 uint64_t mem_badid : 1; /**< [ 53: 53](R/W1C/H) Memory request or response cannot be sent because a link was not found with a packet node
264 ID matching the OCX_COM_LINK(0..2)_CTL[ID] with OCX_COM_LINK(0..2)_CTL[VALID] bit set.
265 Transaction has been dropped. Should not occur during normal operation. This may indicate
266 a software/configuration failure and may be considered fatal. */
267 uint64_t io_badid : 1; /**< [ 54: 54](R/W1C/H) I/O request or response cannot be sent because a link was not found with a packet node ID
268 matching the OCX_COM_LINK(0..2)_CTL[ID] with OCX_COM_LINK(0..2)_CTL[VALID] bit set.
269 Transaction has been dropped. Should not occur during normal operation. This may indicate
270 a software/configuration failure and may be considered fatal. */
271 uint64_t reserved_55_63 : 9;
272 #endif /* Word 0 - End */
273 } s;
274 /* struct bdk_ocx_com_int_s cn; */
275 };
276 typedef union bdk_ocx_com_int bdk_ocx_com_int_t;
277
278 #define BDK_OCX_COM_INT BDK_OCX_COM_INT_FUNC()
279 static inline uint64_t BDK_OCX_COM_INT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_OCX_COM_INT_FUNC(void)280 static inline uint64_t BDK_OCX_COM_INT_FUNC(void)
281 {
282 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX))
283 return 0x87e011000100ll;
284 __bdk_csr_fatal("OCX_COM_INT", 0, 0, 0, 0, 0);
285 }
286
287 #define typedef_BDK_OCX_COM_INT bdk_ocx_com_int_t
288 #define bustype_BDK_OCX_COM_INT BDK_CSR_TYPE_RSL
289 #define basename_BDK_OCX_COM_INT "OCX_COM_INT"
290 #define device_bar_BDK_OCX_COM_INT 0x0 /* PF_BAR0 */
291 #define busnum_BDK_OCX_COM_INT 0
292 #define arguments_BDK_OCX_COM_INT -1,-1,-1,-1
293
294 /**
295 * Register (RSL) ocx_com_int_ena_w1c
296 *
297 * OCX COM Interrupt Enable Clear Register
298 * This register clears interrupt enable bits.
299 */
300 union bdk_ocx_com_int_ena_w1c
301 {
302 uint64_t u;
303 struct bdk_ocx_com_int_ena_w1c_s
304 {
305 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
306 uint64_t reserved_55_63 : 9;
307 uint64_t io_badid : 1; /**< [ 54: 54](R/W1C/H) Reads or clears enable for OCX_COM_INT[IO_BADID]. */
308 uint64_t mem_badid : 1; /**< [ 53: 53](R/W1C/H) Reads or clears enable for OCX_COM_INT[MEM_BADID]. */
309 uint64_t copr_badid : 1; /**< [ 52: 52](R/W1C/H) Reads or clears enable for OCX_COM_INT[COPR_BADID]. */
310 uint64_t win_req_badid : 1; /**< [ 51: 51](R/W1C/H) Reads or clears enable for OCX_COM_INT[WIN_REQ_BADID]. */
311 uint64_t win_req_tout : 1; /**< [ 50: 50](R/W1C/H) Reads or clears enable for OCX_COM_INT[WIN_REQ_TOUT]. */
312 uint64_t win_req_xmit : 1; /**< [ 49: 49](R/W1C/H) Reads or clears enable for OCX_COM_INT[WIN_REQ_XMIT]. */
313 uint64_t win_rsp : 1; /**< [ 48: 48](R/W1C/H) Reads or clears enable for OCX_COM_INT[WIN_RSP]. */
314 uint64_t reserved_24_47 : 24;
315 uint64_t rx_lane : 24; /**< [ 23: 0](R/W1C/H) Reads or clears enable for OCX_COM_INT[RX_LANE]. */
316 #else /* Word 0 - Little Endian */
317 uint64_t rx_lane : 24; /**< [ 23: 0](R/W1C/H) Reads or clears enable for OCX_COM_INT[RX_LANE]. */
318 uint64_t reserved_24_47 : 24;
319 uint64_t win_rsp : 1; /**< [ 48: 48](R/W1C/H) Reads or clears enable for OCX_COM_INT[WIN_RSP]. */
320 uint64_t win_req_xmit : 1; /**< [ 49: 49](R/W1C/H) Reads or clears enable for OCX_COM_INT[WIN_REQ_XMIT]. */
321 uint64_t win_req_tout : 1; /**< [ 50: 50](R/W1C/H) Reads or clears enable for OCX_COM_INT[WIN_REQ_TOUT]. */
322 uint64_t win_req_badid : 1; /**< [ 51: 51](R/W1C/H) Reads or clears enable for OCX_COM_INT[WIN_REQ_BADID]. */
323 uint64_t copr_badid : 1; /**< [ 52: 52](R/W1C/H) Reads or clears enable for OCX_COM_INT[COPR_BADID]. */
324 uint64_t mem_badid : 1; /**< [ 53: 53](R/W1C/H) Reads or clears enable for OCX_COM_INT[MEM_BADID]. */
325 uint64_t io_badid : 1; /**< [ 54: 54](R/W1C/H) Reads or clears enable for OCX_COM_INT[IO_BADID]. */
326 uint64_t reserved_55_63 : 9;
327 #endif /* Word 0 - End */
328 } s;
329 /* struct bdk_ocx_com_int_ena_w1c_s cn; */
330 };
331 typedef union bdk_ocx_com_int_ena_w1c bdk_ocx_com_int_ena_w1c_t;
332
333 #define BDK_OCX_COM_INT_ENA_W1C BDK_OCX_COM_INT_ENA_W1C_FUNC()
334 static inline uint64_t BDK_OCX_COM_INT_ENA_W1C_FUNC(void) __attribute__ ((pure, always_inline));
BDK_OCX_COM_INT_ENA_W1C_FUNC(void)335 static inline uint64_t BDK_OCX_COM_INT_ENA_W1C_FUNC(void)
336 {
337 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX))
338 return 0x87e011000118ll;
339 __bdk_csr_fatal("OCX_COM_INT_ENA_W1C", 0, 0, 0, 0, 0);
340 }
341
342 #define typedef_BDK_OCX_COM_INT_ENA_W1C bdk_ocx_com_int_ena_w1c_t
343 #define bustype_BDK_OCX_COM_INT_ENA_W1C BDK_CSR_TYPE_RSL
344 #define basename_BDK_OCX_COM_INT_ENA_W1C "OCX_COM_INT_ENA_W1C"
345 #define device_bar_BDK_OCX_COM_INT_ENA_W1C 0x0 /* PF_BAR0 */
346 #define busnum_BDK_OCX_COM_INT_ENA_W1C 0
347 #define arguments_BDK_OCX_COM_INT_ENA_W1C -1,-1,-1,-1
348
349 /**
350 * Register (RSL) ocx_com_int_ena_w1s
351 *
352 * OCX COM Interrupt Enable Set Register
353 * This register sets interrupt enable bits.
354 */
355 union bdk_ocx_com_int_ena_w1s
356 {
357 uint64_t u;
358 struct bdk_ocx_com_int_ena_w1s_s
359 {
360 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
361 uint64_t reserved_55_63 : 9;
362 uint64_t io_badid : 1; /**< [ 54: 54](R/W1S/H) Reads or sets enable for OCX_COM_INT[IO_BADID]. */
363 uint64_t mem_badid : 1; /**< [ 53: 53](R/W1S/H) Reads or sets enable for OCX_COM_INT[MEM_BADID]. */
364 uint64_t copr_badid : 1; /**< [ 52: 52](R/W1S/H) Reads or sets enable for OCX_COM_INT[COPR_BADID]. */
365 uint64_t win_req_badid : 1; /**< [ 51: 51](R/W1S/H) Reads or sets enable for OCX_COM_INT[WIN_REQ_BADID]. */
366 uint64_t win_req_tout : 1; /**< [ 50: 50](R/W1S/H) Reads or sets enable for OCX_COM_INT[WIN_REQ_TOUT]. */
367 uint64_t win_req_xmit : 1; /**< [ 49: 49](R/W1S/H) Reads or sets enable for OCX_COM_INT[WIN_REQ_XMIT]. */
368 uint64_t win_rsp : 1; /**< [ 48: 48](R/W1S/H) Reads or sets enable for OCX_COM_INT[WIN_RSP]. */
369 uint64_t reserved_24_47 : 24;
370 uint64_t rx_lane : 24; /**< [ 23: 0](R/W1S/H) Reads or sets enable for OCX_COM_INT[RX_LANE]. */
371 #else /* Word 0 - Little Endian */
372 uint64_t rx_lane : 24; /**< [ 23: 0](R/W1S/H) Reads or sets enable for OCX_COM_INT[RX_LANE]. */
373 uint64_t reserved_24_47 : 24;
374 uint64_t win_rsp : 1; /**< [ 48: 48](R/W1S/H) Reads or sets enable for OCX_COM_INT[WIN_RSP]. */
375 uint64_t win_req_xmit : 1; /**< [ 49: 49](R/W1S/H) Reads or sets enable for OCX_COM_INT[WIN_REQ_XMIT]. */
376 uint64_t win_req_tout : 1; /**< [ 50: 50](R/W1S/H) Reads or sets enable for OCX_COM_INT[WIN_REQ_TOUT]. */
377 uint64_t win_req_badid : 1; /**< [ 51: 51](R/W1S/H) Reads or sets enable for OCX_COM_INT[WIN_REQ_BADID]. */
378 uint64_t copr_badid : 1; /**< [ 52: 52](R/W1S/H) Reads or sets enable for OCX_COM_INT[COPR_BADID]. */
379 uint64_t mem_badid : 1; /**< [ 53: 53](R/W1S/H) Reads or sets enable for OCX_COM_INT[MEM_BADID]. */
380 uint64_t io_badid : 1; /**< [ 54: 54](R/W1S/H) Reads or sets enable for OCX_COM_INT[IO_BADID]. */
381 uint64_t reserved_55_63 : 9;
382 #endif /* Word 0 - End */
383 } s;
384 /* struct bdk_ocx_com_int_ena_w1s_s cn; */
385 };
386 typedef union bdk_ocx_com_int_ena_w1s bdk_ocx_com_int_ena_w1s_t;
387
388 #define BDK_OCX_COM_INT_ENA_W1S BDK_OCX_COM_INT_ENA_W1S_FUNC()
389 static inline uint64_t BDK_OCX_COM_INT_ENA_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_OCX_COM_INT_ENA_W1S_FUNC(void)390 static inline uint64_t BDK_OCX_COM_INT_ENA_W1S_FUNC(void)
391 {
392 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX))
393 return 0x87e011000110ll;
394 __bdk_csr_fatal("OCX_COM_INT_ENA_W1S", 0, 0, 0, 0, 0);
395 }
396
397 #define typedef_BDK_OCX_COM_INT_ENA_W1S bdk_ocx_com_int_ena_w1s_t
398 #define bustype_BDK_OCX_COM_INT_ENA_W1S BDK_CSR_TYPE_RSL
399 #define basename_BDK_OCX_COM_INT_ENA_W1S "OCX_COM_INT_ENA_W1S"
400 #define device_bar_BDK_OCX_COM_INT_ENA_W1S 0x0 /* PF_BAR0 */
401 #define busnum_BDK_OCX_COM_INT_ENA_W1S 0
402 #define arguments_BDK_OCX_COM_INT_ENA_W1S -1,-1,-1,-1
403
404 /**
405 * Register (RSL) ocx_com_int_w1s
406 *
407 * OCX COM Interrupt Set Register
408 * This register sets interrupt bits.
409 */
410 union bdk_ocx_com_int_w1s
411 {
412 uint64_t u;
413 struct bdk_ocx_com_int_w1s_s
414 {
415 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
416 uint64_t reserved_55_63 : 9;
417 uint64_t io_badid : 1; /**< [ 54: 54](R/W1S/H) Reads or sets OCX_COM_INT[IO_BADID]. */
418 uint64_t mem_badid : 1; /**< [ 53: 53](R/W1S/H) Reads or sets OCX_COM_INT[MEM_BADID]. */
419 uint64_t copr_badid : 1; /**< [ 52: 52](R/W1S/H) Reads or sets OCX_COM_INT[COPR_BADID]. */
420 uint64_t win_req_badid : 1; /**< [ 51: 51](R/W1S/H) Reads or sets OCX_COM_INT[WIN_REQ_BADID]. */
421 uint64_t win_req_tout : 1; /**< [ 50: 50](R/W1S/H) Reads or sets OCX_COM_INT[WIN_REQ_TOUT]. */
422 uint64_t win_req_xmit : 1; /**< [ 49: 49](R/W1S/H) Reads or sets OCX_COM_INT[WIN_REQ_XMIT]. */
423 uint64_t win_rsp : 1; /**< [ 48: 48](R/W1S/H) Reads or sets OCX_COM_INT[WIN_RSP]. */
424 uint64_t reserved_24_47 : 24;
425 uint64_t rx_lane : 24; /**< [ 23: 0](R/W1S/H) Reads or sets OCX_COM_INT[RX_LANE]. */
426 #else /* Word 0 - Little Endian */
427 uint64_t rx_lane : 24; /**< [ 23: 0](R/W1S/H) Reads or sets OCX_COM_INT[RX_LANE]. */
428 uint64_t reserved_24_47 : 24;
429 uint64_t win_rsp : 1; /**< [ 48: 48](R/W1S/H) Reads or sets OCX_COM_INT[WIN_RSP]. */
430 uint64_t win_req_xmit : 1; /**< [ 49: 49](R/W1S/H) Reads or sets OCX_COM_INT[WIN_REQ_XMIT]. */
431 uint64_t win_req_tout : 1; /**< [ 50: 50](R/W1S/H) Reads or sets OCX_COM_INT[WIN_REQ_TOUT]. */
432 uint64_t win_req_badid : 1; /**< [ 51: 51](R/W1S/H) Reads or sets OCX_COM_INT[WIN_REQ_BADID]. */
433 uint64_t copr_badid : 1; /**< [ 52: 52](R/W1S/H) Reads or sets OCX_COM_INT[COPR_BADID]. */
434 uint64_t mem_badid : 1; /**< [ 53: 53](R/W1S/H) Reads or sets OCX_COM_INT[MEM_BADID]. */
435 uint64_t io_badid : 1; /**< [ 54: 54](R/W1S/H) Reads or sets OCX_COM_INT[IO_BADID]. */
436 uint64_t reserved_55_63 : 9;
437 #endif /* Word 0 - End */
438 } s;
439 /* struct bdk_ocx_com_int_w1s_s cn; */
440 };
441 typedef union bdk_ocx_com_int_w1s bdk_ocx_com_int_w1s_t;
442
443 #define BDK_OCX_COM_INT_W1S BDK_OCX_COM_INT_W1S_FUNC()
444 static inline uint64_t BDK_OCX_COM_INT_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_OCX_COM_INT_W1S_FUNC(void)445 static inline uint64_t BDK_OCX_COM_INT_W1S_FUNC(void)
446 {
447 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX))
448 return 0x87e011000108ll;
449 __bdk_csr_fatal("OCX_COM_INT_W1S", 0, 0, 0, 0, 0);
450 }
451
452 #define typedef_BDK_OCX_COM_INT_W1S bdk_ocx_com_int_w1s_t
453 #define bustype_BDK_OCX_COM_INT_W1S BDK_CSR_TYPE_RSL
454 #define basename_BDK_OCX_COM_INT_W1S "OCX_COM_INT_W1S"
455 #define device_bar_BDK_OCX_COM_INT_W1S 0x0 /* PF_BAR0 */
456 #define busnum_BDK_OCX_COM_INT_W1S 0
457 #define arguments_BDK_OCX_COM_INT_W1S -1,-1,-1,-1
458
459 /**
460 * Register (RSL) ocx_com_link#_ctl
461 *
462 * OCX COM Link Control Registers
463 * This register controls link operations. In addition, the combination of some of
464 * these conditions are used to generate the link_down status used by the L2C_OCI_CTL[SHTOEN] and
465 * as a reset condition controlled by RST_OCX[RST_LINK]. This link_down status is true when one
466 * of the following occurs:
467 *
468 * * Link is not initialized (see description of [UP]).
469 * * Retry counter expired (see OCX_COM_LINK_TIMER and OCX_COM_LINK()_INT[STOP].
470 * * Receive REINIT request from Link Partner (See description of [REINIT]).
471 * * Detected uncorrectable ECC error while reading the transmit FIFOs (see
472 * OCX_COM_LINK(0..2)_INT[TXFIFO_DBE]).
473 * * Detected uncorrectable ECC error while reading the replay buffer (see
474 * OCX_COM_LINK(0..2)_INT[REPLAY_DBE]).
475 */
476 union bdk_ocx_com_linkx_ctl
477 {
478 uint64_t u;
479 struct bdk_ocx_com_linkx_ctl_s
480 {
481 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
482 uint64_t reserved_10_63 : 54;
483 uint64_t cclk_dis : 1; /**< [ 9: 9](R/W) Reserved.
484 Internal:
485 Disable conditional clocking. Set to force link clocks on
486 unconditionally. */
487 uint64_t loopback : 1; /**< [ 8: 8](R/W) Reserved.
488 Internal:
489 Diagnostic data loopback. Set to force outgoing link to inbound port.
490 All data and link credits are returned and appear to come from link partner. Typically
491 SerDes should be disabled during this operation. */
492 uint64_t reinit : 1; /**< [ 7: 7](R/W) Reinitialize link. Setting this bit forces link back into init state and sets [DROP].
493 Setting the bit also causes the link to transmit a REINIT request to the link partner.
494 This bit must be cleared for link to operate normally. */
495 uint64_t reserved_6 : 1;
496 uint64_t auto_clr : 1; /**< [ 5: 5](R/W) When set, automatically clears the local DROP bit if link partner forces
497 a reinitialization. Typically disabled once software is running.
498 If clear, software must manage clearing [DROP] after it has verified
499 that any pending transactions have timed out. */
500 uint64_t drop : 1; /**< [ 4: 4](R/W/H) Drop all requests on given link. Typically set by hardware when link has failed or been
501 reinitialized. Cleared by software once pending link traffic is removed. (See
502 OCX_TLK(0..2)_FIFO(0..13)_CNT.) */
503 uint64_t up : 1; /**< [ 3: 3](RO/H) Link is operating normally and exchanging control information. */
504 uint64_t valid : 1; /**< [ 2: 2](RO/H) Link has valid lanes and is exchanging information. This bit will never be set if
505 OCX_LNK(0..2)_CFG[QLM_SELECT] is zero. */
506 uint64_t id : 2; /**< [ 1: 0](R/W) This ID is used to sort traffic by link. If more than one link has the same value, the
507 OCX_COM_DUAL_SORT[SORT] field and traffic VC are used to choose a link. This field is only
508 reset during a cold reset to an arbitrary value to avoid conflicts with the
509 OCX_COM_NODE[ID] field and should be configured by software before memory traffic is
510 generated. */
511 #else /* Word 0 - Little Endian */
512 uint64_t id : 2; /**< [ 1: 0](R/W) This ID is used to sort traffic by link. If more than one link has the same value, the
513 OCX_COM_DUAL_SORT[SORT] field and traffic VC are used to choose a link. This field is only
514 reset during a cold reset to an arbitrary value to avoid conflicts with the
515 OCX_COM_NODE[ID] field and should be configured by software before memory traffic is
516 generated. */
517 uint64_t valid : 1; /**< [ 2: 2](RO/H) Link has valid lanes and is exchanging information. This bit will never be set if
518 OCX_LNK(0..2)_CFG[QLM_SELECT] is zero. */
519 uint64_t up : 1; /**< [ 3: 3](RO/H) Link is operating normally and exchanging control information. */
520 uint64_t drop : 1; /**< [ 4: 4](R/W/H) Drop all requests on given link. Typically set by hardware when link has failed or been
521 reinitialized. Cleared by software once pending link traffic is removed. (See
522 OCX_TLK(0..2)_FIFO(0..13)_CNT.) */
523 uint64_t auto_clr : 1; /**< [ 5: 5](R/W) When set, automatically clears the local DROP bit if link partner forces
524 a reinitialization. Typically disabled once software is running.
525 If clear, software must manage clearing [DROP] after it has verified
526 that any pending transactions have timed out. */
527 uint64_t reserved_6 : 1;
528 uint64_t reinit : 1; /**< [ 7: 7](R/W) Reinitialize link. Setting this bit forces link back into init state and sets [DROP].
529 Setting the bit also causes the link to transmit a REINIT request to the link partner.
530 This bit must be cleared for link to operate normally. */
531 uint64_t loopback : 1; /**< [ 8: 8](R/W) Reserved.
532 Internal:
533 Diagnostic data loopback. Set to force outgoing link to inbound port.
534 All data and link credits are returned and appear to come from link partner. Typically
535 SerDes should be disabled during this operation. */
536 uint64_t cclk_dis : 1; /**< [ 9: 9](R/W) Reserved.
537 Internal:
538 Disable conditional clocking. Set to force link clocks on
539 unconditionally. */
540 uint64_t reserved_10_63 : 54;
541 #endif /* Word 0 - End */
542 } s;
543 /* struct bdk_ocx_com_linkx_ctl_s cn; */
544 };
545 typedef union bdk_ocx_com_linkx_ctl bdk_ocx_com_linkx_ctl_t;
546
547 static inline uint64_t BDK_OCX_COM_LINKX_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_COM_LINKX_CTL(unsigned long a)548 static inline uint64_t BDK_OCX_COM_LINKX_CTL(unsigned long a)
549 {
550 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
551 return 0x87e011000020ll + 8ll * ((a) & 0x3);
552 __bdk_csr_fatal("OCX_COM_LINKX_CTL", 1, a, 0, 0, 0);
553 }
554
555 #define typedef_BDK_OCX_COM_LINKX_CTL(a) bdk_ocx_com_linkx_ctl_t
556 #define bustype_BDK_OCX_COM_LINKX_CTL(a) BDK_CSR_TYPE_RSL
557 #define basename_BDK_OCX_COM_LINKX_CTL(a) "OCX_COM_LINKX_CTL"
558 #define device_bar_BDK_OCX_COM_LINKX_CTL(a) 0x0 /* PF_BAR0 */
559 #define busnum_BDK_OCX_COM_LINKX_CTL(a) (a)
560 #define arguments_BDK_OCX_COM_LINKX_CTL(a) (a),-1,-1,-1
561
562 /**
563 * Register (RSL) ocx_com_link#_int
564 *
565 * OCX COM Link Interrupt Register
566 */
567 union bdk_ocx_com_linkx_int
568 {
569 uint64_t u;
570 struct bdk_ocx_com_linkx_int_s
571 {
572 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
573 uint64_t reserved_14_63 : 50;
574 uint64_t bad_word : 1; /**< [ 13: 13](R/W1C/H) Illegal word decoded on at least one lane of link. These receive errors may occur during
575 normal operation, and may likely occur during link bringup. Hardware normally will
576 automatically correct the error. Software may choose to count the number of these errors. */
577 uint64_t align_fail : 1; /**< [ 12: 12](R/W1C/H) Link lanes failed to align. These receive errors may occur during normal operation, and
578 may likely occur during link bringup. Hardware normally will automatically correct the
579 error. Software may choose to count the number of these errors. */
580 uint64_t align_done : 1; /**< [ 11: 11](R/W1C/H) Link lane alignment is complete. These may occur during normal operation, and will occur
581 during link bringup. Software should disable reception of these interrupts during normal
582 operation. */
583 uint64_t up : 1; /**< [ 10: 10](R/W1C/H) Link initialization is complete and is ready to pass traffic. Note: This state occurs
584 some time after the link starts exchanging information as indicated in
585 OCX_COM_LINK(0..2)_CTL[UP]. These should not occur during normal operation. */
586 uint64_t stop : 1; /**< [ 9: 9](R/W1C/H) Link has stopped operating. Link retry count has reached threshold specified in
587 OCX_COM_LINK_TIMER; outgoing traffic has been dropped and an initialization request has
588 been reissued. These should not occur during normal operation. This may be considered
589 fatal. */
590 uint64_t blk_err : 1; /**< [ 8: 8](R/W1C/H) Link block error count has reached threshold specified in OCX_RLK(0..2)_BLK_ERR[LIMIT].
591 These receive errors may occur during normal operation. Hardware normally will
592 automatically correct the error. Software may choose to count the number of these errors. */
593 uint64_t reinit : 1; /**< [ 7: 7](R/W1C/H) Link has received a initialization request from link partner after link has been
594 established. These should not occur during normal operation */
595 uint64_t lnk_data : 1; /**< [ 6: 6](R/W1C/H) Set by hardware when a link data block is received in OCX_RLK(0..2)_LNK_DATA. It
596 software's responsibility to clear the bit after reading the data. */
597 uint64_t rxfifo_dbe : 1; /**< [ 5: 5](R/W1C/H) Double-bit error detected in FIFO RAMs. This error may be considered fatal. */
598 uint64_t rxfifo_sbe : 1; /**< [ 4: 4](R/W1C/H) Single-bit error detected/corrected in FIFO RAMs. Hardware automatically corrected the
599 error. Software may choose to count the number of these single-bit errors. */
600 uint64_t txfifo_dbe : 1; /**< [ 3: 3](R/W1C/H) Double-bit error detected in TX FIFO RAMs. This error may be considered fatal. */
601 uint64_t txfifo_sbe : 1; /**< [ 2: 2](R/W1C/H) Single-bit error detected/corrected in TX FIFO RAMs. Hardware automatically corrected the
602 error. Software may choose to count the number of these single-bit errors. */
603 uint64_t replay_dbe : 1; /**< [ 1: 1](R/W1C/H) Double-bit error detected in REPLAY BUFFER RAMs. This error may be considered fatal. */
604 uint64_t replay_sbe : 1; /**< [ 0: 0](R/W1C/H) Single-bit error detected/corrected in REPLAY BUFFER RAMs. Hardware automatically
605 corrected the error. Software may choose to count the number of these single-bit errors. */
606 #else /* Word 0 - Little Endian */
607 uint64_t replay_sbe : 1; /**< [ 0: 0](R/W1C/H) Single-bit error detected/corrected in REPLAY BUFFER RAMs. Hardware automatically
608 corrected the error. Software may choose to count the number of these single-bit errors. */
609 uint64_t replay_dbe : 1; /**< [ 1: 1](R/W1C/H) Double-bit error detected in REPLAY BUFFER RAMs. This error may be considered fatal. */
610 uint64_t txfifo_sbe : 1; /**< [ 2: 2](R/W1C/H) Single-bit error detected/corrected in TX FIFO RAMs. Hardware automatically corrected the
611 error. Software may choose to count the number of these single-bit errors. */
612 uint64_t txfifo_dbe : 1; /**< [ 3: 3](R/W1C/H) Double-bit error detected in TX FIFO RAMs. This error may be considered fatal. */
613 uint64_t rxfifo_sbe : 1; /**< [ 4: 4](R/W1C/H) Single-bit error detected/corrected in FIFO RAMs. Hardware automatically corrected the
614 error. Software may choose to count the number of these single-bit errors. */
615 uint64_t rxfifo_dbe : 1; /**< [ 5: 5](R/W1C/H) Double-bit error detected in FIFO RAMs. This error may be considered fatal. */
616 uint64_t lnk_data : 1; /**< [ 6: 6](R/W1C/H) Set by hardware when a link data block is received in OCX_RLK(0..2)_LNK_DATA. It
617 software's responsibility to clear the bit after reading the data. */
618 uint64_t reinit : 1; /**< [ 7: 7](R/W1C/H) Link has received a initialization request from link partner after link has been
619 established. These should not occur during normal operation */
620 uint64_t blk_err : 1; /**< [ 8: 8](R/W1C/H) Link block error count has reached threshold specified in OCX_RLK(0..2)_BLK_ERR[LIMIT].
621 These receive errors may occur during normal operation. Hardware normally will
622 automatically correct the error. Software may choose to count the number of these errors. */
623 uint64_t stop : 1; /**< [ 9: 9](R/W1C/H) Link has stopped operating. Link retry count has reached threshold specified in
624 OCX_COM_LINK_TIMER; outgoing traffic has been dropped and an initialization request has
625 been reissued. These should not occur during normal operation. This may be considered
626 fatal. */
627 uint64_t up : 1; /**< [ 10: 10](R/W1C/H) Link initialization is complete and is ready to pass traffic. Note: This state occurs
628 some time after the link starts exchanging information as indicated in
629 OCX_COM_LINK(0..2)_CTL[UP]. These should not occur during normal operation. */
630 uint64_t align_done : 1; /**< [ 11: 11](R/W1C/H) Link lane alignment is complete. These may occur during normal operation, and will occur
631 during link bringup. Software should disable reception of these interrupts during normal
632 operation. */
633 uint64_t align_fail : 1; /**< [ 12: 12](R/W1C/H) Link lanes failed to align. These receive errors may occur during normal operation, and
634 may likely occur during link bringup. Hardware normally will automatically correct the
635 error. Software may choose to count the number of these errors. */
636 uint64_t bad_word : 1; /**< [ 13: 13](R/W1C/H) Illegal word decoded on at least one lane of link. These receive errors may occur during
637 normal operation, and may likely occur during link bringup. Hardware normally will
638 automatically correct the error. Software may choose to count the number of these errors. */
639 uint64_t reserved_14_63 : 50;
640 #endif /* Word 0 - End */
641 } s;
642 /* struct bdk_ocx_com_linkx_int_s cn; */
643 };
644 typedef union bdk_ocx_com_linkx_int bdk_ocx_com_linkx_int_t;
645
646 static inline uint64_t BDK_OCX_COM_LINKX_INT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_COM_LINKX_INT(unsigned long a)647 static inline uint64_t BDK_OCX_COM_LINKX_INT(unsigned long a)
648 {
649 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
650 return 0x87e011000120ll + 8ll * ((a) & 0x3);
651 __bdk_csr_fatal("OCX_COM_LINKX_INT", 1, a, 0, 0, 0);
652 }
653
654 #define typedef_BDK_OCX_COM_LINKX_INT(a) bdk_ocx_com_linkx_int_t
655 #define bustype_BDK_OCX_COM_LINKX_INT(a) BDK_CSR_TYPE_RSL
656 #define basename_BDK_OCX_COM_LINKX_INT(a) "OCX_COM_LINKX_INT"
657 #define device_bar_BDK_OCX_COM_LINKX_INT(a) 0x0 /* PF_BAR0 */
658 #define busnum_BDK_OCX_COM_LINKX_INT(a) (a)
659 #define arguments_BDK_OCX_COM_LINKX_INT(a) (a),-1,-1,-1
660
661 /**
662 * Register (RSL) ocx_com_link#_int_ena_w1c
663 *
664 * OCX COM Link Interrupt Enable Clear Register
665 * This register clears interrupt enable bits.
666 */
667 union bdk_ocx_com_linkx_int_ena_w1c
668 {
669 uint64_t u;
670 struct bdk_ocx_com_linkx_int_ena_w1c_s
671 {
672 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
673 uint64_t reserved_14_63 : 50;
674 uint64_t bad_word : 1; /**< [ 13: 13](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[BAD_WORD]. */
675 uint64_t align_fail : 1; /**< [ 12: 12](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[ALIGN_FAIL]. */
676 uint64_t align_done : 1; /**< [ 11: 11](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[ALIGN_DONE]. */
677 uint64_t up : 1; /**< [ 10: 10](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[UP]. */
678 uint64_t stop : 1; /**< [ 9: 9](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[STOP]. */
679 uint64_t blk_err : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[BLK_ERR]. */
680 uint64_t reinit : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[REINIT]. */
681 uint64_t lnk_data : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[LNK_DATA]. */
682 uint64_t rxfifo_dbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[RXFIFO_DBE]. */
683 uint64_t rxfifo_sbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[RXFIFO_SBE]. */
684 uint64_t txfifo_dbe : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[TXFIFO_DBE]. */
685 uint64_t txfifo_sbe : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[TXFIFO_SBE]. */
686 uint64_t replay_dbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[REPLAY_DBE]. */
687 uint64_t replay_sbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[REPLAY_SBE]. */
688 #else /* Word 0 - Little Endian */
689 uint64_t replay_sbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[REPLAY_SBE]. */
690 uint64_t replay_dbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[REPLAY_DBE]. */
691 uint64_t txfifo_sbe : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[TXFIFO_SBE]. */
692 uint64_t txfifo_dbe : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[TXFIFO_DBE]. */
693 uint64_t rxfifo_sbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[RXFIFO_SBE]. */
694 uint64_t rxfifo_dbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[RXFIFO_DBE]. */
695 uint64_t lnk_data : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[LNK_DATA]. */
696 uint64_t reinit : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[REINIT]. */
697 uint64_t blk_err : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[BLK_ERR]. */
698 uint64_t stop : 1; /**< [ 9: 9](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[STOP]. */
699 uint64_t up : 1; /**< [ 10: 10](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[UP]. */
700 uint64_t align_done : 1; /**< [ 11: 11](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[ALIGN_DONE]. */
701 uint64_t align_fail : 1; /**< [ 12: 12](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[ALIGN_FAIL]. */
702 uint64_t bad_word : 1; /**< [ 13: 13](R/W1C/H) Reads or clears enable for OCX_COM_LINK(0..2)_INT[BAD_WORD]. */
703 uint64_t reserved_14_63 : 50;
704 #endif /* Word 0 - End */
705 } s;
706 /* struct bdk_ocx_com_linkx_int_ena_w1c_s cn; */
707 };
708 typedef union bdk_ocx_com_linkx_int_ena_w1c bdk_ocx_com_linkx_int_ena_w1c_t;
709
710 static inline uint64_t BDK_OCX_COM_LINKX_INT_ENA_W1C(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_COM_LINKX_INT_ENA_W1C(unsigned long a)711 static inline uint64_t BDK_OCX_COM_LINKX_INT_ENA_W1C(unsigned long a)
712 {
713 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
714 return 0x87e011000180ll + 8ll * ((a) & 0x3);
715 __bdk_csr_fatal("OCX_COM_LINKX_INT_ENA_W1C", 1, a, 0, 0, 0);
716 }
717
718 #define typedef_BDK_OCX_COM_LINKX_INT_ENA_W1C(a) bdk_ocx_com_linkx_int_ena_w1c_t
719 #define bustype_BDK_OCX_COM_LINKX_INT_ENA_W1C(a) BDK_CSR_TYPE_RSL
720 #define basename_BDK_OCX_COM_LINKX_INT_ENA_W1C(a) "OCX_COM_LINKX_INT_ENA_W1C"
721 #define device_bar_BDK_OCX_COM_LINKX_INT_ENA_W1C(a) 0x0 /* PF_BAR0 */
722 #define busnum_BDK_OCX_COM_LINKX_INT_ENA_W1C(a) (a)
723 #define arguments_BDK_OCX_COM_LINKX_INT_ENA_W1C(a) (a),-1,-1,-1
724
725 /**
726 * Register (RSL) ocx_com_link#_int_ena_w1s
727 *
728 * OCX COM Link Interrupt Enable Set Register
729 * This register sets interrupt enable bits.
730 */
731 union bdk_ocx_com_linkx_int_ena_w1s
732 {
733 uint64_t u;
734 struct bdk_ocx_com_linkx_int_ena_w1s_s
735 {
736 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
737 uint64_t reserved_14_63 : 50;
738 uint64_t bad_word : 1; /**< [ 13: 13](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[BAD_WORD]. */
739 uint64_t align_fail : 1; /**< [ 12: 12](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[ALIGN_FAIL]. */
740 uint64_t align_done : 1; /**< [ 11: 11](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[ALIGN_DONE]. */
741 uint64_t up : 1; /**< [ 10: 10](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[UP]. */
742 uint64_t stop : 1; /**< [ 9: 9](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[STOP]. */
743 uint64_t blk_err : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[BLK_ERR]. */
744 uint64_t reinit : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[REINIT]. */
745 uint64_t lnk_data : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[LNK_DATA]. */
746 uint64_t rxfifo_dbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[RXFIFO_DBE]. */
747 uint64_t rxfifo_sbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[RXFIFO_SBE]. */
748 uint64_t txfifo_dbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[TXFIFO_DBE]. */
749 uint64_t txfifo_sbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[TXFIFO_SBE]. */
750 uint64_t replay_dbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[REPLAY_DBE]. */
751 uint64_t replay_sbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[REPLAY_SBE]. */
752 #else /* Word 0 - Little Endian */
753 uint64_t replay_sbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[REPLAY_SBE]. */
754 uint64_t replay_dbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[REPLAY_DBE]. */
755 uint64_t txfifo_sbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[TXFIFO_SBE]. */
756 uint64_t txfifo_dbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[TXFIFO_DBE]. */
757 uint64_t rxfifo_sbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[RXFIFO_SBE]. */
758 uint64_t rxfifo_dbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[RXFIFO_DBE]. */
759 uint64_t lnk_data : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[LNK_DATA]. */
760 uint64_t reinit : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[REINIT]. */
761 uint64_t blk_err : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[BLK_ERR]. */
762 uint64_t stop : 1; /**< [ 9: 9](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[STOP]. */
763 uint64_t up : 1; /**< [ 10: 10](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[UP]. */
764 uint64_t align_done : 1; /**< [ 11: 11](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[ALIGN_DONE]. */
765 uint64_t align_fail : 1; /**< [ 12: 12](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[ALIGN_FAIL]. */
766 uint64_t bad_word : 1; /**< [ 13: 13](R/W1S/H) Reads or sets enable for OCX_COM_LINK(0..2)_INT[BAD_WORD]. */
767 uint64_t reserved_14_63 : 50;
768 #endif /* Word 0 - End */
769 } s;
770 /* struct bdk_ocx_com_linkx_int_ena_w1s_s cn; */
771 };
772 typedef union bdk_ocx_com_linkx_int_ena_w1s bdk_ocx_com_linkx_int_ena_w1s_t;
773
774 static inline uint64_t BDK_OCX_COM_LINKX_INT_ENA_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_COM_LINKX_INT_ENA_W1S(unsigned long a)775 static inline uint64_t BDK_OCX_COM_LINKX_INT_ENA_W1S(unsigned long a)
776 {
777 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
778 return 0x87e011000160ll + 8ll * ((a) & 0x3);
779 __bdk_csr_fatal("OCX_COM_LINKX_INT_ENA_W1S", 1, a, 0, 0, 0);
780 }
781
782 #define typedef_BDK_OCX_COM_LINKX_INT_ENA_W1S(a) bdk_ocx_com_linkx_int_ena_w1s_t
783 #define bustype_BDK_OCX_COM_LINKX_INT_ENA_W1S(a) BDK_CSR_TYPE_RSL
784 #define basename_BDK_OCX_COM_LINKX_INT_ENA_W1S(a) "OCX_COM_LINKX_INT_ENA_W1S"
785 #define device_bar_BDK_OCX_COM_LINKX_INT_ENA_W1S(a) 0x0 /* PF_BAR0 */
786 #define busnum_BDK_OCX_COM_LINKX_INT_ENA_W1S(a) (a)
787 #define arguments_BDK_OCX_COM_LINKX_INT_ENA_W1S(a) (a),-1,-1,-1
788
789 /**
790 * Register (RSL) ocx_com_link#_int_w1s
791 *
792 * OCX COM Link Interrupt Set Register
793 * This register sets interrupt bits.
794 */
795 union bdk_ocx_com_linkx_int_w1s
796 {
797 uint64_t u;
798 struct bdk_ocx_com_linkx_int_w1s_s
799 {
800 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
801 uint64_t reserved_14_63 : 50;
802 uint64_t bad_word : 1; /**< [ 13: 13](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[BAD_WORD]. */
803 uint64_t align_fail : 1; /**< [ 12: 12](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[ALIGN_FAIL]. */
804 uint64_t align_done : 1; /**< [ 11: 11](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[ALIGN_DONE]. */
805 uint64_t up : 1; /**< [ 10: 10](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[UP]. */
806 uint64_t stop : 1; /**< [ 9: 9](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[STOP]. */
807 uint64_t blk_err : 1; /**< [ 8: 8](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[BLK_ERR]. */
808 uint64_t reinit : 1; /**< [ 7: 7](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[REINIT]. */
809 uint64_t lnk_data : 1; /**< [ 6: 6](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[LNK_DATA]. */
810 uint64_t rxfifo_dbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[RXFIFO_DBE]. */
811 uint64_t rxfifo_sbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[RXFIFO_SBE]. */
812 uint64_t txfifo_dbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[TXFIFO_DBE]. */
813 uint64_t txfifo_sbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[TXFIFO_SBE]. */
814 uint64_t replay_dbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[REPLAY_DBE]. */
815 uint64_t replay_sbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[REPLAY_SBE]. */
816 #else /* Word 0 - Little Endian */
817 uint64_t replay_sbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[REPLAY_SBE]. */
818 uint64_t replay_dbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[REPLAY_DBE]. */
819 uint64_t txfifo_sbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[TXFIFO_SBE]. */
820 uint64_t txfifo_dbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[TXFIFO_DBE]. */
821 uint64_t rxfifo_sbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[RXFIFO_SBE]. */
822 uint64_t rxfifo_dbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[RXFIFO_DBE]. */
823 uint64_t lnk_data : 1; /**< [ 6: 6](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[LNK_DATA]. */
824 uint64_t reinit : 1; /**< [ 7: 7](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[REINIT]. */
825 uint64_t blk_err : 1; /**< [ 8: 8](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[BLK_ERR]. */
826 uint64_t stop : 1; /**< [ 9: 9](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[STOP]. */
827 uint64_t up : 1; /**< [ 10: 10](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[UP]. */
828 uint64_t align_done : 1; /**< [ 11: 11](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[ALIGN_DONE]. */
829 uint64_t align_fail : 1; /**< [ 12: 12](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[ALIGN_FAIL]. */
830 uint64_t bad_word : 1; /**< [ 13: 13](R/W1S/H) Reads or sets OCX_COM_LINK(0..2)_INT[BAD_WORD]. */
831 uint64_t reserved_14_63 : 50;
832 #endif /* Word 0 - End */
833 } s;
834 /* struct bdk_ocx_com_linkx_int_w1s_s cn; */
835 };
836 typedef union bdk_ocx_com_linkx_int_w1s bdk_ocx_com_linkx_int_w1s_t;
837
838 static inline uint64_t BDK_OCX_COM_LINKX_INT_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_COM_LINKX_INT_W1S(unsigned long a)839 static inline uint64_t BDK_OCX_COM_LINKX_INT_W1S(unsigned long a)
840 {
841 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
842 return 0x87e011000140ll + 8ll * ((a) & 0x3);
843 __bdk_csr_fatal("OCX_COM_LINKX_INT_W1S", 1, a, 0, 0, 0);
844 }
845
846 #define typedef_BDK_OCX_COM_LINKX_INT_W1S(a) bdk_ocx_com_linkx_int_w1s_t
847 #define bustype_BDK_OCX_COM_LINKX_INT_W1S(a) BDK_CSR_TYPE_RSL
848 #define basename_BDK_OCX_COM_LINKX_INT_W1S(a) "OCX_COM_LINKX_INT_W1S"
849 #define device_bar_BDK_OCX_COM_LINKX_INT_W1S(a) 0x0 /* PF_BAR0 */
850 #define busnum_BDK_OCX_COM_LINKX_INT_W1S(a) (a)
851 #define arguments_BDK_OCX_COM_LINKX_INT_W1S(a) (a),-1,-1,-1
852
853 /**
854 * Register (RSL) ocx_com_link_timer
855 *
856 * OCX COM Link Timer Register
857 */
858 union bdk_ocx_com_link_timer
859 {
860 uint64_t u;
861 struct bdk_ocx_com_link_timer_s
862 {
863 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
864 uint64_t reserved_24_63 : 40;
865 uint64_t tout : 24; /**< [ 23: 0](R/W) Indicates the number of unacknowledged retry requests issued before link stops
866 operation and OCX_COM_LINK()_INT[STOP] is asserted. */
867 #else /* Word 0 - Little Endian */
868 uint64_t tout : 24; /**< [ 23: 0](R/W) Indicates the number of unacknowledged retry requests issued before link stops
869 operation and OCX_COM_LINK()_INT[STOP] is asserted. */
870 uint64_t reserved_24_63 : 40;
871 #endif /* Word 0 - End */
872 } s;
873 /* struct bdk_ocx_com_link_timer_s cn; */
874 };
875 typedef union bdk_ocx_com_link_timer bdk_ocx_com_link_timer_t;
876
877 #define BDK_OCX_COM_LINK_TIMER BDK_OCX_COM_LINK_TIMER_FUNC()
878 static inline uint64_t BDK_OCX_COM_LINK_TIMER_FUNC(void) __attribute__ ((pure, always_inline));
BDK_OCX_COM_LINK_TIMER_FUNC(void)879 static inline uint64_t BDK_OCX_COM_LINK_TIMER_FUNC(void)
880 {
881 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX))
882 return 0x87e011000010ll;
883 __bdk_csr_fatal("OCX_COM_LINK_TIMER", 0, 0, 0, 0, 0);
884 }
885
886 #define typedef_BDK_OCX_COM_LINK_TIMER bdk_ocx_com_link_timer_t
887 #define bustype_BDK_OCX_COM_LINK_TIMER BDK_CSR_TYPE_RSL
888 #define basename_BDK_OCX_COM_LINK_TIMER "OCX_COM_LINK_TIMER"
889 #define device_bar_BDK_OCX_COM_LINK_TIMER 0x0 /* PF_BAR0 */
890 #define busnum_BDK_OCX_COM_LINK_TIMER 0
891 #define arguments_BDK_OCX_COM_LINK_TIMER -1,-1,-1,-1
892
893 /**
894 * Register (RSL) ocx_com_node
895 *
896 * OCX COM Node Register
897 */
898 union bdk_ocx_com_node
899 {
900 uint64_t u;
901 struct bdk_ocx_com_node_s
902 {
903 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
904 uint64_t reserved_4_63 : 60;
905 uint64_t fixed_pin : 1; /**< [ 3: 3](RO/H) The current value of the OCI_FIXED_NODE pin. */
906 uint64_t fixed : 1; /**< [ 2: 2](R/W) ID valid associated with the chip. This register is used by the link
907 initialization software to help assign IDs and is transmitted over CCPI. The
908 [FIXED] field set during a cold reset to the value of the OCI_FIXED_NODE
909 pin. The value is also readable in the OCX_LNE()_STS_MSG[TX_META_DAT]\<2\> for
910 each lane. The [FIXED] field of the link partner can be examined by locally
911 reading the OCX_LNE()_STS_MSG[RX_META_DAT]\<2\> on each valid lane or remotely
912 reading the OCX_COM_NODE[FIXED] on the link partner. */
913 uint64_t id : 2; /**< [ 1: 0](R/W) Node ID associated with the chip. This register is used by the rest of the chip
914 to determine what traffic is transmitted over CCPI. The value should not match
915 the OCX_COM_LINK()_CTL[ID] of any active link. The ID field is set during a cold
916 reset to the value of the OCI_NODE_ID pins. The value is also readable in the
917 OCX_LNE()_STS_MSG[TX_META_DAT]\<1:0\> for each lane. The ID field of the link
918 partner can be examined by locally reading the
919 OCX_LNE()_STS_MSG[RX_META_DAT]\<1:0\> on each valid lane or remotely reading the
920 OCX_COM_NODE[ID] on the link partner. */
921 #else /* Word 0 - Little Endian */
922 uint64_t id : 2; /**< [ 1: 0](R/W) Node ID associated with the chip. This register is used by the rest of the chip
923 to determine what traffic is transmitted over CCPI. The value should not match
924 the OCX_COM_LINK()_CTL[ID] of any active link. The ID field is set during a cold
925 reset to the value of the OCI_NODE_ID pins. The value is also readable in the
926 OCX_LNE()_STS_MSG[TX_META_DAT]\<1:0\> for each lane. The ID field of the link
927 partner can be examined by locally reading the
928 OCX_LNE()_STS_MSG[RX_META_DAT]\<1:0\> on each valid lane or remotely reading the
929 OCX_COM_NODE[ID] on the link partner. */
930 uint64_t fixed : 1; /**< [ 2: 2](R/W) ID valid associated with the chip. This register is used by the link
931 initialization software to help assign IDs and is transmitted over CCPI. The
932 [FIXED] field set during a cold reset to the value of the OCI_FIXED_NODE
933 pin. The value is also readable in the OCX_LNE()_STS_MSG[TX_META_DAT]\<2\> for
934 each lane. The [FIXED] field of the link partner can be examined by locally
935 reading the OCX_LNE()_STS_MSG[RX_META_DAT]\<2\> on each valid lane or remotely
936 reading the OCX_COM_NODE[FIXED] on the link partner. */
937 uint64_t fixed_pin : 1; /**< [ 3: 3](RO/H) The current value of the OCI_FIXED_NODE pin. */
938 uint64_t reserved_4_63 : 60;
939 #endif /* Word 0 - End */
940 } s;
941 /* struct bdk_ocx_com_node_s cn; */
942 };
943 typedef union bdk_ocx_com_node bdk_ocx_com_node_t;
944
945 #define BDK_OCX_COM_NODE BDK_OCX_COM_NODE_FUNC()
946 static inline uint64_t BDK_OCX_COM_NODE_FUNC(void) __attribute__ ((pure, always_inline));
BDK_OCX_COM_NODE_FUNC(void)947 static inline uint64_t BDK_OCX_COM_NODE_FUNC(void)
948 {
949 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX))
950 return 0x87e011000000ll;
951 __bdk_csr_fatal("OCX_COM_NODE", 0, 0, 0, 0, 0);
952 }
953
954 #define typedef_BDK_OCX_COM_NODE bdk_ocx_com_node_t
955 #define bustype_BDK_OCX_COM_NODE BDK_CSR_TYPE_RSL
956 #define basename_BDK_OCX_COM_NODE "OCX_COM_NODE"
957 #define device_bar_BDK_OCX_COM_NODE 0x0 /* PF_BAR0 */
958 #define busnum_BDK_OCX_COM_NODE 0
959 #define arguments_BDK_OCX_COM_NODE -1,-1,-1,-1
960
961 /**
962 * Register (RSL) ocx_dll#_status
963 *
964 * OCX DLL Observability Registers
965 * These registers provides the parameters for DLL observability. Index 0 is the northeast DLL,
966 * index 1 the southeast DLL.
967 */
968 union bdk_ocx_dllx_status
969 {
970 uint64_t u;
971 struct bdk_ocx_dllx_status_s
972 {
973 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
974 uint64_t reserved_60_63 : 4;
975 uint64_t max_dll_setting : 12; /**< [ 59: 48](RO/H) Max reported DLL setting. */
976 uint64_t min_dll_setting : 12; /**< [ 47: 36](RO/H) Min reported DLL setting. */
977 uint64_t pd_pos_rclk_refclk : 1; /**< [ 35: 35](RO/H) Phase detector output. */
978 uint64_t pdl_rclk_refclk : 1; /**< [ 34: 34](RO/H) Phase detector output. */
979 uint64_t pdr_rclk_refclk : 1; /**< [ 33: 33](RO/H) Phase detector output. */
980 uint64_t reserved_32 : 1;
981 uint64_t dly_elem_enable : 16; /**< [ 31: 16](RO/H) Delay element enable. */
982 uint64_t dll_setting : 12; /**< [ 15: 4](RO/H) DLL setting. */
983 uint64_t reserved_1_3 : 3;
984 uint64_t dll_lock : 1; /**< [ 0: 0](RO/H) DLL lock: 1 = locked, 0 = unlocked. */
985 #else /* Word 0 - Little Endian */
986 uint64_t dll_lock : 1; /**< [ 0: 0](RO/H) DLL lock: 1 = locked, 0 = unlocked. */
987 uint64_t reserved_1_3 : 3;
988 uint64_t dll_setting : 12; /**< [ 15: 4](RO/H) DLL setting. */
989 uint64_t dly_elem_enable : 16; /**< [ 31: 16](RO/H) Delay element enable. */
990 uint64_t reserved_32 : 1;
991 uint64_t pdr_rclk_refclk : 1; /**< [ 33: 33](RO/H) Phase detector output. */
992 uint64_t pdl_rclk_refclk : 1; /**< [ 34: 34](RO/H) Phase detector output. */
993 uint64_t pd_pos_rclk_refclk : 1; /**< [ 35: 35](RO/H) Phase detector output. */
994 uint64_t min_dll_setting : 12; /**< [ 47: 36](RO/H) Min reported DLL setting. */
995 uint64_t max_dll_setting : 12; /**< [ 59: 48](RO/H) Max reported DLL setting. */
996 uint64_t reserved_60_63 : 4;
997 #endif /* Word 0 - End */
998 } s;
999 /* struct bdk_ocx_dllx_status_s cn; */
1000 };
1001 typedef union bdk_ocx_dllx_status bdk_ocx_dllx_status_t;
1002
1003 static inline uint64_t BDK_OCX_DLLX_STATUS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_DLLX_STATUS(unsigned long a)1004 static inline uint64_t BDK_OCX_DLLX_STATUS(unsigned long a)
1005 {
1006 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
1007 return 0x87e011000080ll + 8ll * ((a) & 0x1);
1008 __bdk_csr_fatal("OCX_DLLX_STATUS", 1, a, 0, 0, 0);
1009 }
1010
1011 #define typedef_BDK_OCX_DLLX_STATUS(a) bdk_ocx_dllx_status_t
1012 #define bustype_BDK_OCX_DLLX_STATUS(a) BDK_CSR_TYPE_RSL
1013 #define basename_BDK_OCX_DLLX_STATUS(a) "OCX_DLLX_STATUS"
1014 #define device_bar_BDK_OCX_DLLX_STATUS(a) 0x0 /* PF_BAR0 */
1015 #define busnum_BDK_OCX_DLLX_STATUS(a) (a)
1016 #define arguments_BDK_OCX_DLLX_STATUS(a) (a),-1,-1,-1
1017
1018 /**
1019 * Register (RSL) ocx_frc#_stat0
1020 *
1021 * OCX FRC 0-5 Statistics Registers 0
1022 */
1023 union bdk_ocx_frcx_stat0
1024 {
1025 uint64_t u;
1026 struct bdk_ocx_frcx_stat0_s
1027 {
1028 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1029 uint64_t reserved_21_63 : 43;
1030 uint64_t align_cnt : 21; /**< [ 20: 0](R/W/H) Indicates the number of alignment sequences received (i.e. those that do not violate the
1031 current alignment). */
1032 #else /* Word 0 - Little Endian */
1033 uint64_t align_cnt : 21; /**< [ 20: 0](R/W/H) Indicates the number of alignment sequences received (i.e. those that do not violate the
1034 current alignment). */
1035 uint64_t reserved_21_63 : 43;
1036 #endif /* Word 0 - End */
1037 } s;
1038 /* struct bdk_ocx_frcx_stat0_s cn; */
1039 };
1040 typedef union bdk_ocx_frcx_stat0 bdk_ocx_frcx_stat0_t;
1041
1042 static inline uint64_t BDK_OCX_FRCX_STAT0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_FRCX_STAT0(unsigned long a)1043 static inline uint64_t BDK_OCX_FRCX_STAT0(unsigned long a)
1044 {
1045 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=5))
1046 return 0x87e01100fa00ll + 8ll * ((a) & 0x7);
1047 __bdk_csr_fatal("OCX_FRCX_STAT0", 1, a, 0, 0, 0);
1048 }
1049
1050 #define typedef_BDK_OCX_FRCX_STAT0(a) bdk_ocx_frcx_stat0_t
1051 #define bustype_BDK_OCX_FRCX_STAT0(a) BDK_CSR_TYPE_RSL
1052 #define basename_BDK_OCX_FRCX_STAT0(a) "OCX_FRCX_STAT0"
1053 #define device_bar_BDK_OCX_FRCX_STAT0(a) 0x0 /* PF_BAR0 */
1054 #define busnum_BDK_OCX_FRCX_STAT0(a) (a)
1055 #define arguments_BDK_OCX_FRCX_STAT0(a) (a),-1,-1,-1
1056
1057 /**
1058 * Register (RSL) ocx_frc#_stat1
1059 *
1060 * OCX FRC 0-5 Statistics Registers 1
1061 */
1062 union bdk_ocx_frcx_stat1
1063 {
1064 uint64_t u;
1065 struct bdk_ocx_frcx_stat1_s
1066 {
1067 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1068 uint64_t reserved_21_63 : 43;
1069 uint64_t align_err_cnt : 21; /**< [ 20: 0](R/W/H) Indicates the number of alignment sequences received in error (i.e. those that violate the
1070 current alignment). */
1071 #else /* Word 0 - Little Endian */
1072 uint64_t align_err_cnt : 21; /**< [ 20: 0](R/W/H) Indicates the number of alignment sequences received in error (i.e. those that violate the
1073 current alignment). */
1074 uint64_t reserved_21_63 : 43;
1075 #endif /* Word 0 - End */
1076 } s;
1077 /* struct bdk_ocx_frcx_stat1_s cn; */
1078 };
1079 typedef union bdk_ocx_frcx_stat1 bdk_ocx_frcx_stat1_t;
1080
1081 static inline uint64_t BDK_OCX_FRCX_STAT1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_FRCX_STAT1(unsigned long a)1082 static inline uint64_t BDK_OCX_FRCX_STAT1(unsigned long a)
1083 {
1084 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=5))
1085 return 0x87e01100fa80ll + 8ll * ((a) & 0x7);
1086 __bdk_csr_fatal("OCX_FRCX_STAT1", 1, a, 0, 0, 0);
1087 }
1088
1089 #define typedef_BDK_OCX_FRCX_STAT1(a) bdk_ocx_frcx_stat1_t
1090 #define bustype_BDK_OCX_FRCX_STAT1(a) BDK_CSR_TYPE_RSL
1091 #define basename_BDK_OCX_FRCX_STAT1(a) "OCX_FRCX_STAT1"
1092 #define device_bar_BDK_OCX_FRCX_STAT1(a) 0x0 /* PF_BAR0 */
1093 #define busnum_BDK_OCX_FRCX_STAT1(a) (a)
1094 #define arguments_BDK_OCX_FRCX_STAT1(a) (a),-1,-1,-1
1095
1096 /**
1097 * Register (RSL) ocx_frc#_stat2
1098 *
1099 * OCX FRC 0-5 Statistics Registers 2
1100 */
1101 union bdk_ocx_frcx_stat2
1102 {
1103 uint64_t u;
1104 struct bdk_ocx_frcx_stat2_s
1105 {
1106 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1107 uint64_t reserved_21_63 : 43;
1108 uint64_t align_done : 21; /**< [ 20: 0](R/W/H) Indicates the number of attempts at alignment that succeeded. */
1109 #else /* Word 0 - Little Endian */
1110 uint64_t align_done : 21; /**< [ 20: 0](R/W/H) Indicates the number of attempts at alignment that succeeded. */
1111 uint64_t reserved_21_63 : 43;
1112 #endif /* Word 0 - End */
1113 } s;
1114 /* struct bdk_ocx_frcx_stat2_s cn; */
1115 };
1116 typedef union bdk_ocx_frcx_stat2 bdk_ocx_frcx_stat2_t;
1117
1118 static inline uint64_t BDK_OCX_FRCX_STAT2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_FRCX_STAT2(unsigned long a)1119 static inline uint64_t BDK_OCX_FRCX_STAT2(unsigned long a)
1120 {
1121 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=5))
1122 return 0x87e01100fb00ll + 8ll * ((a) & 0x7);
1123 __bdk_csr_fatal("OCX_FRCX_STAT2", 1, a, 0, 0, 0);
1124 }
1125
1126 #define typedef_BDK_OCX_FRCX_STAT2(a) bdk_ocx_frcx_stat2_t
1127 #define bustype_BDK_OCX_FRCX_STAT2(a) BDK_CSR_TYPE_RSL
1128 #define basename_BDK_OCX_FRCX_STAT2(a) "OCX_FRCX_STAT2"
1129 #define device_bar_BDK_OCX_FRCX_STAT2(a) 0x0 /* PF_BAR0 */
1130 #define busnum_BDK_OCX_FRCX_STAT2(a) (a)
1131 #define arguments_BDK_OCX_FRCX_STAT2(a) (a),-1,-1,-1
1132
1133 /**
1134 * Register (RSL) ocx_frc#_stat3
1135 *
1136 * OCX FRC 0-5 Statistics Registers 3
1137 */
1138 union bdk_ocx_frcx_stat3
1139 {
1140 uint64_t u;
1141 struct bdk_ocx_frcx_stat3_s
1142 {
1143 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1144 uint64_t reserved_21_63 : 43;
1145 uint64_t align_fail : 21; /**< [ 20: 0](R/W/H) Indicates the number of attempts at alignment that failed. */
1146 #else /* Word 0 - Little Endian */
1147 uint64_t align_fail : 21; /**< [ 20: 0](R/W/H) Indicates the number of attempts at alignment that failed. */
1148 uint64_t reserved_21_63 : 43;
1149 #endif /* Word 0 - End */
1150 } s;
1151 /* struct bdk_ocx_frcx_stat3_s cn; */
1152 };
1153 typedef union bdk_ocx_frcx_stat3 bdk_ocx_frcx_stat3_t;
1154
1155 static inline uint64_t BDK_OCX_FRCX_STAT3(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_FRCX_STAT3(unsigned long a)1156 static inline uint64_t BDK_OCX_FRCX_STAT3(unsigned long a)
1157 {
1158 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=5))
1159 return 0x87e01100fb80ll + 8ll * ((a) & 0x7);
1160 __bdk_csr_fatal("OCX_FRCX_STAT3", 1, a, 0, 0, 0);
1161 }
1162
1163 #define typedef_BDK_OCX_FRCX_STAT3(a) bdk_ocx_frcx_stat3_t
1164 #define bustype_BDK_OCX_FRCX_STAT3(a) BDK_CSR_TYPE_RSL
1165 #define basename_BDK_OCX_FRCX_STAT3(a) "OCX_FRCX_STAT3"
1166 #define device_bar_BDK_OCX_FRCX_STAT3(a) 0x0 /* PF_BAR0 */
1167 #define busnum_BDK_OCX_FRCX_STAT3(a) (a)
1168 #define arguments_BDK_OCX_FRCX_STAT3(a) (a),-1,-1,-1
1169
1170 /**
1171 * Register (RSL) ocx_lne#_bad_cnt
1172 *
1173 * OCX Lane Bad Count Register
1174 */
1175 union bdk_ocx_lnex_bad_cnt
1176 {
1177 uint64_t u;
1178 struct bdk_ocx_lnex_bad_cnt_s
1179 {
1180 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1181 uint64_t reserved_12_63 : 52;
1182 uint64_t tx_bad_crc32 : 1; /**< [ 11: 11](R/W/H) Send one diagnostic word with bad CRC32 to the selected lane.
1183 Injects just once. */
1184 uint64_t tx_bad_6467_cnt : 5; /**< [ 10: 6](R/W/H) Send N bad 64B/67B code words on selected lane. */
1185 uint64_t tx_bad_sync_cnt : 3; /**< [ 5: 3](R/W/H) Send N bad sync words on selected lane. */
1186 uint64_t tx_bad_scram_cnt : 3; /**< [ 2: 0](R/W/H) Send N bad scram state on selected lane. */
1187 #else /* Word 0 - Little Endian */
1188 uint64_t tx_bad_scram_cnt : 3; /**< [ 2: 0](R/W/H) Send N bad scram state on selected lane. */
1189 uint64_t tx_bad_sync_cnt : 3; /**< [ 5: 3](R/W/H) Send N bad sync words on selected lane. */
1190 uint64_t tx_bad_6467_cnt : 5; /**< [ 10: 6](R/W/H) Send N bad 64B/67B code words on selected lane. */
1191 uint64_t tx_bad_crc32 : 1; /**< [ 11: 11](R/W/H) Send one diagnostic word with bad CRC32 to the selected lane.
1192 Injects just once. */
1193 uint64_t reserved_12_63 : 52;
1194 #endif /* Word 0 - End */
1195 } s;
1196 /* struct bdk_ocx_lnex_bad_cnt_s cn; */
1197 };
1198 typedef union bdk_ocx_lnex_bad_cnt bdk_ocx_lnex_bad_cnt_t;
1199
1200 static inline uint64_t BDK_OCX_LNEX_BAD_CNT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_BAD_CNT(unsigned long a)1201 static inline uint64_t BDK_OCX_LNEX_BAD_CNT(unsigned long a)
1202 {
1203 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
1204 return 0x87e011008028ll + 0x100ll * ((a) & 0x1f);
1205 __bdk_csr_fatal("OCX_LNEX_BAD_CNT", 1, a, 0, 0, 0);
1206 }
1207
1208 #define typedef_BDK_OCX_LNEX_BAD_CNT(a) bdk_ocx_lnex_bad_cnt_t
1209 #define bustype_BDK_OCX_LNEX_BAD_CNT(a) BDK_CSR_TYPE_RSL
1210 #define basename_BDK_OCX_LNEX_BAD_CNT(a) "OCX_LNEX_BAD_CNT"
1211 #define device_bar_BDK_OCX_LNEX_BAD_CNT(a) 0x0 /* PF_BAR0 */
1212 #define busnum_BDK_OCX_LNEX_BAD_CNT(a) (a)
1213 #define arguments_BDK_OCX_LNEX_BAD_CNT(a) (a),-1,-1,-1
1214
1215 /**
1216 * Register (RSL) ocx_lne#_cfg
1217 *
1218 * OCX Lane Config Register
1219 */
1220 union bdk_ocx_lnex_cfg
1221 {
1222 uint64_t u;
1223 struct bdk_ocx_lnex_cfg_s
1224 {
1225 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1226 uint64_t reserved_9_63 : 55;
1227 uint64_t rx_bdry_lock_dis : 1; /**< [ 8: 8](R/W) Disable word boundary lock. While disabled, received data is tossed. Once enabled,
1228 received data is searched for legal two-bit patterns. */
1229 uint64_t reserved_3_7 : 5;
1230 uint64_t rx_stat_wrap_dis : 1; /**< [ 2: 2](R/W) Upon overflow, a statistics counter should saturate instead of wrapping. */
1231 uint64_t rx_stat_rdclr : 1; /**< [ 1: 1](R/W) CSR read to OCX_LNEx_STAT* clears the selected counter after returning its current value. */
1232 uint64_t rx_stat_ena : 1; /**< [ 0: 0](R/W) Enable RX lane statistics counters. */
1233 #else /* Word 0 - Little Endian */
1234 uint64_t rx_stat_ena : 1; /**< [ 0: 0](R/W) Enable RX lane statistics counters. */
1235 uint64_t rx_stat_rdclr : 1; /**< [ 1: 1](R/W) CSR read to OCX_LNEx_STAT* clears the selected counter after returning its current value. */
1236 uint64_t rx_stat_wrap_dis : 1; /**< [ 2: 2](R/W) Upon overflow, a statistics counter should saturate instead of wrapping. */
1237 uint64_t reserved_3_7 : 5;
1238 uint64_t rx_bdry_lock_dis : 1; /**< [ 8: 8](R/W) Disable word boundary lock. While disabled, received data is tossed. Once enabled,
1239 received data is searched for legal two-bit patterns. */
1240 uint64_t reserved_9_63 : 55;
1241 #endif /* Word 0 - End */
1242 } s;
1243 /* struct bdk_ocx_lnex_cfg_s cn; */
1244 };
1245 typedef union bdk_ocx_lnex_cfg bdk_ocx_lnex_cfg_t;
1246
1247 static inline uint64_t BDK_OCX_LNEX_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_CFG(unsigned long a)1248 static inline uint64_t BDK_OCX_LNEX_CFG(unsigned long a)
1249 {
1250 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
1251 return 0x87e011008000ll + 0x100ll * ((a) & 0x1f);
1252 __bdk_csr_fatal("OCX_LNEX_CFG", 1, a, 0, 0, 0);
1253 }
1254
1255 #define typedef_BDK_OCX_LNEX_CFG(a) bdk_ocx_lnex_cfg_t
1256 #define bustype_BDK_OCX_LNEX_CFG(a) BDK_CSR_TYPE_RSL
1257 #define basename_BDK_OCX_LNEX_CFG(a) "OCX_LNEX_CFG"
1258 #define device_bar_BDK_OCX_LNEX_CFG(a) 0x0 /* PF_BAR0 */
1259 #define busnum_BDK_OCX_LNEX_CFG(a) (a)
1260 #define arguments_BDK_OCX_LNEX_CFG(a) (a),-1,-1,-1
1261
1262 /**
1263 * Register (RSL) ocx_lne#_int
1264 *
1265 * OCX Lane Interrupt Register
1266 */
1267 union bdk_ocx_lnex_int
1268 {
1269 uint64_t u;
1270 struct bdk_ocx_lnex_int_s
1271 {
1272 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1273 uint64_t reserved_10_63 : 54;
1274 uint64_t disp_err : 1; /**< [ 9: 9](R/W1C/H) RX disparity error encountered. These receive errors may occur during normal
1275 operation, and may likely occur during link bring up. Hardware normally will
1276 automatically correct the error. Software may choose to count the number of
1277 these errors. */
1278 uint64_t bad_64b67b : 1; /**< [ 8: 8](R/W1C/H) Bad 64B/67B codeword encountered. Once the bad word reaches the link, as denoted by
1279 OCX_COM_LINK(0..2)_INT[BAD_WORD], a retry handshake is initiated. These receive errors may
1280 occur during normal operation, and may likely occur during link bringup. Hardware normally
1281 automatically corrects the error. Software may choose to count the number of these
1282 errors. */
1283 uint64_t stat_cnt_ovfl : 1; /**< [ 7: 7](R/W1C/H) RX lane statistic counter overflow. */
1284 uint64_t stat_msg : 1; /**< [ 6: 6](R/W1C/H) Status bits for the link or a lane transitioned from a 1 (healthy) to a 0 (problem). These
1285 should not occur during normal operation. This may be considered fatal, depending on the
1286 software protocol. */
1287 uint64_t dskew_fifo_ovfl : 1; /**< [ 5: 5](R/W1C/H) RX deskew FIFO overflow occurred. These receive errors may occur during normal operation,
1288 and may likely occur during link bring up. Hardware normally automatically corrects the
1289 error. Software may choose to count the number of these errors. */
1290 uint64_t scrm_sync_loss : 1; /**< [ 4: 4](R/W1C/H) Four consecutive bad sync words or three consecutive scramble state
1291 mismatches. These receive errors should not occur during normal operation, but
1292 may likely occur during link bring up.
1293 Hardware normally will automatically correct the error. Software may choose to count the
1294 number of these errors. */
1295 uint64_t ukwn_cntl_word : 1; /**< [ 3: 3](R/W1C/H) Unknown framing-control word. The block type does not match any of (SYNC, SCRAM, SKIP,
1296 DIAG).
1297 These receive errors may occur during normal operation. Hardware normally
1298 automatically corrects the error. Software may choose to count the number of these errors. */
1299 uint64_t crc32_err : 1; /**< [ 2: 2](R/W1C/H) Diagnostic CRC32 errors. These receive errors may occur during normal operation, typically
1300 in the presence of other errors, and may likely occur during link bring up. Hardware
1301 normally automatically corrects the error. Software may choose to count the number of
1302 these errors. */
1303 uint64_t bdry_sync_loss : 1; /**< [ 1: 1](R/W1C/H) RX logic lost word boundary sync after 16 tries. Hardware automatically attempts to regain
1304 word boundary sync. These receive errors should not occur during normal operation, but may
1305 likely occur during link bring up. Hardware normally automatically corrects the error.
1306 Software may choose to count the number of these errors. */
1307 uint64_t serdes_lock_loss : 1; /**< [ 0: 0](R/W1C/H) RX SerDes loses lock. These receive errors should not occur during normal operation. This
1308 may be considered fatal. */
1309 #else /* Word 0 - Little Endian */
1310 uint64_t serdes_lock_loss : 1; /**< [ 0: 0](R/W1C/H) RX SerDes loses lock. These receive errors should not occur during normal operation. This
1311 may be considered fatal. */
1312 uint64_t bdry_sync_loss : 1; /**< [ 1: 1](R/W1C/H) RX logic lost word boundary sync after 16 tries. Hardware automatically attempts to regain
1313 word boundary sync. These receive errors should not occur during normal operation, but may
1314 likely occur during link bring up. Hardware normally automatically corrects the error.
1315 Software may choose to count the number of these errors. */
1316 uint64_t crc32_err : 1; /**< [ 2: 2](R/W1C/H) Diagnostic CRC32 errors. These receive errors may occur during normal operation, typically
1317 in the presence of other errors, and may likely occur during link bring up. Hardware
1318 normally automatically corrects the error. Software may choose to count the number of
1319 these errors. */
1320 uint64_t ukwn_cntl_word : 1; /**< [ 3: 3](R/W1C/H) Unknown framing-control word. The block type does not match any of (SYNC, SCRAM, SKIP,
1321 DIAG).
1322 These receive errors may occur during normal operation. Hardware normally
1323 automatically corrects the error. Software may choose to count the number of these errors. */
1324 uint64_t scrm_sync_loss : 1; /**< [ 4: 4](R/W1C/H) Four consecutive bad sync words or three consecutive scramble state
1325 mismatches. These receive errors should not occur during normal operation, but
1326 may likely occur during link bring up.
1327 Hardware normally will automatically correct the error. Software may choose to count the
1328 number of these errors. */
1329 uint64_t dskew_fifo_ovfl : 1; /**< [ 5: 5](R/W1C/H) RX deskew FIFO overflow occurred. These receive errors may occur during normal operation,
1330 and may likely occur during link bring up. Hardware normally automatically corrects the
1331 error. Software may choose to count the number of these errors. */
1332 uint64_t stat_msg : 1; /**< [ 6: 6](R/W1C/H) Status bits for the link or a lane transitioned from a 1 (healthy) to a 0 (problem). These
1333 should not occur during normal operation. This may be considered fatal, depending on the
1334 software protocol. */
1335 uint64_t stat_cnt_ovfl : 1; /**< [ 7: 7](R/W1C/H) RX lane statistic counter overflow. */
1336 uint64_t bad_64b67b : 1; /**< [ 8: 8](R/W1C/H) Bad 64B/67B codeword encountered. Once the bad word reaches the link, as denoted by
1337 OCX_COM_LINK(0..2)_INT[BAD_WORD], a retry handshake is initiated. These receive errors may
1338 occur during normal operation, and may likely occur during link bringup. Hardware normally
1339 automatically corrects the error. Software may choose to count the number of these
1340 errors. */
1341 uint64_t disp_err : 1; /**< [ 9: 9](R/W1C/H) RX disparity error encountered. These receive errors may occur during normal
1342 operation, and may likely occur during link bring up. Hardware normally will
1343 automatically correct the error. Software may choose to count the number of
1344 these errors. */
1345 uint64_t reserved_10_63 : 54;
1346 #endif /* Word 0 - End */
1347 } s;
1348 /* struct bdk_ocx_lnex_int_s cn; */
1349 };
1350 typedef union bdk_ocx_lnex_int bdk_ocx_lnex_int_t;
1351
1352 static inline uint64_t BDK_OCX_LNEX_INT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_INT(unsigned long a)1353 static inline uint64_t BDK_OCX_LNEX_INT(unsigned long a)
1354 {
1355 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
1356 return 0x87e011008018ll + 0x100ll * ((a) & 0x1f);
1357 __bdk_csr_fatal("OCX_LNEX_INT", 1, a, 0, 0, 0);
1358 }
1359
1360 #define typedef_BDK_OCX_LNEX_INT(a) bdk_ocx_lnex_int_t
1361 #define bustype_BDK_OCX_LNEX_INT(a) BDK_CSR_TYPE_RSL
1362 #define basename_BDK_OCX_LNEX_INT(a) "OCX_LNEX_INT"
1363 #define device_bar_BDK_OCX_LNEX_INT(a) 0x0 /* PF_BAR0 */
1364 #define busnum_BDK_OCX_LNEX_INT(a) (a)
1365 #define arguments_BDK_OCX_LNEX_INT(a) (a),-1,-1,-1
1366
1367 /**
1368 * Register (RSL) ocx_lne#_int_en
1369 *
1370 * OCX Lane Interrupt Enable Register
1371 */
1372 union bdk_ocx_lnex_int_en
1373 {
1374 uint64_t u;
1375 struct bdk_ocx_lnex_int_en_s
1376 {
1377 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1378 uint64_t reserved_10_63 : 54;
1379 uint64_t disp_err : 1; /**< [ 9: 9](RAZ) Reserved. */
1380 uint64_t bad_64b67b : 1; /**< [ 8: 8](R/W) Enable bit for bad 64B/67B codeword encountered. */
1381 uint64_t stat_cnt_ovfl : 1; /**< [ 7: 7](R/W) Enable bit for RX lane statistic counter overflow. */
1382 uint64_t stat_msg : 1; /**< [ 6: 6](R/W) Enable bit for status bits for the link or a lane transitioned from a 1 (healthy) to a 0 (problem). */
1383 uint64_t dskew_fifo_ovfl : 1; /**< [ 5: 5](R/W) Enable bit for RX deskew FIFO overflow occurred. */
1384 uint64_t scrm_sync_loss : 1; /**< [ 4: 4](R/W) Enable bit for 4 consecutive bad sync words or 3 consecutive scramble state mismatches. */
1385 uint64_t ukwn_cntl_word : 1; /**< [ 3: 3](R/W) Enable bit for unknown framing control word. Block type does not match any of (SYNC,
1386 SCRAM, SKIP, DIAG). */
1387 uint64_t crc32_err : 1; /**< [ 2: 2](R/W) Enable bit for diagnostic CRC32 errors. */
1388 uint64_t bdry_sync_loss : 1; /**< [ 1: 1](R/W) Enable bit for RX logic lost word boundary sync after 16 tries. */
1389 uint64_t serdes_lock_loss : 1; /**< [ 0: 0](R/W) Enable bit for RX SerDes loses lock. */
1390 #else /* Word 0 - Little Endian */
1391 uint64_t serdes_lock_loss : 1; /**< [ 0: 0](R/W) Enable bit for RX SerDes loses lock. */
1392 uint64_t bdry_sync_loss : 1; /**< [ 1: 1](R/W) Enable bit for RX logic lost word boundary sync after 16 tries. */
1393 uint64_t crc32_err : 1; /**< [ 2: 2](R/W) Enable bit for diagnostic CRC32 errors. */
1394 uint64_t ukwn_cntl_word : 1; /**< [ 3: 3](R/W) Enable bit for unknown framing control word. Block type does not match any of (SYNC,
1395 SCRAM, SKIP, DIAG). */
1396 uint64_t scrm_sync_loss : 1; /**< [ 4: 4](R/W) Enable bit for 4 consecutive bad sync words or 3 consecutive scramble state mismatches. */
1397 uint64_t dskew_fifo_ovfl : 1; /**< [ 5: 5](R/W) Enable bit for RX deskew FIFO overflow occurred. */
1398 uint64_t stat_msg : 1; /**< [ 6: 6](R/W) Enable bit for status bits for the link or a lane transitioned from a 1 (healthy) to a 0 (problem). */
1399 uint64_t stat_cnt_ovfl : 1; /**< [ 7: 7](R/W) Enable bit for RX lane statistic counter overflow. */
1400 uint64_t bad_64b67b : 1; /**< [ 8: 8](R/W) Enable bit for bad 64B/67B codeword encountered. */
1401 uint64_t disp_err : 1; /**< [ 9: 9](RAZ) Reserved. */
1402 uint64_t reserved_10_63 : 54;
1403 #endif /* Word 0 - End */
1404 } s;
1405 /* struct bdk_ocx_lnex_int_en_s cn88xxp1; */
1406 struct bdk_ocx_lnex_int_en_cn88xxp2
1407 {
1408 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1409 uint64_t reserved_10_63 : 54;
1410 uint64_t disp_err : 1; /**< [ 9: 9](R/W) Enable bit for RX disparity error encountered. */
1411 uint64_t bad_64b67b : 1; /**< [ 8: 8](R/W) Enable bit for bad 64B/67B codeword encountered. */
1412 uint64_t stat_cnt_ovfl : 1; /**< [ 7: 7](R/W) Enable bit for RX lane statistic counter overflow. */
1413 uint64_t stat_msg : 1; /**< [ 6: 6](R/W) Enable bit for status bits for the link or a lane transitioned from a 1 (healthy) to a 0 (problem). */
1414 uint64_t dskew_fifo_ovfl : 1; /**< [ 5: 5](R/W) Enable bit for RX deskew FIFO overflow occurred. */
1415 uint64_t scrm_sync_loss : 1; /**< [ 4: 4](R/W) Enable bit for 4 consecutive bad sync words or 3 consecutive scramble state mismatches. */
1416 uint64_t ukwn_cntl_word : 1; /**< [ 3: 3](R/W) Enable bit for unknown framing control word. Block type does not match any of (SYNC,
1417 SCRAM, SKIP, DIAG). */
1418 uint64_t crc32_err : 1; /**< [ 2: 2](R/W) Enable bit for diagnostic CRC32 errors. */
1419 uint64_t bdry_sync_loss : 1; /**< [ 1: 1](R/W) Enable bit for RX logic lost word boundary sync after 16 tries. */
1420 uint64_t serdes_lock_loss : 1; /**< [ 0: 0](R/W) Enable bit for RX SerDes loses lock. */
1421 #else /* Word 0 - Little Endian */
1422 uint64_t serdes_lock_loss : 1; /**< [ 0: 0](R/W) Enable bit for RX SerDes loses lock. */
1423 uint64_t bdry_sync_loss : 1; /**< [ 1: 1](R/W) Enable bit for RX logic lost word boundary sync after 16 tries. */
1424 uint64_t crc32_err : 1; /**< [ 2: 2](R/W) Enable bit for diagnostic CRC32 errors. */
1425 uint64_t ukwn_cntl_word : 1; /**< [ 3: 3](R/W) Enable bit for unknown framing control word. Block type does not match any of (SYNC,
1426 SCRAM, SKIP, DIAG). */
1427 uint64_t scrm_sync_loss : 1; /**< [ 4: 4](R/W) Enable bit for 4 consecutive bad sync words or 3 consecutive scramble state mismatches. */
1428 uint64_t dskew_fifo_ovfl : 1; /**< [ 5: 5](R/W) Enable bit for RX deskew FIFO overflow occurred. */
1429 uint64_t stat_msg : 1; /**< [ 6: 6](R/W) Enable bit for status bits for the link or a lane transitioned from a 1 (healthy) to a 0 (problem). */
1430 uint64_t stat_cnt_ovfl : 1; /**< [ 7: 7](R/W) Enable bit for RX lane statistic counter overflow. */
1431 uint64_t bad_64b67b : 1; /**< [ 8: 8](R/W) Enable bit for bad 64B/67B codeword encountered. */
1432 uint64_t disp_err : 1; /**< [ 9: 9](R/W) Enable bit for RX disparity error encountered. */
1433 uint64_t reserved_10_63 : 54;
1434 #endif /* Word 0 - End */
1435 } cn88xxp2;
1436 };
1437 typedef union bdk_ocx_lnex_int_en bdk_ocx_lnex_int_en_t;
1438
1439 static inline uint64_t BDK_OCX_LNEX_INT_EN(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_INT_EN(unsigned long a)1440 static inline uint64_t BDK_OCX_LNEX_INT_EN(unsigned long a)
1441 {
1442 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
1443 return 0x87e011008020ll + 0x100ll * ((a) & 0x1f);
1444 __bdk_csr_fatal("OCX_LNEX_INT_EN", 1, a, 0, 0, 0);
1445 }
1446
1447 #define typedef_BDK_OCX_LNEX_INT_EN(a) bdk_ocx_lnex_int_en_t
1448 #define bustype_BDK_OCX_LNEX_INT_EN(a) BDK_CSR_TYPE_RSL
1449 #define basename_BDK_OCX_LNEX_INT_EN(a) "OCX_LNEX_INT_EN"
1450 #define device_bar_BDK_OCX_LNEX_INT_EN(a) 0x0 /* PF_BAR0 */
1451 #define busnum_BDK_OCX_LNEX_INT_EN(a) (a)
1452 #define arguments_BDK_OCX_LNEX_INT_EN(a) (a),-1,-1,-1
1453
1454 /**
1455 * Register (RSL) ocx_lne#_stat00
1456 *
1457 * OCX Lane Statistic 0 Register
1458 */
1459 union bdk_ocx_lnex_stat00
1460 {
1461 uint64_t u;
1462 struct bdk_ocx_lnex_stat00_s
1463 {
1464 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1465 uint64_t reserved_18_63 : 46;
1466 uint64_t ser_lock_loss_cnt : 18; /**< [ 17: 0](RO/H) Number of times the lane lost clock-data-recovery. Saturates. Interrupt on saturation if
1467 OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1468 #else /* Word 0 - Little Endian */
1469 uint64_t ser_lock_loss_cnt : 18; /**< [ 17: 0](RO/H) Number of times the lane lost clock-data-recovery. Saturates. Interrupt on saturation if
1470 OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1471 uint64_t reserved_18_63 : 46;
1472 #endif /* Word 0 - End */
1473 } s;
1474 /* struct bdk_ocx_lnex_stat00_s cn; */
1475 };
1476 typedef union bdk_ocx_lnex_stat00 bdk_ocx_lnex_stat00_t;
1477
1478 static inline uint64_t BDK_OCX_LNEX_STAT00(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_STAT00(unsigned long a)1479 static inline uint64_t BDK_OCX_LNEX_STAT00(unsigned long a)
1480 {
1481 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
1482 return 0x87e011008040ll + 0x100ll * ((a) & 0x1f);
1483 __bdk_csr_fatal("OCX_LNEX_STAT00", 1, a, 0, 0, 0);
1484 }
1485
1486 #define typedef_BDK_OCX_LNEX_STAT00(a) bdk_ocx_lnex_stat00_t
1487 #define bustype_BDK_OCX_LNEX_STAT00(a) BDK_CSR_TYPE_RSL
1488 #define basename_BDK_OCX_LNEX_STAT00(a) "OCX_LNEX_STAT00"
1489 #define device_bar_BDK_OCX_LNEX_STAT00(a) 0x0 /* PF_BAR0 */
1490 #define busnum_BDK_OCX_LNEX_STAT00(a) (a)
1491 #define arguments_BDK_OCX_LNEX_STAT00(a) (a),-1,-1,-1
1492
1493 /**
1494 * Register (RSL) ocx_lne#_stat01
1495 *
1496 * OCX Lane Statistic 1 Register
1497 */
1498 union bdk_ocx_lnex_stat01
1499 {
1500 uint64_t u;
1501 struct bdk_ocx_lnex_stat01_s
1502 {
1503 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1504 uint64_t reserved_18_63 : 46;
1505 uint64_t bdry_sync_loss_cnt : 18; /**< [ 17: 0](RO/H) Number of times a lane lost word boundary synchronization. Saturates. Interrupt on
1506 saturation if OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1507 #else /* Word 0 - Little Endian */
1508 uint64_t bdry_sync_loss_cnt : 18; /**< [ 17: 0](RO/H) Number of times a lane lost word boundary synchronization. Saturates. Interrupt on
1509 saturation if OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1510 uint64_t reserved_18_63 : 46;
1511 #endif /* Word 0 - End */
1512 } s;
1513 /* struct bdk_ocx_lnex_stat01_s cn; */
1514 };
1515 typedef union bdk_ocx_lnex_stat01 bdk_ocx_lnex_stat01_t;
1516
1517 static inline uint64_t BDK_OCX_LNEX_STAT01(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_STAT01(unsigned long a)1518 static inline uint64_t BDK_OCX_LNEX_STAT01(unsigned long a)
1519 {
1520 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
1521 return 0x87e011008048ll + 0x100ll * ((a) & 0x1f);
1522 __bdk_csr_fatal("OCX_LNEX_STAT01", 1, a, 0, 0, 0);
1523 }
1524
1525 #define typedef_BDK_OCX_LNEX_STAT01(a) bdk_ocx_lnex_stat01_t
1526 #define bustype_BDK_OCX_LNEX_STAT01(a) BDK_CSR_TYPE_RSL
1527 #define basename_BDK_OCX_LNEX_STAT01(a) "OCX_LNEX_STAT01"
1528 #define device_bar_BDK_OCX_LNEX_STAT01(a) 0x0 /* PF_BAR0 */
1529 #define busnum_BDK_OCX_LNEX_STAT01(a) (a)
1530 #define arguments_BDK_OCX_LNEX_STAT01(a) (a),-1,-1,-1
1531
1532 /**
1533 * Register (RSL) ocx_lne#_stat02
1534 *
1535 * OCX Lane Statistic 2 Register
1536 */
1537 union bdk_ocx_lnex_stat02
1538 {
1539 uint64_t u;
1540 struct bdk_ocx_lnex_stat02_s
1541 {
1542 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1543 uint64_t reserved_18_63 : 46;
1544 uint64_t syncw_bad_cnt : 18; /**< [ 17: 0](RO/H) Number of bad synchronization words. Saturates. Interrupt on saturation if
1545 OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1546 #else /* Word 0 - Little Endian */
1547 uint64_t syncw_bad_cnt : 18; /**< [ 17: 0](RO/H) Number of bad synchronization words. Saturates. Interrupt on saturation if
1548 OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1549 uint64_t reserved_18_63 : 46;
1550 #endif /* Word 0 - End */
1551 } s;
1552 /* struct bdk_ocx_lnex_stat02_s cn; */
1553 };
1554 typedef union bdk_ocx_lnex_stat02 bdk_ocx_lnex_stat02_t;
1555
1556 static inline uint64_t BDK_OCX_LNEX_STAT02(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_STAT02(unsigned long a)1557 static inline uint64_t BDK_OCX_LNEX_STAT02(unsigned long a)
1558 {
1559 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
1560 return 0x87e011008050ll + 0x100ll * ((a) & 0x1f);
1561 __bdk_csr_fatal("OCX_LNEX_STAT02", 1, a, 0, 0, 0);
1562 }
1563
1564 #define typedef_BDK_OCX_LNEX_STAT02(a) bdk_ocx_lnex_stat02_t
1565 #define bustype_BDK_OCX_LNEX_STAT02(a) BDK_CSR_TYPE_RSL
1566 #define basename_BDK_OCX_LNEX_STAT02(a) "OCX_LNEX_STAT02"
1567 #define device_bar_BDK_OCX_LNEX_STAT02(a) 0x0 /* PF_BAR0 */
1568 #define busnum_BDK_OCX_LNEX_STAT02(a) (a)
1569 #define arguments_BDK_OCX_LNEX_STAT02(a) (a),-1,-1,-1
1570
1571 /**
1572 * Register (RSL) ocx_lne#_stat03
1573 *
1574 * OCX Lane Statistic 3 Register
1575 */
1576 union bdk_ocx_lnex_stat03
1577 {
1578 uint64_t u;
1579 struct bdk_ocx_lnex_stat03_s
1580 {
1581 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1582 uint64_t reserved_18_63 : 46;
1583 uint64_t syncw_good_cnt : 18; /**< [ 17: 0](RO/H) Number of good synchronization words. Saturates. Interrupt on saturation if
1584 OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1585 #else /* Word 0 - Little Endian */
1586 uint64_t syncw_good_cnt : 18; /**< [ 17: 0](RO/H) Number of good synchronization words. Saturates. Interrupt on saturation if
1587 OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1588 uint64_t reserved_18_63 : 46;
1589 #endif /* Word 0 - End */
1590 } s;
1591 /* struct bdk_ocx_lnex_stat03_s cn; */
1592 };
1593 typedef union bdk_ocx_lnex_stat03 bdk_ocx_lnex_stat03_t;
1594
1595 static inline uint64_t BDK_OCX_LNEX_STAT03(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_STAT03(unsigned long a)1596 static inline uint64_t BDK_OCX_LNEX_STAT03(unsigned long a)
1597 {
1598 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
1599 return 0x87e011008058ll + 0x100ll * ((a) & 0x1f);
1600 __bdk_csr_fatal("OCX_LNEX_STAT03", 1, a, 0, 0, 0);
1601 }
1602
1603 #define typedef_BDK_OCX_LNEX_STAT03(a) bdk_ocx_lnex_stat03_t
1604 #define bustype_BDK_OCX_LNEX_STAT03(a) BDK_CSR_TYPE_RSL
1605 #define basename_BDK_OCX_LNEX_STAT03(a) "OCX_LNEX_STAT03"
1606 #define device_bar_BDK_OCX_LNEX_STAT03(a) 0x0 /* PF_BAR0 */
1607 #define busnum_BDK_OCX_LNEX_STAT03(a) (a)
1608 #define arguments_BDK_OCX_LNEX_STAT03(a) (a),-1,-1,-1
1609
1610 /**
1611 * Register (RSL) ocx_lne#_stat04
1612 *
1613 * OCX Lane Statistic 4 Register
1614 */
1615 union bdk_ocx_lnex_stat04
1616 {
1617 uint64_t u;
1618 struct bdk_ocx_lnex_stat04_s
1619 {
1620 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1621 uint64_t reserved_18_63 : 46;
1622 uint64_t bad_64b67b_cnt : 18; /**< [ 17: 0](RO/H) Number of bad 64B/67B words, meaning bit 65 or 64 has been corrupted. Saturates. Interrupt
1623 on saturation if OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1624 #else /* Word 0 - Little Endian */
1625 uint64_t bad_64b67b_cnt : 18; /**< [ 17: 0](RO/H) Number of bad 64B/67B words, meaning bit 65 or 64 has been corrupted. Saturates. Interrupt
1626 on saturation if OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1627 uint64_t reserved_18_63 : 46;
1628 #endif /* Word 0 - End */
1629 } s;
1630 /* struct bdk_ocx_lnex_stat04_s cn; */
1631 };
1632 typedef union bdk_ocx_lnex_stat04 bdk_ocx_lnex_stat04_t;
1633
1634 static inline uint64_t BDK_OCX_LNEX_STAT04(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_STAT04(unsigned long a)1635 static inline uint64_t BDK_OCX_LNEX_STAT04(unsigned long a)
1636 {
1637 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
1638 return 0x87e011008060ll + 0x100ll * ((a) & 0x1f);
1639 __bdk_csr_fatal("OCX_LNEX_STAT04", 1, a, 0, 0, 0);
1640 }
1641
1642 #define typedef_BDK_OCX_LNEX_STAT04(a) bdk_ocx_lnex_stat04_t
1643 #define bustype_BDK_OCX_LNEX_STAT04(a) BDK_CSR_TYPE_RSL
1644 #define basename_BDK_OCX_LNEX_STAT04(a) "OCX_LNEX_STAT04"
1645 #define device_bar_BDK_OCX_LNEX_STAT04(a) 0x0 /* PF_BAR0 */
1646 #define busnum_BDK_OCX_LNEX_STAT04(a) (a)
1647 #define arguments_BDK_OCX_LNEX_STAT04(a) (a),-1,-1,-1
1648
1649 /**
1650 * Register (RSL) ocx_lne#_stat05
1651 *
1652 * OCX Lane Statistic 5 Register
1653 */
1654 union bdk_ocx_lnex_stat05
1655 {
1656 uint64_t u;
1657 struct bdk_ocx_lnex_stat05_s
1658 {
1659 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1660 uint64_t reserved_27_63 : 37;
1661 uint64_t data_word_cnt : 27; /**< [ 26: 0](RO/H) Number of data words received. Saturates. Interrupt on saturation if
1662 OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1663 #else /* Word 0 - Little Endian */
1664 uint64_t data_word_cnt : 27; /**< [ 26: 0](RO/H) Number of data words received. Saturates. Interrupt on saturation if
1665 OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1666 uint64_t reserved_27_63 : 37;
1667 #endif /* Word 0 - End */
1668 } s;
1669 /* struct bdk_ocx_lnex_stat05_s cn; */
1670 };
1671 typedef union bdk_ocx_lnex_stat05 bdk_ocx_lnex_stat05_t;
1672
1673 static inline uint64_t BDK_OCX_LNEX_STAT05(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_STAT05(unsigned long a)1674 static inline uint64_t BDK_OCX_LNEX_STAT05(unsigned long a)
1675 {
1676 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
1677 return 0x87e011008068ll + 0x100ll * ((a) & 0x1f);
1678 __bdk_csr_fatal("OCX_LNEX_STAT05", 1, a, 0, 0, 0);
1679 }
1680
1681 #define typedef_BDK_OCX_LNEX_STAT05(a) bdk_ocx_lnex_stat05_t
1682 #define bustype_BDK_OCX_LNEX_STAT05(a) BDK_CSR_TYPE_RSL
1683 #define basename_BDK_OCX_LNEX_STAT05(a) "OCX_LNEX_STAT05"
1684 #define device_bar_BDK_OCX_LNEX_STAT05(a) 0x0 /* PF_BAR0 */
1685 #define busnum_BDK_OCX_LNEX_STAT05(a) (a)
1686 #define arguments_BDK_OCX_LNEX_STAT05(a) (a),-1,-1,-1
1687
1688 /**
1689 * Register (RSL) ocx_lne#_stat06
1690 *
1691 * OCX Lane Statistic 6 Register
1692 */
1693 union bdk_ocx_lnex_stat06
1694 {
1695 uint64_t u;
1696 struct bdk_ocx_lnex_stat06_s
1697 {
1698 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1699 uint64_t reserved_27_63 : 37;
1700 uint64_t cntl_word_cnt : 27; /**< [ 26: 0](RO/H) Number of control words received. Saturates. Interrupt on saturation if
1701 OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1702 #else /* Word 0 - Little Endian */
1703 uint64_t cntl_word_cnt : 27; /**< [ 26: 0](RO/H) Number of control words received. Saturates. Interrupt on saturation if
1704 OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1705 uint64_t reserved_27_63 : 37;
1706 #endif /* Word 0 - End */
1707 } s;
1708 /* struct bdk_ocx_lnex_stat06_s cn; */
1709 };
1710 typedef union bdk_ocx_lnex_stat06 bdk_ocx_lnex_stat06_t;
1711
1712 static inline uint64_t BDK_OCX_LNEX_STAT06(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_STAT06(unsigned long a)1713 static inline uint64_t BDK_OCX_LNEX_STAT06(unsigned long a)
1714 {
1715 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
1716 return 0x87e011008070ll + 0x100ll * ((a) & 0x1f);
1717 __bdk_csr_fatal("OCX_LNEX_STAT06", 1, a, 0, 0, 0);
1718 }
1719
1720 #define typedef_BDK_OCX_LNEX_STAT06(a) bdk_ocx_lnex_stat06_t
1721 #define bustype_BDK_OCX_LNEX_STAT06(a) BDK_CSR_TYPE_RSL
1722 #define basename_BDK_OCX_LNEX_STAT06(a) "OCX_LNEX_STAT06"
1723 #define device_bar_BDK_OCX_LNEX_STAT06(a) 0x0 /* PF_BAR0 */
1724 #define busnum_BDK_OCX_LNEX_STAT06(a) (a)
1725 #define arguments_BDK_OCX_LNEX_STAT06(a) (a),-1,-1,-1
1726
1727 /**
1728 * Register (RSL) ocx_lne#_stat07
1729 *
1730 * OCX Lane Statistic 7 Register
1731 */
1732 union bdk_ocx_lnex_stat07
1733 {
1734 uint64_t u;
1735 struct bdk_ocx_lnex_stat07_s
1736 {
1737 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1738 uint64_t reserved_18_63 : 46;
1739 uint64_t unkwn_word_cnt : 18; /**< [ 17: 0](RO/H) Number of unknown control words. Saturates. Interrupt on saturation if
1740 OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1741 #else /* Word 0 - Little Endian */
1742 uint64_t unkwn_word_cnt : 18; /**< [ 17: 0](RO/H) Number of unknown control words. Saturates. Interrupt on saturation if
1743 OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1744 uint64_t reserved_18_63 : 46;
1745 #endif /* Word 0 - End */
1746 } s;
1747 /* struct bdk_ocx_lnex_stat07_s cn; */
1748 };
1749 typedef union bdk_ocx_lnex_stat07 bdk_ocx_lnex_stat07_t;
1750
1751 static inline uint64_t BDK_OCX_LNEX_STAT07(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_STAT07(unsigned long a)1752 static inline uint64_t BDK_OCX_LNEX_STAT07(unsigned long a)
1753 {
1754 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
1755 return 0x87e011008078ll + 0x100ll * ((a) & 0x1f);
1756 __bdk_csr_fatal("OCX_LNEX_STAT07", 1, a, 0, 0, 0);
1757 }
1758
1759 #define typedef_BDK_OCX_LNEX_STAT07(a) bdk_ocx_lnex_stat07_t
1760 #define bustype_BDK_OCX_LNEX_STAT07(a) BDK_CSR_TYPE_RSL
1761 #define basename_BDK_OCX_LNEX_STAT07(a) "OCX_LNEX_STAT07"
1762 #define device_bar_BDK_OCX_LNEX_STAT07(a) 0x0 /* PF_BAR0 */
1763 #define busnum_BDK_OCX_LNEX_STAT07(a) (a)
1764 #define arguments_BDK_OCX_LNEX_STAT07(a) (a),-1,-1,-1
1765
1766 /**
1767 * Register (RSL) ocx_lne#_stat08
1768 *
1769 * OCX Lane Statistic 8 Register
1770 */
1771 union bdk_ocx_lnex_stat08
1772 {
1773 uint64_t u;
1774 struct bdk_ocx_lnex_stat08_s
1775 {
1776 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1777 uint64_t reserved_18_63 : 46;
1778 uint64_t scrm_sync_loss_cnt : 18; /**< [ 17: 0](RO/H) Number of times scrambler synchronization was lost (due to either four
1779 consecutive bad sync words or three consecutive scrambler state
1780 mismatches). Saturates. Interrupt on saturation if
1781 OCX_LNE()_INT_EN[STAT_CNT_OVFL] = 1. */
1782 #else /* Word 0 - Little Endian */
1783 uint64_t scrm_sync_loss_cnt : 18; /**< [ 17: 0](RO/H) Number of times scrambler synchronization was lost (due to either four
1784 consecutive bad sync words or three consecutive scrambler state
1785 mismatches). Saturates. Interrupt on saturation if
1786 OCX_LNE()_INT_EN[STAT_CNT_OVFL] = 1. */
1787 uint64_t reserved_18_63 : 46;
1788 #endif /* Word 0 - End */
1789 } s;
1790 /* struct bdk_ocx_lnex_stat08_s cn; */
1791 };
1792 typedef union bdk_ocx_lnex_stat08 bdk_ocx_lnex_stat08_t;
1793
1794 static inline uint64_t BDK_OCX_LNEX_STAT08(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_STAT08(unsigned long a)1795 static inline uint64_t BDK_OCX_LNEX_STAT08(unsigned long a)
1796 {
1797 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
1798 return 0x87e011008080ll + 0x100ll * ((a) & 0x1f);
1799 __bdk_csr_fatal("OCX_LNEX_STAT08", 1, a, 0, 0, 0);
1800 }
1801
1802 #define typedef_BDK_OCX_LNEX_STAT08(a) bdk_ocx_lnex_stat08_t
1803 #define bustype_BDK_OCX_LNEX_STAT08(a) BDK_CSR_TYPE_RSL
1804 #define basename_BDK_OCX_LNEX_STAT08(a) "OCX_LNEX_STAT08"
1805 #define device_bar_BDK_OCX_LNEX_STAT08(a) 0x0 /* PF_BAR0 */
1806 #define busnum_BDK_OCX_LNEX_STAT08(a) (a)
1807 #define arguments_BDK_OCX_LNEX_STAT08(a) (a),-1,-1,-1
1808
1809 /**
1810 * Register (RSL) ocx_lne#_stat09
1811 *
1812 * OCX Lane Statistic 9 Register
1813 */
1814 union bdk_ocx_lnex_stat09
1815 {
1816 uint64_t u;
1817 struct bdk_ocx_lnex_stat09_s
1818 {
1819 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1820 uint64_t reserved_18_63 : 46;
1821 uint64_t scrm_match_cnt : 18; /**< [ 17: 0](RO/H) Number of scrambler state matches received. Saturates. Interrupt on saturation if
1822 OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1823 #else /* Word 0 - Little Endian */
1824 uint64_t scrm_match_cnt : 18; /**< [ 17: 0](RO/H) Number of scrambler state matches received. Saturates. Interrupt on saturation if
1825 OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1826 uint64_t reserved_18_63 : 46;
1827 #endif /* Word 0 - End */
1828 } s;
1829 /* struct bdk_ocx_lnex_stat09_s cn; */
1830 };
1831 typedef union bdk_ocx_lnex_stat09 bdk_ocx_lnex_stat09_t;
1832
1833 static inline uint64_t BDK_OCX_LNEX_STAT09(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_STAT09(unsigned long a)1834 static inline uint64_t BDK_OCX_LNEX_STAT09(unsigned long a)
1835 {
1836 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
1837 return 0x87e011008088ll + 0x100ll * ((a) & 0x1f);
1838 __bdk_csr_fatal("OCX_LNEX_STAT09", 1, a, 0, 0, 0);
1839 }
1840
1841 #define typedef_BDK_OCX_LNEX_STAT09(a) bdk_ocx_lnex_stat09_t
1842 #define bustype_BDK_OCX_LNEX_STAT09(a) BDK_CSR_TYPE_RSL
1843 #define basename_BDK_OCX_LNEX_STAT09(a) "OCX_LNEX_STAT09"
1844 #define device_bar_BDK_OCX_LNEX_STAT09(a) 0x0 /* PF_BAR0 */
1845 #define busnum_BDK_OCX_LNEX_STAT09(a) (a)
1846 #define arguments_BDK_OCX_LNEX_STAT09(a) (a),-1,-1,-1
1847
1848 /**
1849 * Register (RSL) ocx_lne#_stat10
1850 *
1851 * OCX Lane Statistic 10 Register
1852 */
1853 union bdk_ocx_lnex_stat10
1854 {
1855 uint64_t u;
1856 struct bdk_ocx_lnex_stat10_s
1857 {
1858 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1859 uint64_t reserved_18_63 : 46;
1860 uint64_t skipw_good_cnt : 18; /**< [ 17: 0](RO/H) Number of good skip words. Saturates. Interrupt on saturation if
1861 OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1862 #else /* Word 0 - Little Endian */
1863 uint64_t skipw_good_cnt : 18; /**< [ 17: 0](RO/H) Number of good skip words. Saturates. Interrupt on saturation if
1864 OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1865 uint64_t reserved_18_63 : 46;
1866 #endif /* Word 0 - End */
1867 } s;
1868 /* struct bdk_ocx_lnex_stat10_s cn; */
1869 };
1870 typedef union bdk_ocx_lnex_stat10 bdk_ocx_lnex_stat10_t;
1871
1872 static inline uint64_t BDK_OCX_LNEX_STAT10(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_STAT10(unsigned long a)1873 static inline uint64_t BDK_OCX_LNEX_STAT10(unsigned long a)
1874 {
1875 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
1876 return 0x87e011008090ll + 0x100ll * ((a) & 0x1f);
1877 __bdk_csr_fatal("OCX_LNEX_STAT10", 1, a, 0, 0, 0);
1878 }
1879
1880 #define typedef_BDK_OCX_LNEX_STAT10(a) bdk_ocx_lnex_stat10_t
1881 #define bustype_BDK_OCX_LNEX_STAT10(a) BDK_CSR_TYPE_RSL
1882 #define basename_BDK_OCX_LNEX_STAT10(a) "OCX_LNEX_STAT10"
1883 #define device_bar_BDK_OCX_LNEX_STAT10(a) 0x0 /* PF_BAR0 */
1884 #define busnum_BDK_OCX_LNEX_STAT10(a) (a)
1885 #define arguments_BDK_OCX_LNEX_STAT10(a) (a),-1,-1,-1
1886
1887 /**
1888 * Register (RSL) ocx_lne#_stat11
1889 *
1890 * OCX Lane Statistic 11 Register
1891 */
1892 union bdk_ocx_lnex_stat11
1893 {
1894 uint64_t u;
1895 struct bdk_ocx_lnex_stat11_s
1896 {
1897 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1898 uint64_t reserved_27_63 : 37;
1899 uint64_t crc32_err_cnt : 27; /**< [ 26: 0](RO/H) Number of errors in the lane CRC. Saturates. Interrupt on saturation if
1900 OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1901 #else /* Word 0 - Little Endian */
1902 uint64_t crc32_err_cnt : 27; /**< [ 26: 0](RO/H) Number of errors in the lane CRC. Saturates. Interrupt on saturation if
1903 OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1904 uint64_t reserved_27_63 : 37;
1905 #endif /* Word 0 - End */
1906 } s;
1907 /* struct bdk_ocx_lnex_stat11_s cn; */
1908 };
1909 typedef union bdk_ocx_lnex_stat11 bdk_ocx_lnex_stat11_t;
1910
1911 static inline uint64_t BDK_OCX_LNEX_STAT11(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_STAT11(unsigned long a)1912 static inline uint64_t BDK_OCX_LNEX_STAT11(unsigned long a)
1913 {
1914 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
1915 return 0x87e011008098ll + 0x100ll * ((a) & 0x1f);
1916 __bdk_csr_fatal("OCX_LNEX_STAT11", 1, a, 0, 0, 0);
1917 }
1918
1919 #define typedef_BDK_OCX_LNEX_STAT11(a) bdk_ocx_lnex_stat11_t
1920 #define bustype_BDK_OCX_LNEX_STAT11(a) BDK_CSR_TYPE_RSL
1921 #define basename_BDK_OCX_LNEX_STAT11(a) "OCX_LNEX_STAT11"
1922 #define device_bar_BDK_OCX_LNEX_STAT11(a) 0x0 /* PF_BAR0 */
1923 #define busnum_BDK_OCX_LNEX_STAT11(a) (a)
1924 #define arguments_BDK_OCX_LNEX_STAT11(a) (a),-1,-1,-1
1925
1926 /**
1927 * Register (RSL) ocx_lne#_stat12
1928 *
1929 * OCX Lane Statistic 12 Register
1930 */
1931 union bdk_ocx_lnex_stat12
1932 {
1933 uint64_t u;
1934 struct bdk_ocx_lnex_stat12_s
1935 {
1936 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1937 uint64_t reserved_27_63 : 37;
1938 uint64_t crc32_match_cnt : 27; /**< [ 26: 0](RO/H) Number of CRC32 matches received. Saturates. Interrupt on saturation if
1939 OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1940 #else /* Word 0 - Little Endian */
1941 uint64_t crc32_match_cnt : 27; /**< [ 26: 0](RO/H) Number of CRC32 matches received. Saturates. Interrupt on saturation if
1942 OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1943 uint64_t reserved_27_63 : 37;
1944 #endif /* Word 0 - End */
1945 } s;
1946 /* struct bdk_ocx_lnex_stat12_s cn; */
1947 };
1948 typedef union bdk_ocx_lnex_stat12 bdk_ocx_lnex_stat12_t;
1949
1950 static inline uint64_t BDK_OCX_LNEX_STAT12(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_STAT12(unsigned long a)1951 static inline uint64_t BDK_OCX_LNEX_STAT12(unsigned long a)
1952 {
1953 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
1954 return 0x87e0110080a0ll + 0x100ll * ((a) & 0x1f);
1955 __bdk_csr_fatal("OCX_LNEX_STAT12", 1, a, 0, 0, 0);
1956 }
1957
1958 #define typedef_BDK_OCX_LNEX_STAT12(a) bdk_ocx_lnex_stat12_t
1959 #define bustype_BDK_OCX_LNEX_STAT12(a) BDK_CSR_TYPE_RSL
1960 #define basename_BDK_OCX_LNEX_STAT12(a) "OCX_LNEX_STAT12"
1961 #define device_bar_BDK_OCX_LNEX_STAT12(a) 0x0 /* PF_BAR0 */
1962 #define busnum_BDK_OCX_LNEX_STAT12(a) (a)
1963 #define arguments_BDK_OCX_LNEX_STAT12(a) (a),-1,-1,-1
1964
1965 /**
1966 * Register (RSL) ocx_lne#_stat13
1967 *
1968 * OCX Lane Statistic 13 Register
1969 */
1970 union bdk_ocx_lnex_stat13
1971 {
1972 uint64_t u;
1973 struct bdk_ocx_lnex_stat13_s
1974 {
1975 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1976 uint64_t reserved_16_63 : 48;
1977 uint64_t trn_bad_cnt : 16; /**< [ 15: 0](RO/H) Number of training frames received with an invalid control channel. Saturates. Interrupt
1978 on saturation if OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1979 #else /* Word 0 - Little Endian */
1980 uint64_t trn_bad_cnt : 16; /**< [ 15: 0](RO/H) Number of training frames received with an invalid control channel. Saturates. Interrupt
1981 on saturation if OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
1982 uint64_t reserved_16_63 : 48;
1983 #endif /* Word 0 - End */
1984 } s;
1985 /* struct bdk_ocx_lnex_stat13_s cn; */
1986 };
1987 typedef union bdk_ocx_lnex_stat13 bdk_ocx_lnex_stat13_t;
1988
1989 static inline uint64_t BDK_OCX_LNEX_STAT13(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_STAT13(unsigned long a)1990 static inline uint64_t BDK_OCX_LNEX_STAT13(unsigned long a)
1991 {
1992 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
1993 return 0x87e0110080a8ll + 0x100ll * ((a) & 0x1f);
1994 __bdk_csr_fatal("OCX_LNEX_STAT13", 1, a, 0, 0, 0);
1995 }
1996
1997 #define typedef_BDK_OCX_LNEX_STAT13(a) bdk_ocx_lnex_stat13_t
1998 #define bustype_BDK_OCX_LNEX_STAT13(a) BDK_CSR_TYPE_RSL
1999 #define basename_BDK_OCX_LNEX_STAT13(a) "OCX_LNEX_STAT13"
2000 #define device_bar_BDK_OCX_LNEX_STAT13(a) 0x0 /* PF_BAR0 */
2001 #define busnum_BDK_OCX_LNEX_STAT13(a) (a)
2002 #define arguments_BDK_OCX_LNEX_STAT13(a) (a),-1,-1,-1
2003
2004 /**
2005 * Register (RSL) ocx_lne#_stat14
2006 *
2007 * OCX Lane Statistic 14 Register
2008 */
2009 union bdk_ocx_lnex_stat14
2010 {
2011 uint64_t u;
2012 struct bdk_ocx_lnex_stat14_s
2013 {
2014 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2015 uint64_t reserved_16_63 : 48;
2016 uint64_t trn_prbs_bad_cnt : 16; /**< [ 15: 0](RO/H) Number of training frames received with a bad PRBS pattern. Saturates. Interrupt on
2017 saturation if OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
2018 #else /* Word 0 - Little Endian */
2019 uint64_t trn_prbs_bad_cnt : 16; /**< [ 15: 0](RO/H) Number of training frames received with a bad PRBS pattern. Saturates. Interrupt on
2020 saturation if OCX_LNE(0..23)_INT_EN[STAT_CNT_OVFL] = 1. */
2021 uint64_t reserved_16_63 : 48;
2022 #endif /* Word 0 - End */
2023 } s;
2024 /* struct bdk_ocx_lnex_stat14_s cn; */
2025 };
2026 typedef union bdk_ocx_lnex_stat14 bdk_ocx_lnex_stat14_t;
2027
2028 static inline uint64_t BDK_OCX_LNEX_STAT14(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_STAT14(unsigned long a)2029 static inline uint64_t BDK_OCX_LNEX_STAT14(unsigned long a)
2030 {
2031 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
2032 return 0x87e0110080b0ll + 0x100ll * ((a) & 0x1f);
2033 __bdk_csr_fatal("OCX_LNEX_STAT14", 1, a, 0, 0, 0);
2034 }
2035
2036 #define typedef_BDK_OCX_LNEX_STAT14(a) bdk_ocx_lnex_stat14_t
2037 #define bustype_BDK_OCX_LNEX_STAT14(a) BDK_CSR_TYPE_RSL
2038 #define basename_BDK_OCX_LNEX_STAT14(a) "OCX_LNEX_STAT14"
2039 #define device_bar_BDK_OCX_LNEX_STAT14(a) 0x0 /* PF_BAR0 */
2040 #define busnum_BDK_OCX_LNEX_STAT14(a) (a)
2041 #define arguments_BDK_OCX_LNEX_STAT14(a) (a),-1,-1,-1
2042
2043 /**
2044 * Register (RSL) ocx_lne#_status
2045 *
2046 * OCX Lane Status Register
2047 */
2048 union bdk_ocx_lnex_status
2049 {
2050 uint64_t u;
2051 struct bdk_ocx_lnex_status_s
2052 {
2053 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2054 uint64_t reserved_3_63 : 61;
2055 uint64_t rx_trn_val : 1; /**< [ 2: 2](R/W/H) The control channel of a link training was received without any errors. */
2056 uint64_t rx_scrm_sync : 1; /**< [ 1: 1](RO/H) RX scrambler synchronization status. Set to 1 when synchronization achieved. */
2057 uint64_t rx_bdry_sync : 1; /**< [ 0: 0](RO/H) RX word boundary sync status. Set to 1 when synchronization achieved. */
2058 #else /* Word 0 - Little Endian */
2059 uint64_t rx_bdry_sync : 1; /**< [ 0: 0](RO/H) RX word boundary sync status. Set to 1 when synchronization achieved. */
2060 uint64_t rx_scrm_sync : 1; /**< [ 1: 1](RO/H) RX scrambler synchronization status. Set to 1 when synchronization achieved. */
2061 uint64_t rx_trn_val : 1; /**< [ 2: 2](R/W/H) The control channel of a link training was received without any errors. */
2062 uint64_t reserved_3_63 : 61;
2063 #endif /* Word 0 - End */
2064 } s;
2065 /* struct bdk_ocx_lnex_status_s cn; */
2066 };
2067 typedef union bdk_ocx_lnex_status bdk_ocx_lnex_status_t;
2068
2069 static inline uint64_t BDK_OCX_LNEX_STATUS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_STATUS(unsigned long a)2070 static inline uint64_t BDK_OCX_LNEX_STATUS(unsigned long a)
2071 {
2072 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
2073 return 0x87e011008008ll + 0x100ll * ((a) & 0x1f);
2074 __bdk_csr_fatal("OCX_LNEX_STATUS", 1, a, 0, 0, 0);
2075 }
2076
2077 #define typedef_BDK_OCX_LNEX_STATUS(a) bdk_ocx_lnex_status_t
2078 #define bustype_BDK_OCX_LNEX_STATUS(a) BDK_CSR_TYPE_RSL
2079 #define basename_BDK_OCX_LNEX_STATUS(a) "OCX_LNEX_STATUS"
2080 #define device_bar_BDK_OCX_LNEX_STATUS(a) 0x0 /* PF_BAR0 */
2081 #define busnum_BDK_OCX_LNEX_STATUS(a) (a)
2082 #define arguments_BDK_OCX_LNEX_STATUS(a) (a),-1,-1,-1
2083
2084 /**
2085 * Register (RSL) ocx_lne#_sts_msg
2086 *
2087 * OCX Lane Status Message Register
2088 */
2089 union bdk_ocx_lnex_sts_msg
2090 {
2091 uint64_t u;
2092 struct bdk_ocx_lnex_sts_msg_s
2093 {
2094 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2095 uint64_t rx_meta_val : 1; /**< [ 63: 63](RO/H) Meta-data received in the diagnostic word (per-lane) is valid. */
2096 uint64_t reserved_37_62 : 26;
2097 uint64_t rx_meta_dat : 3; /**< [ 36: 34](RO/H) Meta-data received in the diagnostic word (per-lane). */
2098 uint64_t rx_lne_stat : 1; /**< [ 33: 33](RO/H) Lane status received in the diagnostic word (per-lane). Set to 1 when healthy
2099 (according to the Interlaken spec). */
2100 uint64_t rx_lnk_stat : 1; /**< [ 32: 32](RO/H) Link status received in the diagnostic word (per-lane). Set to 1 when healthy
2101 (according to the Interlaken spec). */
2102 uint64_t reserved_5_31 : 27;
2103 uint64_t tx_meta_dat : 3; /**< [ 4: 2](RO/H) Meta-data transmitted in the diagnostic word (per-lane). */
2104 uint64_t tx_lne_stat : 1; /**< [ 1: 1](R/W/H) Lane status transmitted in the diagnostic word (per-lane). Set to 1 means
2105 healthy (according to the Interlaken spec). */
2106 uint64_t tx_lnk_stat : 1; /**< [ 0: 0](R/W/H) Link status transmitted in the diagnostic word (per-lane). Set to 1 means
2107 healthy (according to the Interlaken spec). */
2108 #else /* Word 0 - Little Endian */
2109 uint64_t tx_lnk_stat : 1; /**< [ 0: 0](R/W/H) Link status transmitted in the diagnostic word (per-lane). Set to 1 means
2110 healthy (according to the Interlaken spec). */
2111 uint64_t tx_lne_stat : 1; /**< [ 1: 1](R/W/H) Lane status transmitted in the diagnostic word (per-lane). Set to 1 means
2112 healthy (according to the Interlaken spec). */
2113 uint64_t tx_meta_dat : 3; /**< [ 4: 2](RO/H) Meta-data transmitted in the diagnostic word (per-lane). */
2114 uint64_t reserved_5_31 : 27;
2115 uint64_t rx_lnk_stat : 1; /**< [ 32: 32](RO/H) Link status received in the diagnostic word (per-lane). Set to 1 when healthy
2116 (according to the Interlaken spec). */
2117 uint64_t rx_lne_stat : 1; /**< [ 33: 33](RO/H) Lane status received in the diagnostic word (per-lane). Set to 1 when healthy
2118 (according to the Interlaken spec). */
2119 uint64_t rx_meta_dat : 3; /**< [ 36: 34](RO/H) Meta-data received in the diagnostic word (per-lane). */
2120 uint64_t reserved_37_62 : 26;
2121 uint64_t rx_meta_val : 1; /**< [ 63: 63](RO/H) Meta-data received in the diagnostic word (per-lane) is valid. */
2122 #endif /* Word 0 - End */
2123 } s;
2124 /* struct bdk_ocx_lnex_sts_msg_s cn; */
2125 };
2126 typedef union bdk_ocx_lnex_sts_msg bdk_ocx_lnex_sts_msg_t;
2127
2128 static inline uint64_t BDK_OCX_LNEX_STS_MSG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_STS_MSG(unsigned long a)2129 static inline uint64_t BDK_OCX_LNEX_STS_MSG(unsigned long a)
2130 {
2131 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
2132 return 0x87e011008010ll + 0x100ll * ((a) & 0x1f);
2133 __bdk_csr_fatal("OCX_LNEX_STS_MSG", 1, a, 0, 0, 0);
2134 }
2135
2136 #define typedef_BDK_OCX_LNEX_STS_MSG(a) bdk_ocx_lnex_sts_msg_t
2137 #define bustype_BDK_OCX_LNEX_STS_MSG(a) BDK_CSR_TYPE_RSL
2138 #define basename_BDK_OCX_LNEX_STS_MSG(a) "OCX_LNEX_STS_MSG"
2139 #define device_bar_BDK_OCX_LNEX_STS_MSG(a) 0x0 /* PF_BAR0 */
2140 #define busnum_BDK_OCX_LNEX_STS_MSG(a) (a)
2141 #define arguments_BDK_OCX_LNEX_STS_MSG(a) (a),-1,-1,-1
2142
2143 /**
2144 * Register (RSL) ocx_lne#_trn_ctl
2145 *
2146 * OCX Lane Training Link Partner Register
2147 */
2148 union bdk_ocx_lnex_trn_ctl
2149 {
2150 uint64_t u;
2151 struct bdk_ocx_lnex_trn_ctl_s
2152 {
2153 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2154 uint64_t reserved_4_63 : 60;
2155 uint64_t lock : 1; /**< [ 3: 3](RO/H) Training frame boundary locked. */
2156 uint64_t done : 1; /**< [ 2: 2](R/W/H) Training done. For diagnostic use only may be written to 1 to force training done. */
2157 uint64_t ena : 1; /**< [ 1: 1](RO/H) OCX_LNEX_TRN_CTL[TRN_ENA]=1 indicates that the lane is currently training. It is a status
2158 bit used for debug. It will read as zero when training has completed or when the QLM
2159 isn't ready for training. */
2160 uint64_t eie_detect : 1; /**< [ 0: 0](RO/H) Electrical idle exit (EIE) detected. */
2161 #else /* Word 0 - Little Endian */
2162 uint64_t eie_detect : 1; /**< [ 0: 0](RO/H) Electrical idle exit (EIE) detected. */
2163 uint64_t ena : 1; /**< [ 1: 1](RO/H) OCX_LNEX_TRN_CTL[TRN_ENA]=1 indicates that the lane is currently training. It is a status
2164 bit used for debug. It will read as zero when training has completed or when the QLM
2165 isn't ready for training. */
2166 uint64_t done : 1; /**< [ 2: 2](R/W/H) Training done. For diagnostic use only may be written to 1 to force training done. */
2167 uint64_t lock : 1; /**< [ 3: 3](RO/H) Training frame boundary locked. */
2168 uint64_t reserved_4_63 : 60;
2169 #endif /* Word 0 - End */
2170 } s;
2171 /* struct bdk_ocx_lnex_trn_ctl_s cn; */
2172 };
2173 typedef union bdk_ocx_lnex_trn_ctl bdk_ocx_lnex_trn_ctl_t;
2174
2175 static inline uint64_t BDK_OCX_LNEX_TRN_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_TRN_CTL(unsigned long a)2176 static inline uint64_t BDK_OCX_LNEX_TRN_CTL(unsigned long a)
2177 {
2178 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
2179 return 0x87e0110080d0ll + 0x100ll * ((a) & 0x1f);
2180 __bdk_csr_fatal("OCX_LNEX_TRN_CTL", 1, a, 0, 0, 0);
2181 }
2182
2183 #define typedef_BDK_OCX_LNEX_TRN_CTL(a) bdk_ocx_lnex_trn_ctl_t
2184 #define bustype_BDK_OCX_LNEX_TRN_CTL(a) BDK_CSR_TYPE_RSL
2185 #define basename_BDK_OCX_LNEX_TRN_CTL(a) "OCX_LNEX_TRN_CTL"
2186 #define device_bar_BDK_OCX_LNEX_TRN_CTL(a) 0x0 /* PF_BAR0 */
2187 #define busnum_BDK_OCX_LNEX_TRN_CTL(a) (a)
2188 #define arguments_BDK_OCX_LNEX_TRN_CTL(a) (a),-1,-1,-1
2189
2190 /**
2191 * Register (RSL) ocx_lne#_trn_ld
2192 *
2193 * OCX Lane Training Local Device Register
2194 */
2195 union bdk_ocx_lnex_trn_ld
2196 {
2197 uint64_t u;
2198 struct bdk_ocx_lnex_trn_ld_s
2199 {
2200 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2201 uint64_t lp_manual : 1; /**< [ 63: 63](R/W) Allow software to manually manipulate local device CU/SR by ignoring hardware update. */
2202 uint64_t reserved_49_62 : 14;
2203 uint64_t ld_cu_val : 1; /**< [ 48: 48](RO/H) Local device coefficient update field valid. */
2204 uint64_t ld_cu_dat : 16; /**< [ 47: 32](R/W/H) Local device coefficient update field data.
2205 The format of this field is BGX_SPU_BR_TRAIN_CUP_S. */
2206 uint64_t reserved_17_31 : 15;
2207 uint64_t ld_sr_val : 1; /**< [ 16: 16](RO/H) Local device status report field valid. */
2208 uint64_t ld_sr_dat : 16; /**< [ 15: 0](R/W/H) Local device status report field data.
2209 The format of this field is BGX_SPU_BR_TRAIN_REP_S. */
2210 #else /* Word 0 - Little Endian */
2211 uint64_t ld_sr_dat : 16; /**< [ 15: 0](R/W/H) Local device status report field data.
2212 The format of this field is BGX_SPU_BR_TRAIN_REP_S. */
2213 uint64_t ld_sr_val : 1; /**< [ 16: 16](RO/H) Local device status report field valid. */
2214 uint64_t reserved_17_31 : 15;
2215 uint64_t ld_cu_dat : 16; /**< [ 47: 32](R/W/H) Local device coefficient update field data.
2216 The format of this field is BGX_SPU_BR_TRAIN_CUP_S. */
2217 uint64_t ld_cu_val : 1; /**< [ 48: 48](RO/H) Local device coefficient update field valid. */
2218 uint64_t reserved_49_62 : 14;
2219 uint64_t lp_manual : 1; /**< [ 63: 63](R/W) Allow software to manually manipulate local device CU/SR by ignoring hardware update. */
2220 #endif /* Word 0 - End */
2221 } s;
2222 /* struct bdk_ocx_lnex_trn_ld_s cn; */
2223 };
2224 typedef union bdk_ocx_lnex_trn_ld bdk_ocx_lnex_trn_ld_t;
2225
2226 static inline uint64_t BDK_OCX_LNEX_TRN_LD(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_TRN_LD(unsigned long a)2227 static inline uint64_t BDK_OCX_LNEX_TRN_LD(unsigned long a)
2228 {
2229 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
2230 return 0x87e0110080c0ll + 0x100ll * ((a) & 0x1f);
2231 __bdk_csr_fatal("OCX_LNEX_TRN_LD", 1, a, 0, 0, 0);
2232 }
2233
2234 #define typedef_BDK_OCX_LNEX_TRN_LD(a) bdk_ocx_lnex_trn_ld_t
2235 #define bustype_BDK_OCX_LNEX_TRN_LD(a) BDK_CSR_TYPE_RSL
2236 #define basename_BDK_OCX_LNEX_TRN_LD(a) "OCX_LNEX_TRN_LD"
2237 #define device_bar_BDK_OCX_LNEX_TRN_LD(a) 0x0 /* PF_BAR0 */
2238 #define busnum_BDK_OCX_LNEX_TRN_LD(a) (a)
2239 #define arguments_BDK_OCX_LNEX_TRN_LD(a) (a),-1,-1,-1
2240
2241 /**
2242 * Register (RSL) ocx_lne#_trn_lp
2243 *
2244 * OCX Lane Training Link Partner Register
2245 */
2246 union bdk_ocx_lnex_trn_lp
2247 {
2248 uint64_t u;
2249 struct bdk_ocx_lnex_trn_lp_s
2250 {
2251 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2252 uint64_t reserved_49_63 : 15;
2253 uint64_t lp_cu_val : 1; /**< [ 48: 48](RO/H) Link partner coefficient update field valid. */
2254 uint64_t lp_cu_dat : 16; /**< [ 47: 32](RO/H) Link partner coefficient update field data.
2255 The format of this field is BGX_SPU_BR_TRAIN_CUP_S. */
2256 uint64_t reserved_17_31 : 15;
2257 uint64_t lp_sr_val : 1; /**< [ 16: 16](RO/H) Link partner status report field valid. */
2258 uint64_t lp_sr_dat : 16; /**< [ 15: 0](RO/H) Link partner status report field data.
2259 The format of this field is BGX_SPU_BR_TRAIN_REP_S. */
2260 #else /* Word 0 - Little Endian */
2261 uint64_t lp_sr_dat : 16; /**< [ 15: 0](RO/H) Link partner status report field data.
2262 The format of this field is BGX_SPU_BR_TRAIN_REP_S. */
2263 uint64_t lp_sr_val : 1; /**< [ 16: 16](RO/H) Link partner status report field valid. */
2264 uint64_t reserved_17_31 : 15;
2265 uint64_t lp_cu_dat : 16; /**< [ 47: 32](RO/H) Link partner coefficient update field data.
2266 The format of this field is BGX_SPU_BR_TRAIN_CUP_S. */
2267 uint64_t lp_cu_val : 1; /**< [ 48: 48](RO/H) Link partner coefficient update field valid. */
2268 uint64_t reserved_49_63 : 15;
2269 #endif /* Word 0 - End */
2270 } s;
2271 /* struct bdk_ocx_lnex_trn_lp_s cn; */
2272 };
2273 typedef union bdk_ocx_lnex_trn_lp bdk_ocx_lnex_trn_lp_t;
2274
2275 static inline uint64_t BDK_OCX_LNEX_TRN_LP(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNEX_TRN_LP(unsigned long a)2276 static inline uint64_t BDK_OCX_LNEX_TRN_LP(unsigned long a)
2277 {
2278 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=23))
2279 return 0x87e0110080c8ll + 0x100ll * ((a) & 0x1f);
2280 __bdk_csr_fatal("OCX_LNEX_TRN_LP", 1, a, 0, 0, 0);
2281 }
2282
2283 #define typedef_BDK_OCX_LNEX_TRN_LP(a) bdk_ocx_lnex_trn_lp_t
2284 #define bustype_BDK_OCX_LNEX_TRN_LP(a) BDK_CSR_TYPE_RSL
2285 #define basename_BDK_OCX_LNEX_TRN_LP(a) "OCX_LNEX_TRN_LP"
2286 #define device_bar_BDK_OCX_LNEX_TRN_LP(a) 0x0 /* PF_BAR0 */
2287 #define busnum_BDK_OCX_LNEX_TRN_LP(a) (a)
2288 #define arguments_BDK_OCX_LNEX_TRN_LP(a) (a),-1,-1,-1
2289
2290 /**
2291 * Register (RSL) ocx_lne_dbg
2292 *
2293 * OCX Lane Debug Register
2294 */
2295 union bdk_ocx_lne_dbg
2296 {
2297 uint64_t u;
2298 struct bdk_ocx_lne_dbg_s
2299 {
2300 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2301 uint64_t timeout : 24; /**< [ 63: 40](R/W/H) Number of core-clock cycles (RCLKs) used by the bad lane timer. If this timer
2302 expires before all enabled lanes can be made ready, then any lane that is not
2303 ready is disabled via OCX_QLM()_CFG[SER_LANE_BAD]. For diagnostic use only. */
2304 uint64_t reserved_38_39 : 2;
2305 uint64_t frc_stats_ena : 1; /**< [ 37: 37](R/W) Enable FRC statistic counters. */
2306 uint64_t rx_dis_psh_skip : 1; /**< [ 36: 36](R/W/H) When [RX_DIS_PSH_SKIP] = 0, skip words are destriped. When [RX_DIS_PSH_SKIP] =
2307 1, skip words are discarded in the lane logic. If the lane is in internal
2308 loopback mode, [RX_DIS_PSH_SKIP] is ignored and skip words are always discarded
2309 in the lane logic. */
2310 uint64_t rx_mfrm_len : 2; /**< [ 35: 34](R/W/H) The quantity of data received on each lane including one sync word, scrambler state,
2311 diagnostic word, zero or more skip words, and the data payload.
2312 0x0 = 2048 words.
2313 0x1 = 1024 words.
2314 0x2 = 512 words.
2315 0x3 = 128 words. */
2316 uint64_t rx_dis_ukwn : 1; /**< [ 33: 33](R/W) Disable normal response to unknown words. They are still logged but do not cause an error
2317 to all open channels. */
2318 uint64_t rx_dis_scram : 1; /**< [ 32: 32](R/W) Disable lane scrambler. */
2319 uint64_t reserved_5_31 : 27;
2320 uint64_t tx_lane_rev : 1; /**< [ 4: 4](R/W) TX lane reversal. When enabled, lane destriping is performed from the most significant
2321 lane enabled to least significant lane enabled [QLM_SELECT] must be 0x0 before changing
2322 [LANE_REV]. */
2323 uint64_t tx_mfrm_len : 2; /**< [ 3: 2](R/W/H) The quantity of data sent on each lane including one sync word, scrambler state,
2324 diagnostic word, zero or more skip words, and the data payload.
2325 0x0 = 2048 words.
2326 0x1 = 1024 words.
2327 0x2 = 512 words.
2328 0x3 = 128 words. */
2329 uint64_t tx_dis_dispr : 1; /**< [ 1: 1](R/W) Disparity disable. */
2330 uint64_t tx_dis_scram : 1; /**< [ 0: 0](R/W) Scrambler disable. */
2331 #else /* Word 0 - Little Endian */
2332 uint64_t tx_dis_scram : 1; /**< [ 0: 0](R/W) Scrambler disable. */
2333 uint64_t tx_dis_dispr : 1; /**< [ 1: 1](R/W) Disparity disable. */
2334 uint64_t tx_mfrm_len : 2; /**< [ 3: 2](R/W/H) The quantity of data sent on each lane including one sync word, scrambler state,
2335 diagnostic word, zero or more skip words, and the data payload.
2336 0x0 = 2048 words.
2337 0x1 = 1024 words.
2338 0x2 = 512 words.
2339 0x3 = 128 words. */
2340 uint64_t tx_lane_rev : 1; /**< [ 4: 4](R/W) TX lane reversal. When enabled, lane destriping is performed from the most significant
2341 lane enabled to least significant lane enabled [QLM_SELECT] must be 0x0 before changing
2342 [LANE_REV]. */
2343 uint64_t reserved_5_31 : 27;
2344 uint64_t rx_dis_scram : 1; /**< [ 32: 32](R/W) Disable lane scrambler. */
2345 uint64_t rx_dis_ukwn : 1; /**< [ 33: 33](R/W) Disable normal response to unknown words. They are still logged but do not cause an error
2346 to all open channels. */
2347 uint64_t rx_mfrm_len : 2; /**< [ 35: 34](R/W/H) The quantity of data received on each lane including one sync word, scrambler state,
2348 diagnostic word, zero or more skip words, and the data payload.
2349 0x0 = 2048 words.
2350 0x1 = 1024 words.
2351 0x2 = 512 words.
2352 0x3 = 128 words. */
2353 uint64_t rx_dis_psh_skip : 1; /**< [ 36: 36](R/W/H) When [RX_DIS_PSH_SKIP] = 0, skip words are destriped. When [RX_DIS_PSH_SKIP] =
2354 1, skip words are discarded in the lane logic. If the lane is in internal
2355 loopback mode, [RX_DIS_PSH_SKIP] is ignored and skip words are always discarded
2356 in the lane logic. */
2357 uint64_t frc_stats_ena : 1; /**< [ 37: 37](R/W) Enable FRC statistic counters. */
2358 uint64_t reserved_38_39 : 2;
2359 uint64_t timeout : 24; /**< [ 63: 40](R/W/H) Number of core-clock cycles (RCLKs) used by the bad lane timer. If this timer
2360 expires before all enabled lanes can be made ready, then any lane that is not
2361 ready is disabled via OCX_QLM()_CFG[SER_LANE_BAD]. For diagnostic use only. */
2362 #endif /* Word 0 - End */
2363 } s;
2364 /* struct bdk_ocx_lne_dbg_s cn; */
2365 };
2366 typedef union bdk_ocx_lne_dbg bdk_ocx_lne_dbg_t;
2367
2368 #define BDK_OCX_LNE_DBG BDK_OCX_LNE_DBG_FUNC()
2369 static inline uint64_t BDK_OCX_LNE_DBG_FUNC(void) __attribute__ ((pure, always_inline));
BDK_OCX_LNE_DBG_FUNC(void)2370 static inline uint64_t BDK_OCX_LNE_DBG_FUNC(void)
2371 {
2372 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX))
2373 return 0x87e01100ff00ll;
2374 __bdk_csr_fatal("OCX_LNE_DBG", 0, 0, 0, 0, 0);
2375 }
2376
2377 #define typedef_BDK_OCX_LNE_DBG bdk_ocx_lne_dbg_t
2378 #define bustype_BDK_OCX_LNE_DBG BDK_CSR_TYPE_RSL
2379 #define basename_BDK_OCX_LNE_DBG "OCX_LNE_DBG"
2380 #define device_bar_BDK_OCX_LNE_DBG 0x0 /* PF_BAR0 */
2381 #define busnum_BDK_OCX_LNE_DBG 0
2382 #define arguments_BDK_OCX_LNE_DBG -1,-1,-1,-1
2383
2384 /**
2385 * Register (RSL) ocx_lnk#_cfg
2386 *
2387 * OCX Link 0-2 Configuration Registers
2388 */
2389 union bdk_ocx_lnkx_cfg
2390 {
2391 uint64_t u;
2392 struct bdk_ocx_lnkx_cfg_s
2393 {
2394 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2395 uint64_t reserved_54_63 : 10;
2396 uint64_t qlm_manual : 6; /**< [ 53: 48](R/W/H) QLM manual mask, where each bit corresponds to a QLM. A link automatically selects a QLM
2397 unless either QLM_MANUAL[QLM] = 1 or a QLM is not eligible for the link.
2398
2399 _ QLM_MANUAL\<0\> = LNE(0..3) = QLM0.
2400 _ QLM_MANUAL\<1\> = LNE(7..4) = QLM1.
2401 _ QLM_MANUAL\<2\> = LNE(11..8) = QLM2.
2402 _ QLM_MANUAL\<3\> = LNE(15..12) = QLM3.
2403 _ QLM_MANUAL\<4\> = LNE(19..16) = QLM4.
2404 _ QLM_MANUAL\<5\> = LNE(23..23) = QLM5.
2405 _ LINK 0 may not select QLM4, QLM5.
2406 _ LINK 1 may not select QLM0, QLM1, QLM4, QLM5.
2407 _ LINK 2 may not select QLM0, QLM1.
2408
2409 During a cold reset, this field is initialized to 0x3F when OCI_SPD\<3:0\> == 0xF.
2410
2411 During a cold reset, this field is initialized to 0x0 when OCI_SPD\<3:0\> != 0xF.
2412
2413 This field is not modified by hardware at any other time.
2414
2415 This field is not affected by soft or warm reset. */
2416 uint64_t reserved_38_47 : 10;
2417 uint64_t qlm_select : 6; /**< [ 37: 32](R/W/H) QLM select mask, where each bit corresponds to a QLM. A link will transmit/receive data
2418 using only the selected QLMs. A link is enabled if any QLM is selected. The same QLM
2419 should not be selected for multiple links.
2420 [LANE_REV] has no effect on this mapping.
2421
2422 _ QLM_SELECT\<0\> = LNE(0..3) = QLM0.
2423 _ QLM_SELECT\<1\> = LNE(7..4) = QLM1.
2424 _ QLM_SELECT\<2\> = LNE(11..8) = QLM2.
2425 _ QLM_SELECT\<3\> = LNE(15..12) = QLM3.
2426 _ QLM_SELECT\<4\> = LNE(19..16) = QLM4.
2427 _ QLM_SELECT\<5\> = LNE(23..23) = QLM5.
2428 _ LINK 0 may not select QLM4, QLM5.
2429 _ LINK 1 may not select QLM0, QLM1, QLM4, QLM5.
2430 _ LINK 2 may not select QLM0, QLM1.
2431 _ LINK 2 may not select QLM2 or QLM3 when LINK1 selects any QLM.
2432 _ LINK 0 may not select QLM2 or QLM3 when LINK1 selects any QLM.
2433 _ LINK 0 automatically selects QLM0 when [QLM_MANUAL]\<0\>=0.
2434 _ LINK 0 automatically selects QLM1 when [QLM_MANUAL]\<1\>=0.
2435 _ LINK 0 automatically selects QLM2 when [QLM_MANUAL]\<2\>=0 and OCX_QLM2_CFG[SER_LOCAL]=0.
2436 _ LINK 1 automatically selects QLM2 when [QLM_MANUAL]\<2\>=0 and OCX_QLM2_CFG[SER_LOCAL]=1.
2437 _ LINK 1 automatically selects QLM3 when [QLM_MANUAL]\<3\>=0 and OCX_QLM3_CFG[SER_LOCAL]=1.
2438 _ LINK 2 automatically selects QLM3 when [QLM_MANUAL]\<3\>=0 and OCX_QLM3_CFG[SER_LOCAL]=0.
2439 _ LINK 3 automatically selects QLM4 when [QLM_MANUAL]\<4\>=0.
2440 _ LINK 3 automatically selects QLM5 when [QLM_MANUAL]\<5\>=0.
2441
2442 A link with [QLM_SELECT] = 0x0 is invalid and will never exchange traffic with the
2443 link partner. */
2444 uint64_t reserved_29_31 : 3;
2445 uint64_t data_rate : 13; /**< [ 28: 16](R/W/H) The number of core-clock cycles (RCLKs) to transmit 32 words, where each word is
2446 67 bits. Hardware automatically calculates a conservative value for this
2447 field. Software can override the calculation by writing
2448 TX_DAT_RATE=roundup((67*RCLK / GBAUD)*32). */
2449 uint64_t low_delay : 6; /**< [ 15: 10](R/W) The delay before reacting to a lane low data indication, as a multiple of 64 core-clock
2450 cycles (RCLKs). */
2451 uint64_t lane_align_dis : 1; /**< [ 9: 9](R/W/H) Disable the RX lane alignment. */
2452 uint64_t lane_rev : 1; /**< [ 8: 8](R/W/H) RX lane reversal. When enabled, lane destriping is performed from the most significant
2453 lane enabled to least significant lane enabled [QLM_SELECT] must be 0x0 before changing
2454 [LANE_REV]. */
2455 uint64_t lane_rev_auto : 1; /**< [ 7: 7](RAZ) Reserved. */
2456 uint64_t reserved_0_6 : 7;
2457 #else /* Word 0 - Little Endian */
2458 uint64_t reserved_0_6 : 7;
2459 uint64_t lane_rev_auto : 1; /**< [ 7: 7](RAZ) Reserved. */
2460 uint64_t lane_rev : 1; /**< [ 8: 8](R/W/H) RX lane reversal. When enabled, lane destriping is performed from the most significant
2461 lane enabled to least significant lane enabled [QLM_SELECT] must be 0x0 before changing
2462 [LANE_REV]. */
2463 uint64_t lane_align_dis : 1; /**< [ 9: 9](R/W/H) Disable the RX lane alignment. */
2464 uint64_t low_delay : 6; /**< [ 15: 10](R/W) The delay before reacting to a lane low data indication, as a multiple of 64 core-clock
2465 cycles (RCLKs). */
2466 uint64_t data_rate : 13; /**< [ 28: 16](R/W/H) The number of core-clock cycles (RCLKs) to transmit 32 words, where each word is
2467 67 bits. Hardware automatically calculates a conservative value for this
2468 field. Software can override the calculation by writing
2469 TX_DAT_RATE=roundup((67*RCLK / GBAUD)*32). */
2470 uint64_t reserved_29_31 : 3;
2471 uint64_t qlm_select : 6; /**< [ 37: 32](R/W/H) QLM select mask, where each bit corresponds to a QLM. A link will transmit/receive data
2472 using only the selected QLMs. A link is enabled if any QLM is selected. The same QLM
2473 should not be selected for multiple links.
2474 [LANE_REV] has no effect on this mapping.
2475
2476 _ QLM_SELECT\<0\> = LNE(0..3) = QLM0.
2477 _ QLM_SELECT\<1\> = LNE(7..4) = QLM1.
2478 _ QLM_SELECT\<2\> = LNE(11..8) = QLM2.
2479 _ QLM_SELECT\<3\> = LNE(15..12) = QLM3.
2480 _ QLM_SELECT\<4\> = LNE(19..16) = QLM4.
2481 _ QLM_SELECT\<5\> = LNE(23..23) = QLM5.
2482 _ LINK 0 may not select QLM4, QLM5.
2483 _ LINK 1 may not select QLM0, QLM1, QLM4, QLM5.
2484 _ LINK 2 may not select QLM0, QLM1.
2485 _ LINK 2 may not select QLM2 or QLM3 when LINK1 selects any QLM.
2486 _ LINK 0 may not select QLM2 or QLM3 when LINK1 selects any QLM.
2487 _ LINK 0 automatically selects QLM0 when [QLM_MANUAL]\<0\>=0.
2488 _ LINK 0 automatically selects QLM1 when [QLM_MANUAL]\<1\>=0.
2489 _ LINK 0 automatically selects QLM2 when [QLM_MANUAL]\<2\>=0 and OCX_QLM2_CFG[SER_LOCAL]=0.
2490 _ LINK 1 automatically selects QLM2 when [QLM_MANUAL]\<2\>=0 and OCX_QLM2_CFG[SER_LOCAL]=1.
2491 _ LINK 1 automatically selects QLM3 when [QLM_MANUAL]\<3\>=0 and OCX_QLM3_CFG[SER_LOCAL]=1.
2492 _ LINK 2 automatically selects QLM3 when [QLM_MANUAL]\<3\>=0 and OCX_QLM3_CFG[SER_LOCAL]=0.
2493 _ LINK 3 automatically selects QLM4 when [QLM_MANUAL]\<4\>=0.
2494 _ LINK 3 automatically selects QLM5 when [QLM_MANUAL]\<5\>=0.
2495
2496 A link with [QLM_SELECT] = 0x0 is invalid and will never exchange traffic with the
2497 link partner. */
2498 uint64_t reserved_38_47 : 10;
2499 uint64_t qlm_manual : 6; /**< [ 53: 48](R/W/H) QLM manual mask, where each bit corresponds to a QLM. A link automatically selects a QLM
2500 unless either QLM_MANUAL[QLM] = 1 or a QLM is not eligible for the link.
2501
2502 _ QLM_MANUAL\<0\> = LNE(0..3) = QLM0.
2503 _ QLM_MANUAL\<1\> = LNE(7..4) = QLM1.
2504 _ QLM_MANUAL\<2\> = LNE(11..8) = QLM2.
2505 _ QLM_MANUAL\<3\> = LNE(15..12) = QLM3.
2506 _ QLM_MANUAL\<4\> = LNE(19..16) = QLM4.
2507 _ QLM_MANUAL\<5\> = LNE(23..23) = QLM5.
2508 _ LINK 0 may not select QLM4, QLM5.
2509 _ LINK 1 may not select QLM0, QLM1, QLM4, QLM5.
2510 _ LINK 2 may not select QLM0, QLM1.
2511
2512 During a cold reset, this field is initialized to 0x3F when OCI_SPD\<3:0\> == 0xF.
2513
2514 During a cold reset, this field is initialized to 0x0 when OCI_SPD\<3:0\> != 0xF.
2515
2516 This field is not modified by hardware at any other time.
2517
2518 This field is not affected by soft or warm reset. */
2519 uint64_t reserved_54_63 : 10;
2520 #endif /* Word 0 - End */
2521 } s;
2522 /* struct bdk_ocx_lnkx_cfg_s cn88xxp1; */
2523 struct bdk_ocx_lnkx_cfg_cn88xxp2
2524 {
2525 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2526 uint64_t reserved_54_63 : 10;
2527 uint64_t qlm_manual : 6; /**< [ 53: 48](R/W/H) QLM manual mask, where each bit corresponds to a QLM. A link automatically selects a QLM
2528 unless either QLM_MANUAL[QLM] = 1 or a QLM is not eligible for the link.
2529
2530 _ QLM_MANUAL\<0\> = LNE(0..3) = QLM0.
2531 _ QLM_MANUAL\<1\> = LNE(7..4) = QLM1.
2532 _ QLM_MANUAL\<2\> = LNE(11..8) = QLM2.
2533 _ QLM_MANUAL\<3\> = LNE(15..12) = QLM3.
2534 _ QLM_MANUAL\<4\> = LNE(19..16) = QLM4.
2535 _ QLM_MANUAL\<5\> = LNE(23..23) = QLM5.
2536 _ LINK 0 may not select QLM4, QLM5.
2537 _ LINK 1 may not select QLM0, QLM1, QLM4, QLM5.
2538 _ LINK 2 may not select QLM0, QLM1.
2539
2540 During a cold reset, this field is initialized to 0x3F when OCI_SPD\<3:0\> == 0xF.
2541
2542 During a cold reset, this field is initialized to 0x0 when OCI_SPD\<3:0\> != 0xF.
2543
2544 This field is not modified by hardware at any other time.
2545
2546 This field is not affected by soft or warm reset. */
2547 uint64_t reserved_38_47 : 10;
2548 uint64_t qlm_select : 6; /**< [ 37: 32](R/W/H) QLM select mask, where each bit corresponds to a QLM. A link will transmit/receive data
2549 using only the selected QLMs. A link is enabled if any QLM is selected. The same QLM
2550 should not be selected for multiple links.
2551 [LANE_REV] has no effect on this mapping.
2552
2553 _ QLM_SELECT\<0\> = LNE(0..3) = QLM0.
2554 _ QLM_SELECT\<1\> = LNE(7..4) = QLM1.
2555 _ QLM_SELECT\<2\> = LNE(11..8) = QLM2.
2556 _ QLM_SELECT\<3\> = LNE(15..12) = QLM3.
2557 _ QLM_SELECT\<4\> = LNE(19..16) = QLM4.
2558 _ QLM_SELECT\<5\> = LNE(23..23) = QLM5.
2559 _ LINK 0 may not select QLM4, QLM5.
2560 _ LINK 1 may not select QLM0, QLM1, QLM4, QLM5.
2561 _ LINK 2 may not select QLM0, QLM1.
2562 _ LINK 2 may not select QLM2 or QLM3 when LINK1 selects any QLM.
2563 _ LINK 0 may not select QLM2 or QLM3 when LINK1 selects any QLM.
2564 _ LINK 0 automatically selects QLM0 when [QLM_MANUAL]\<0\>=0.
2565 _ LINK 0 automatically selects QLM1 when [QLM_MANUAL]\<1\>=0.
2566 _ LINK 0 automatically selects QLM2 when [QLM_MANUAL]\<2\>=0 and OCX_QLM2_CFG[SER_LOCAL]=0.
2567 _ LINK 1 automatically selects QLM2 when [QLM_MANUAL]\<2\>=0 and OCX_QLM2_CFG[SER_LOCAL]=1.
2568 _ LINK 1 automatically selects QLM3 when [QLM_MANUAL]\<3\>=0 and OCX_QLM3_CFG[SER_LOCAL]=1.
2569 _ LINK 2 automatically selects QLM3 when [QLM_MANUAL]\<3\>=0 and OCX_QLM3_CFG[SER_LOCAL]=0.
2570 _ LINK 3 automatically selects QLM4 when [QLM_MANUAL]\<4\>=0.
2571 _ LINK 3 automatically selects QLM5 when [QLM_MANUAL]\<5\>=0.
2572
2573 A link with [QLM_SELECT] = 0x0 is invalid and will never exchange traffic with the
2574 link partner. */
2575 uint64_t reserved_29_31 : 3;
2576 uint64_t data_rate : 13; /**< [ 28: 16](R/W/H) The number of core-clock cycles (RCLKs) to transmit 32 words, where each word is
2577 67 bits. Hardware automatically calculates a conservative value for this
2578 field. Software can override the calculation by writing
2579 TX_DAT_RATE=roundup((67*RCLK / GBAUD)*32). */
2580 uint64_t low_delay : 6; /**< [ 15: 10](R/W) The delay before reacting to a lane low data indication, as a multiple of 64 core-clock
2581 cycles (RCLKs). */
2582 uint64_t lane_align_dis : 1; /**< [ 9: 9](R/W/H) Disable the RX lane alignment. */
2583 uint64_t lane_rev : 1; /**< [ 8: 8](R/W/H) RX lane reversal. When enabled, lane destriping is performed from the most significant
2584 lane enabled to least significant lane enabled [QLM_SELECT] must be 0x0 before changing
2585 [LANE_REV]. */
2586 uint64_t lane_rev_auto : 1; /**< [ 7: 7](R/W) Automatically detect RX lane reversal. When enabled, [LANE_REV] is updated by
2587 hardware. */
2588 uint64_t reserved_0_6 : 7;
2589 #else /* Word 0 - Little Endian */
2590 uint64_t reserved_0_6 : 7;
2591 uint64_t lane_rev_auto : 1; /**< [ 7: 7](R/W) Automatically detect RX lane reversal. When enabled, [LANE_REV] is updated by
2592 hardware. */
2593 uint64_t lane_rev : 1; /**< [ 8: 8](R/W/H) RX lane reversal. When enabled, lane destriping is performed from the most significant
2594 lane enabled to least significant lane enabled [QLM_SELECT] must be 0x0 before changing
2595 [LANE_REV]. */
2596 uint64_t lane_align_dis : 1; /**< [ 9: 9](R/W/H) Disable the RX lane alignment. */
2597 uint64_t low_delay : 6; /**< [ 15: 10](R/W) The delay before reacting to a lane low data indication, as a multiple of 64 core-clock
2598 cycles (RCLKs). */
2599 uint64_t data_rate : 13; /**< [ 28: 16](R/W/H) The number of core-clock cycles (RCLKs) to transmit 32 words, where each word is
2600 67 bits. Hardware automatically calculates a conservative value for this
2601 field. Software can override the calculation by writing
2602 TX_DAT_RATE=roundup((67*RCLK / GBAUD)*32). */
2603 uint64_t reserved_29_31 : 3;
2604 uint64_t qlm_select : 6; /**< [ 37: 32](R/W/H) QLM select mask, where each bit corresponds to a QLM. A link will transmit/receive data
2605 using only the selected QLMs. A link is enabled if any QLM is selected. The same QLM
2606 should not be selected for multiple links.
2607 [LANE_REV] has no effect on this mapping.
2608
2609 _ QLM_SELECT\<0\> = LNE(0..3) = QLM0.
2610 _ QLM_SELECT\<1\> = LNE(7..4) = QLM1.
2611 _ QLM_SELECT\<2\> = LNE(11..8) = QLM2.
2612 _ QLM_SELECT\<3\> = LNE(15..12) = QLM3.
2613 _ QLM_SELECT\<4\> = LNE(19..16) = QLM4.
2614 _ QLM_SELECT\<5\> = LNE(23..23) = QLM5.
2615 _ LINK 0 may not select QLM4, QLM5.
2616 _ LINK 1 may not select QLM0, QLM1, QLM4, QLM5.
2617 _ LINK 2 may not select QLM0, QLM1.
2618 _ LINK 2 may not select QLM2 or QLM3 when LINK1 selects any QLM.
2619 _ LINK 0 may not select QLM2 or QLM3 when LINK1 selects any QLM.
2620 _ LINK 0 automatically selects QLM0 when [QLM_MANUAL]\<0\>=0.
2621 _ LINK 0 automatically selects QLM1 when [QLM_MANUAL]\<1\>=0.
2622 _ LINK 0 automatically selects QLM2 when [QLM_MANUAL]\<2\>=0 and OCX_QLM2_CFG[SER_LOCAL]=0.
2623 _ LINK 1 automatically selects QLM2 when [QLM_MANUAL]\<2\>=0 and OCX_QLM2_CFG[SER_LOCAL]=1.
2624 _ LINK 1 automatically selects QLM3 when [QLM_MANUAL]\<3\>=0 and OCX_QLM3_CFG[SER_LOCAL]=1.
2625 _ LINK 2 automatically selects QLM3 when [QLM_MANUAL]\<3\>=0 and OCX_QLM3_CFG[SER_LOCAL]=0.
2626 _ LINK 3 automatically selects QLM4 when [QLM_MANUAL]\<4\>=0.
2627 _ LINK 3 automatically selects QLM5 when [QLM_MANUAL]\<5\>=0.
2628
2629 A link with [QLM_SELECT] = 0x0 is invalid and will never exchange traffic with the
2630 link partner. */
2631 uint64_t reserved_38_47 : 10;
2632 uint64_t qlm_manual : 6; /**< [ 53: 48](R/W/H) QLM manual mask, where each bit corresponds to a QLM. A link automatically selects a QLM
2633 unless either QLM_MANUAL[QLM] = 1 or a QLM is not eligible for the link.
2634
2635 _ QLM_MANUAL\<0\> = LNE(0..3) = QLM0.
2636 _ QLM_MANUAL\<1\> = LNE(7..4) = QLM1.
2637 _ QLM_MANUAL\<2\> = LNE(11..8) = QLM2.
2638 _ QLM_MANUAL\<3\> = LNE(15..12) = QLM3.
2639 _ QLM_MANUAL\<4\> = LNE(19..16) = QLM4.
2640 _ QLM_MANUAL\<5\> = LNE(23..23) = QLM5.
2641 _ LINK 0 may not select QLM4, QLM5.
2642 _ LINK 1 may not select QLM0, QLM1, QLM4, QLM5.
2643 _ LINK 2 may not select QLM0, QLM1.
2644
2645 During a cold reset, this field is initialized to 0x3F when OCI_SPD\<3:0\> == 0xF.
2646
2647 During a cold reset, this field is initialized to 0x0 when OCI_SPD\<3:0\> != 0xF.
2648
2649 This field is not modified by hardware at any other time.
2650
2651 This field is not affected by soft or warm reset. */
2652 uint64_t reserved_54_63 : 10;
2653 #endif /* Word 0 - End */
2654 } cn88xxp2;
2655 };
2656 typedef union bdk_ocx_lnkx_cfg bdk_ocx_lnkx_cfg_t;
2657
2658 static inline uint64_t BDK_OCX_LNKX_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_LNKX_CFG(unsigned long a)2659 static inline uint64_t BDK_OCX_LNKX_CFG(unsigned long a)
2660 {
2661 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
2662 return 0x87e01100f900ll + 8ll * ((a) & 0x3);
2663 __bdk_csr_fatal("OCX_LNKX_CFG", 1, a, 0, 0, 0);
2664 }
2665
2666 #define typedef_BDK_OCX_LNKX_CFG(a) bdk_ocx_lnkx_cfg_t
2667 #define bustype_BDK_OCX_LNKX_CFG(a) BDK_CSR_TYPE_RSL
2668 #define basename_BDK_OCX_LNKX_CFG(a) "OCX_LNKX_CFG"
2669 #define device_bar_BDK_OCX_LNKX_CFG(a) 0x0 /* PF_BAR0 */
2670 #define busnum_BDK_OCX_LNKX_CFG(a) (a)
2671 #define arguments_BDK_OCX_LNKX_CFG(a) (a),-1,-1,-1
2672
2673 /**
2674 * Register (RSL) ocx_msix_pba#
2675 *
2676 * OCX MSI-X Pending Bit Array Register
2677 * This register is the MSI-X PBA table; the bit number is indexed by the OCX_INT_VEC_E
2678 * enumeration.
2679 */
2680 union bdk_ocx_msix_pbax
2681 {
2682 uint64_t u;
2683 struct bdk_ocx_msix_pbax_s
2684 {
2685 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2686 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for the associated OCX_MSIX_VEC()_CTL, enumerated by
2687 OCX_INT_VEC_E. Bits that have no associated OCX_INT_VEC_E are 0. */
2688 #else /* Word 0 - Little Endian */
2689 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for the associated OCX_MSIX_VEC()_CTL, enumerated by
2690 OCX_INT_VEC_E. Bits that have no associated OCX_INT_VEC_E are 0. */
2691 #endif /* Word 0 - End */
2692 } s;
2693 /* struct bdk_ocx_msix_pbax_s cn; */
2694 };
2695 typedef union bdk_ocx_msix_pbax bdk_ocx_msix_pbax_t;
2696
2697 static inline uint64_t BDK_OCX_MSIX_PBAX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_MSIX_PBAX(unsigned long a)2698 static inline uint64_t BDK_OCX_MSIX_PBAX(unsigned long a)
2699 {
2700 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a==0))
2701 return 0x87e011ff0000ll + 8ll * ((a) & 0x0);
2702 __bdk_csr_fatal("OCX_MSIX_PBAX", 1, a, 0, 0, 0);
2703 }
2704
2705 #define typedef_BDK_OCX_MSIX_PBAX(a) bdk_ocx_msix_pbax_t
2706 #define bustype_BDK_OCX_MSIX_PBAX(a) BDK_CSR_TYPE_RSL
2707 #define basename_BDK_OCX_MSIX_PBAX(a) "OCX_MSIX_PBAX"
2708 #define device_bar_BDK_OCX_MSIX_PBAX(a) 0x4 /* PF_BAR4 */
2709 #define busnum_BDK_OCX_MSIX_PBAX(a) (a)
2710 #define arguments_BDK_OCX_MSIX_PBAX(a) (a),-1,-1,-1
2711
2712 /**
2713 * Register (RSL) ocx_msix_vec#_addr
2714 *
2715 * OCX MSI-X Vector-Table Address Registers
2716 * This register is the MSI-X vector table, indexed by the OCX_INT_VEC_E enumeration.
2717 */
2718 union bdk_ocx_msix_vecx_addr
2719 {
2720 uint64_t u;
2721 struct bdk_ocx_msix_vecx_addr_s
2722 {
2723 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2724 uint64_t reserved_49_63 : 15;
2725 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
2726 uint64_t reserved_1 : 1;
2727 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
2728 0 = This vector may be read or written by either secure or nonsecure states.
2729 1 = This vector's OCX_MSIX_VEC()_ADDR, OCX_MSIX_VEC()_CTL, and
2730 corresponding bit of OCX_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
2731 by the nonsecure world.
2732
2733 If PCCPF_OCX_VSEC_SCTL[MSIX_SEC] (for documentation, see
2734 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) =
2735 1, all vectors are secure and function as if [SECVEC] was set. */
2736 #else /* Word 0 - Little Endian */
2737 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
2738 0 = This vector may be read or written by either secure or nonsecure states.
2739 1 = This vector's OCX_MSIX_VEC()_ADDR, OCX_MSIX_VEC()_CTL, and
2740 corresponding bit of OCX_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
2741 by the nonsecure world.
2742
2743 If PCCPF_OCX_VSEC_SCTL[MSIX_SEC] (for documentation, see
2744 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) =
2745 1, all vectors are secure and function as if [SECVEC] was set. */
2746 uint64_t reserved_1 : 1;
2747 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
2748 uint64_t reserved_49_63 : 15;
2749 #endif /* Word 0 - End */
2750 } s;
2751 /* struct bdk_ocx_msix_vecx_addr_s cn; */
2752 };
2753 typedef union bdk_ocx_msix_vecx_addr bdk_ocx_msix_vecx_addr_t;
2754
2755 static inline uint64_t BDK_OCX_MSIX_VECX_ADDR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_MSIX_VECX_ADDR(unsigned long a)2756 static inline uint64_t BDK_OCX_MSIX_VECX_ADDR(unsigned long a)
2757 {
2758 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=3))
2759 return 0x87e011f00000ll + 0x10ll * ((a) & 0x3);
2760 __bdk_csr_fatal("OCX_MSIX_VECX_ADDR", 1, a, 0, 0, 0);
2761 }
2762
2763 #define typedef_BDK_OCX_MSIX_VECX_ADDR(a) bdk_ocx_msix_vecx_addr_t
2764 #define bustype_BDK_OCX_MSIX_VECX_ADDR(a) BDK_CSR_TYPE_RSL
2765 #define basename_BDK_OCX_MSIX_VECX_ADDR(a) "OCX_MSIX_VECX_ADDR"
2766 #define device_bar_BDK_OCX_MSIX_VECX_ADDR(a) 0x4 /* PF_BAR4 */
2767 #define busnum_BDK_OCX_MSIX_VECX_ADDR(a) (a)
2768 #define arguments_BDK_OCX_MSIX_VECX_ADDR(a) (a),-1,-1,-1
2769
2770 /**
2771 * Register (RSL) ocx_msix_vec#_ctl
2772 *
2773 * OCX MSI-X Vector-Table Control and Data Registers
2774 * This register is the MSI-X vector table, indexed by the OCX_INT_VEC_E enumeration.
2775 */
2776 union bdk_ocx_msix_vecx_ctl
2777 {
2778 uint64_t u;
2779 struct bdk_ocx_msix_vecx_ctl_s
2780 {
2781 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2782 uint64_t reserved_33_63 : 31;
2783 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
2784 uint64_t reserved_20_31 : 12;
2785 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
2786 #else /* Word 0 - Little Endian */
2787 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
2788 uint64_t reserved_20_31 : 12;
2789 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
2790 uint64_t reserved_33_63 : 31;
2791 #endif /* Word 0 - End */
2792 } s;
2793 /* struct bdk_ocx_msix_vecx_ctl_s cn; */
2794 };
2795 typedef union bdk_ocx_msix_vecx_ctl bdk_ocx_msix_vecx_ctl_t;
2796
2797 static inline uint64_t BDK_OCX_MSIX_VECX_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_MSIX_VECX_CTL(unsigned long a)2798 static inline uint64_t BDK_OCX_MSIX_VECX_CTL(unsigned long a)
2799 {
2800 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=3))
2801 return 0x87e011f00008ll + 0x10ll * ((a) & 0x3);
2802 __bdk_csr_fatal("OCX_MSIX_VECX_CTL", 1, a, 0, 0, 0);
2803 }
2804
2805 #define typedef_BDK_OCX_MSIX_VECX_CTL(a) bdk_ocx_msix_vecx_ctl_t
2806 #define bustype_BDK_OCX_MSIX_VECX_CTL(a) BDK_CSR_TYPE_RSL
2807 #define basename_BDK_OCX_MSIX_VECX_CTL(a) "OCX_MSIX_VECX_CTL"
2808 #define device_bar_BDK_OCX_MSIX_VECX_CTL(a) 0x4 /* PF_BAR4 */
2809 #define busnum_BDK_OCX_MSIX_VECX_CTL(a) (a)
2810 #define arguments_BDK_OCX_MSIX_VECX_CTL(a) (a),-1,-1,-1
2811
2812 /**
2813 * Register (RSL) ocx_pp_cmd
2814 *
2815 * OCX Core Address Register
2816 * Contains the address, read size and write mask to used for the core operation. Write data
2817 * should be written first and placed in the OCX_PP_WR_DATA register. Writing this register
2818 * starts the operation. A second write to this register while an operation is in progress will
2819 * stall. Data is placed in the OCX_PP_RD_DATA register.
2820 * This register has the same bit fields as OCX_WIN_CMD.
2821 */
2822 union bdk_ocx_pp_cmd
2823 {
2824 uint64_t u;
2825 struct bdk_ocx_pp_cmd_s
2826 {
2827 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2828 uint64_t wr_mask : 8; /**< [ 63: 56](R/W) Mask for the data to be written. When a bit is 1, the corresponding byte will be written.
2829 The values of this field must be contiguous and for 1, 2, 4, or 8 byte operations and
2830 aligned to operation size. A value of 0 will produce unpredictable results. Field is
2831 ignored during a read (LD_OP=1). */
2832 uint64_t reserved_54_55 : 2;
2833 uint64_t el : 2; /**< [ 53: 52](R/W) Execution level. This field is used to supply the execution level of the generated load
2834 or store command. */
2835 uint64_t nsecure : 1; /**< [ 51: 51](R/W) Nonsecure mode. Setting this bit causes the generated load or store command to be
2836 considered nonsecure. */
2837 uint64_t ld_cmd : 2; /**< [ 50: 49](R/W) The load command sent with the read:
2838 0x0 = Load 1-bytes.
2839 0x1 = Load 2-bytes.
2840 0x2 = Load 4-bytes.
2841 0x3 = Load 8-bytes. */
2842 uint64_t ld_op : 1; /**< [ 48: 48](R/W) Operation type:
2843 0 = Store.
2844 1 = Load operation. */
2845 uint64_t addr : 48; /**< [ 47: 0](R/W) The address used in both the load and store operations:
2846 \<47:46\> = Reserved.
2847 \<45:44\> = CCPI_ID.
2848 \<43:36\> = NCB_ID.
2849 \<35:0\> = Address.
2850
2851 When \<43:36\> NCB_ID is RSL (0x7E) address field is defined as:
2852 \<47:46\> = Reserved.
2853 \<45:44\> = CCPI_ID.
2854 \<43:36\> = 0x7E.
2855 \<35:32\> = Reserved.
2856 \<31:24\> = RSL_ID.
2857 \<23:0\> = RSL register offset.
2858
2859 \<2:0\> are ignored in a store operation. */
2860 #else /* Word 0 - Little Endian */
2861 uint64_t addr : 48; /**< [ 47: 0](R/W) The address used in both the load and store operations:
2862 \<47:46\> = Reserved.
2863 \<45:44\> = CCPI_ID.
2864 \<43:36\> = NCB_ID.
2865 \<35:0\> = Address.
2866
2867 When \<43:36\> NCB_ID is RSL (0x7E) address field is defined as:
2868 \<47:46\> = Reserved.
2869 \<45:44\> = CCPI_ID.
2870 \<43:36\> = 0x7E.
2871 \<35:32\> = Reserved.
2872 \<31:24\> = RSL_ID.
2873 \<23:0\> = RSL register offset.
2874
2875 \<2:0\> are ignored in a store operation. */
2876 uint64_t ld_op : 1; /**< [ 48: 48](R/W) Operation type:
2877 0 = Store.
2878 1 = Load operation. */
2879 uint64_t ld_cmd : 2; /**< [ 50: 49](R/W) The load command sent with the read:
2880 0x0 = Load 1-bytes.
2881 0x1 = Load 2-bytes.
2882 0x2 = Load 4-bytes.
2883 0x3 = Load 8-bytes. */
2884 uint64_t nsecure : 1; /**< [ 51: 51](R/W) Nonsecure mode. Setting this bit causes the generated load or store command to be
2885 considered nonsecure. */
2886 uint64_t el : 2; /**< [ 53: 52](R/W) Execution level. This field is used to supply the execution level of the generated load
2887 or store command. */
2888 uint64_t reserved_54_55 : 2;
2889 uint64_t wr_mask : 8; /**< [ 63: 56](R/W) Mask for the data to be written. When a bit is 1, the corresponding byte will be written.
2890 The values of this field must be contiguous and for 1, 2, 4, or 8 byte operations and
2891 aligned to operation size. A value of 0 will produce unpredictable results. Field is
2892 ignored during a read (LD_OP=1). */
2893 #endif /* Word 0 - End */
2894 } s;
2895 /* struct bdk_ocx_pp_cmd_s cn; */
2896 };
2897 typedef union bdk_ocx_pp_cmd bdk_ocx_pp_cmd_t;
2898
2899 #define BDK_OCX_PP_CMD BDK_OCX_PP_CMD_FUNC()
2900 static inline uint64_t BDK_OCX_PP_CMD_FUNC(void) __attribute__ ((pure, always_inline));
BDK_OCX_PP_CMD_FUNC(void)2901 static inline uint64_t BDK_OCX_PP_CMD_FUNC(void)
2902 {
2903 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX))
2904 return 0x87e0110000c8ll;
2905 __bdk_csr_fatal("OCX_PP_CMD", 0, 0, 0, 0, 0);
2906 }
2907
2908 #define typedef_BDK_OCX_PP_CMD bdk_ocx_pp_cmd_t
2909 #define bustype_BDK_OCX_PP_CMD BDK_CSR_TYPE_RSL
2910 #define basename_BDK_OCX_PP_CMD "OCX_PP_CMD"
2911 #define device_bar_BDK_OCX_PP_CMD 0x0 /* PF_BAR0 */
2912 #define busnum_BDK_OCX_PP_CMD 0
2913 #define arguments_BDK_OCX_PP_CMD -1,-1,-1,-1
2914
2915 /**
2916 * Register (RSL) ocx_pp_rd_data
2917 *
2918 * OCX Core Read Data Register
2919 * This register is the read response data associated with core command. Reads all-ones until
2920 * response is received.
2921 * This register has the same bit fields as OCX_WIN_RD_DATA.
2922 */
2923 union bdk_ocx_pp_rd_data
2924 {
2925 uint64_t u;
2926 struct bdk_ocx_pp_rd_data_s
2927 {
2928 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2929 uint64_t data : 64; /**< [ 63: 0](RO/H) Read response data. */
2930 #else /* Word 0 - Little Endian */
2931 uint64_t data : 64; /**< [ 63: 0](RO/H) Read response data. */
2932 #endif /* Word 0 - End */
2933 } s;
2934 /* struct bdk_ocx_pp_rd_data_s cn; */
2935 };
2936 typedef union bdk_ocx_pp_rd_data bdk_ocx_pp_rd_data_t;
2937
2938 #define BDK_OCX_PP_RD_DATA BDK_OCX_PP_RD_DATA_FUNC()
2939 static inline uint64_t BDK_OCX_PP_RD_DATA_FUNC(void) __attribute__ ((pure, always_inline));
BDK_OCX_PP_RD_DATA_FUNC(void)2940 static inline uint64_t BDK_OCX_PP_RD_DATA_FUNC(void)
2941 {
2942 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX))
2943 return 0x87e0110000d0ll;
2944 __bdk_csr_fatal("OCX_PP_RD_DATA", 0, 0, 0, 0, 0);
2945 }
2946
2947 #define typedef_BDK_OCX_PP_RD_DATA bdk_ocx_pp_rd_data_t
2948 #define bustype_BDK_OCX_PP_RD_DATA BDK_CSR_TYPE_RSL
2949 #define basename_BDK_OCX_PP_RD_DATA "OCX_PP_RD_DATA"
2950 #define device_bar_BDK_OCX_PP_RD_DATA 0x0 /* PF_BAR0 */
2951 #define busnum_BDK_OCX_PP_RD_DATA 0
2952 #define arguments_BDK_OCX_PP_RD_DATA -1,-1,-1,-1
2953
2954 /**
2955 * Register (RSL) ocx_pp_wr_data
2956 *
2957 * OCX Core Data Register
2958 * Contains the data to write to the address located in OCX_PP_CMD. Writing this register will
2959 * cause a write operation to take place.
2960 * This register has the same bit fields as OCX_WIN_WR_DATA.
2961 */
2962 union bdk_ocx_pp_wr_data
2963 {
2964 uint64_t u;
2965 struct bdk_ocx_pp_wr_data_s
2966 {
2967 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2968 uint64_t wr_data : 64; /**< [ 63: 0](R/W) The data to be written. */
2969 #else /* Word 0 - Little Endian */
2970 uint64_t wr_data : 64; /**< [ 63: 0](R/W) The data to be written. */
2971 #endif /* Word 0 - End */
2972 } s;
2973 /* struct bdk_ocx_pp_wr_data_s cn; */
2974 };
2975 typedef union bdk_ocx_pp_wr_data bdk_ocx_pp_wr_data_t;
2976
2977 #define BDK_OCX_PP_WR_DATA BDK_OCX_PP_WR_DATA_FUNC()
2978 static inline uint64_t BDK_OCX_PP_WR_DATA_FUNC(void) __attribute__ ((pure, always_inline));
BDK_OCX_PP_WR_DATA_FUNC(void)2979 static inline uint64_t BDK_OCX_PP_WR_DATA_FUNC(void)
2980 {
2981 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX))
2982 return 0x87e0110000c0ll;
2983 __bdk_csr_fatal("OCX_PP_WR_DATA", 0, 0, 0, 0, 0);
2984 }
2985
2986 #define typedef_BDK_OCX_PP_WR_DATA bdk_ocx_pp_wr_data_t
2987 #define bustype_BDK_OCX_PP_WR_DATA BDK_CSR_TYPE_RSL
2988 #define basename_BDK_OCX_PP_WR_DATA "OCX_PP_WR_DATA"
2989 #define device_bar_BDK_OCX_PP_WR_DATA 0x0 /* PF_BAR0 */
2990 #define busnum_BDK_OCX_PP_WR_DATA 0
2991 #define arguments_BDK_OCX_PP_WR_DATA -1,-1,-1,-1
2992
2993 /**
2994 * Register (RSL) ocx_qlm#_cfg
2995 *
2996 * OCX QLM 0-5 Configuration Registers
2997 */
2998 union bdk_ocx_qlmx_cfg
2999 {
3000 uint64_t u;
3001 struct bdk_ocx_qlmx_cfg_s
3002 {
3003 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3004 uint64_t ser_low : 4; /**< [ 63: 60](R/W/H) Reduce latency by limiting the amount of data in flight for each SerDes. Writing to 0
3005 causes hardware to determine a typically optimal value. */
3006 uint64_t reserved_42_59 : 18;
3007 uint64_t ser_limit : 10; /**< [ 41: 32](RAZ) Reserved. */
3008 uint64_t crd_dis : 1; /**< [ 31: 31](R/W) For diagnostic use only. */
3009 uint64_t reserved_27_30 : 4;
3010 uint64_t trn_rxeq_only : 1; /**< [ 26: 26](R/W/H) Shortened training sequence. Initialized to 1 during cold reset when OCI_SPD\<3:0\> pins
3011 indicate 5 GBAUD \<=speed \< 8 GBAUD. Otherwise, initialized to 0 during a cold reset. This
3012 field is not affected by soft or warm reset. For diagnostic use only. */
3013 uint64_t timer_dis : 1; /**< [ 25: 25](R/W/H) Disable bad lane timer. A timer counts core clocks (RCLKs) when any enabled lane is not
3014 ready, i.e. not in the scrambler sync state. If this timer expires before all enabled
3015 lanes can be made ready, then any lane which is not ready is disabled via
3016 OCX_QLM(0..5)_CFG[SER_LANE_BAD]. This field is not affected by soft or warm reset. */
3017 uint64_t trn_ena : 1; /**< [ 24: 24](R/W/H) Link training enable. Link training is performed during auto link bring up. Initialized to
3018 1 during cold reset when OCI_SPD\<3:0\> pins indicate speed \>= 5 GBAUD. Otherwise,
3019 initialized to 0 during a cold reset. This field is not affected by soft or warm reset. */
3020 uint64_t ser_lane_ready : 4; /**< [ 23: 20](R/W/H) SerDes lanes that are ready for bundling into the link. */
3021 uint64_t ser_lane_bad : 4; /**< [ 19: 16](R/W/H) SerDes lanes excluded from use. */
3022 uint64_t reserved_7_15 : 9;
3023 uint64_t ser_lane_rev : 1; /**< [ 6: 6](RO/H) SerDes lane reversal has been detected. */
3024 uint64_t ser_rxpol_auto : 1; /**< [ 5: 5](R/W) SerDes lane receive polarity auto detection mode. */
3025 uint64_t ser_rxpol : 1; /**< [ 4: 4](R/W) SerDes lane receive polarity:
3026 0 = RX without inversion.
3027 1 = RX with inversion. */
3028 uint64_t ser_txpol : 1; /**< [ 3: 3](R/W) SerDes lane transmit polarity:
3029 0 = TX without inversion.
3030 1 = TX with inversion. */
3031 uint64_t reserved_1_2 : 2;
3032 uint64_t ser_local : 1; /**< [ 0: 0](R/W/H) Auto initialization may set OCX_LNK0_CFG[QLM_SELECT\<2\>] = 1 only if
3033 OCX_QLM2_CFG[SER_LOCAL] = 0.
3034 Auto initialization may set OCX_LNK1_CFG[QLM_SELECT\<2\>] = 1 only if
3035 OCX_QLM2_CFG[SER_LOCAL] = 1.
3036 Auto initialization may set OCX_LNK1_CFG[QLM_SELECT\<3\>] = 1 only if
3037 OCX_QLM3_CFG[SER_LOCAL] = 1.
3038 Auto initialization may set OCX_LNK2_CFG[QLM_SELECT\<3\>] = 1 only if
3039 OCX_QLM3_CFG[SER_LOCAL] = 0.
3040
3041 QLM0/1 can only participate in LNK0; therefore
3042 OCX_QLM0/1_CFG[SER_LOCAL] has no effect.
3043 QLM4/5 can only participate in LNK2; therefore
3044 OCX_QLM4/5_CFG[SER_LOCAL] has no effect.
3045
3046 During a cold reset, initialized as follows:
3047 _ OCX_QLM2_CFG[SER_LOCAL] = pi_oci2_link1.
3048 _ OCX_QLM3_CFG[SER_LOCAL] = pi_oci3_link1.
3049
3050 The combo of pi_oci2_link1=1 and pi_oci3_link1=0 is illegal.
3051
3052 The combo of OCX_QLM2_CFG[SER_LOCAL]=1 and OCX_QLM3_CFG[SER_LOCAL] = 0 is illegal. */
3053 #else /* Word 0 - Little Endian */
3054 uint64_t ser_local : 1; /**< [ 0: 0](R/W/H) Auto initialization may set OCX_LNK0_CFG[QLM_SELECT\<2\>] = 1 only if
3055 OCX_QLM2_CFG[SER_LOCAL] = 0.
3056 Auto initialization may set OCX_LNK1_CFG[QLM_SELECT\<2\>] = 1 only if
3057 OCX_QLM2_CFG[SER_LOCAL] = 1.
3058 Auto initialization may set OCX_LNK1_CFG[QLM_SELECT\<3\>] = 1 only if
3059 OCX_QLM3_CFG[SER_LOCAL] = 1.
3060 Auto initialization may set OCX_LNK2_CFG[QLM_SELECT\<3\>] = 1 only if
3061 OCX_QLM3_CFG[SER_LOCAL] = 0.
3062
3063 QLM0/1 can only participate in LNK0; therefore
3064 OCX_QLM0/1_CFG[SER_LOCAL] has no effect.
3065 QLM4/5 can only participate in LNK2; therefore
3066 OCX_QLM4/5_CFG[SER_LOCAL] has no effect.
3067
3068 During a cold reset, initialized as follows:
3069 _ OCX_QLM2_CFG[SER_LOCAL] = pi_oci2_link1.
3070 _ OCX_QLM3_CFG[SER_LOCAL] = pi_oci3_link1.
3071
3072 The combo of pi_oci2_link1=1 and pi_oci3_link1=0 is illegal.
3073
3074 The combo of OCX_QLM2_CFG[SER_LOCAL]=1 and OCX_QLM3_CFG[SER_LOCAL] = 0 is illegal. */
3075 uint64_t reserved_1_2 : 2;
3076 uint64_t ser_txpol : 1; /**< [ 3: 3](R/W) SerDes lane transmit polarity:
3077 0 = TX without inversion.
3078 1 = TX with inversion. */
3079 uint64_t ser_rxpol : 1; /**< [ 4: 4](R/W) SerDes lane receive polarity:
3080 0 = RX without inversion.
3081 1 = RX with inversion. */
3082 uint64_t ser_rxpol_auto : 1; /**< [ 5: 5](R/W) SerDes lane receive polarity auto detection mode. */
3083 uint64_t ser_lane_rev : 1; /**< [ 6: 6](RO/H) SerDes lane reversal has been detected. */
3084 uint64_t reserved_7_15 : 9;
3085 uint64_t ser_lane_bad : 4; /**< [ 19: 16](R/W/H) SerDes lanes excluded from use. */
3086 uint64_t ser_lane_ready : 4; /**< [ 23: 20](R/W/H) SerDes lanes that are ready for bundling into the link. */
3087 uint64_t trn_ena : 1; /**< [ 24: 24](R/W/H) Link training enable. Link training is performed during auto link bring up. Initialized to
3088 1 during cold reset when OCI_SPD\<3:0\> pins indicate speed \>= 5 GBAUD. Otherwise,
3089 initialized to 0 during a cold reset. This field is not affected by soft or warm reset. */
3090 uint64_t timer_dis : 1; /**< [ 25: 25](R/W/H) Disable bad lane timer. A timer counts core clocks (RCLKs) when any enabled lane is not
3091 ready, i.e. not in the scrambler sync state. If this timer expires before all enabled
3092 lanes can be made ready, then any lane which is not ready is disabled via
3093 OCX_QLM(0..5)_CFG[SER_LANE_BAD]. This field is not affected by soft or warm reset. */
3094 uint64_t trn_rxeq_only : 1; /**< [ 26: 26](R/W/H) Shortened training sequence. Initialized to 1 during cold reset when OCI_SPD\<3:0\> pins
3095 indicate 5 GBAUD \<=speed \< 8 GBAUD. Otherwise, initialized to 0 during a cold reset. This
3096 field is not affected by soft or warm reset. For diagnostic use only. */
3097 uint64_t reserved_27_30 : 4;
3098 uint64_t crd_dis : 1; /**< [ 31: 31](R/W) For diagnostic use only. */
3099 uint64_t ser_limit : 10; /**< [ 41: 32](RAZ) Reserved. */
3100 uint64_t reserved_42_59 : 18;
3101 uint64_t ser_low : 4; /**< [ 63: 60](R/W/H) Reduce latency by limiting the amount of data in flight for each SerDes. Writing to 0
3102 causes hardware to determine a typically optimal value. */
3103 #endif /* Word 0 - End */
3104 } s;
3105 /* struct bdk_ocx_qlmx_cfg_s cn; */
3106 };
3107 typedef union bdk_ocx_qlmx_cfg bdk_ocx_qlmx_cfg_t;
3108
3109 static inline uint64_t BDK_OCX_QLMX_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_QLMX_CFG(unsigned long a)3110 static inline uint64_t BDK_OCX_QLMX_CFG(unsigned long a)
3111 {
3112 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=5))
3113 return 0x87e01100f800ll + 8ll * ((a) & 0x7);
3114 __bdk_csr_fatal("OCX_QLMX_CFG", 1, a, 0, 0, 0);
3115 }
3116
3117 #define typedef_BDK_OCX_QLMX_CFG(a) bdk_ocx_qlmx_cfg_t
3118 #define bustype_BDK_OCX_QLMX_CFG(a) BDK_CSR_TYPE_RSL
3119 #define basename_BDK_OCX_QLMX_CFG(a) "OCX_QLMX_CFG"
3120 #define device_bar_BDK_OCX_QLMX_CFG(a) 0x0 /* PF_BAR0 */
3121 #define busnum_BDK_OCX_QLMX_CFG(a) (a)
3122 #define arguments_BDK_OCX_QLMX_CFG(a) (a),-1,-1,-1
3123
3124 /**
3125 * Register (RSL) ocx_rlk#_align
3126 *
3127 * OCX Receive Link Align Registers
3128 */
3129 union bdk_ocx_rlkx_align
3130 {
3131 uint64_t u;
3132 struct bdk_ocx_rlkx_align_s
3133 {
3134 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3135 uint64_t bad_cnt : 32; /**< [ 63: 32](R/W/H) Number of alignment sequences received in error (i.e. those that violate the current
3136 alignment). Count saturates at max value. */
3137 uint64_t good_cnt : 32; /**< [ 31: 0](R/W/H) Number of alignment sequences received (i.e. those that do not violate the current
3138 alignment). Count saturates at max value. */
3139 #else /* Word 0 - Little Endian */
3140 uint64_t good_cnt : 32; /**< [ 31: 0](R/W/H) Number of alignment sequences received (i.e. those that do not violate the current
3141 alignment). Count saturates at max value. */
3142 uint64_t bad_cnt : 32; /**< [ 63: 32](R/W/H) Number of alignment sequences received in error (i.e. those that violate the current
3143 alignment). Count saturates at max value. */
3144 #endif /* Word 0 - End */
3145 } s;
3146 /* struct bdk_ocx_rlkx_align_s cn; */
3147 };
3148 typedef union bdk_ocx_rlkx_align bdk_ocx_rlkx_align_t;
3149
3150 static inline uint64_t BDK_OCX_RLKX_ALIGN(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_RLKX_ALIGN(unsigned long a)3151 static inline uint64_t BDK_OCX_RLKX_ALIGN(unsigned long a)
3152 {
3153 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
3154 return 0x87e011018060ll + 0x2000ll * ((a) & 0x3);
3155 __bdk_csr_fatal("OCX_RLKX_ALIGN", 1, a, 0, 0, 0);
3156 }
3157
3158 #define typedef_BDK_OCX_RLKX_ALIGN(a) bdk_ocx_rlkx_align_t
3159 #define bustype_BDK_OCX_RLKX_ALIGN(a) BDK_CSR_TYPE_RSL
3160 #define basename_BDK_OCX_RLKX_ALIGN(a) "OCX_RLKX_ALIGN"
3161 #define device_bar_BDK_OCX_RLKX_ALIGN(a) 0x0 /* PF_BAR0 */
3162 #define busnum_BDK_OCX_RLKX_ALIGN(a) (a)
3163 #define arguments_BDK_OCX_RLKX_ALIGN(a) (a),-1,-1,-1
3164
3165 /**
3166 * Register (RSL) ocx_rlk#_blk_err
3167 *
3168 * OCX Receive Link Block Error Registers
3169 */
3170 union bdk_ocx_rlkx_blk_err
3171 {
3172 uint64_t u;
3173 struct bdk_ocx_rlkx_blk_err_s
3174 {
3175 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3176 uint64_t reserved_32_63 : 32;
3177 uint64_t limit : 16; /**< [ 31: 16](R/W) Contains the number of blocks received with errors before the
3178 OCX_COM_LINK()_INT[BLK_ERR] interrupt is generated. */
3179 uint64_t count : 16; /**< [ 15: 0](R/W) Shows the number of blocks received with one or more errors detected. Multiple
3180 errors may be detected as the link starts up. */
3181 #else /* Word 0 - Little Endian */
3182 uint64_t count : 16; /**< [ 15: 0](R/W) Shows the number of blocks received with one or more errors detected. Multiple
3183 errors may be detected as the link starts up. */
3184 uint64_t limit : 16; /**< [ 31: 16](R/W) Contains the number of blocks received with errors before the
3185 OCX_COM_LINK()_INT[BLK_ERR] interrupt is generated. */
3186 uint64_t reserved_32_63 : 32;
3187 #endif /* Word 0 - End */
3188 } s;
3189 /* struct bdk_ocx_rlkx_blk_err_s cn; */
3190 };
3191 typedef union bdk_ocx_rlkx_blk_err bdk_ocx_rlkx_blk_err_t;
3192
3193 static inline uint64_t BDK_OCX_RLKX_BLK_ERR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_RLKX_BLK_ERR(unsigned long a)3194 static inline uint64_t BDK_OCX_RLKX_BLK_ERR(unsigned long a)
3195 {
3196 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
3197 return 0x87e011018050ll + 0x2000ll * ((a) & 0x3);
3198 __bdk_csr_fatal("OCX_RLKX_BLK_ERR", 1, a, 0, 0, 0);
3199 }
3200
3201 #define typedef_BDK_OCX_RLKX_BLK_ERR(a) bdk_ocx_rlkx_blk_err_t
3202 #define bustype_BDK_OCX_RLKX_BLK_ERR(a) BDK_CSR_TYPE_RSL
3203 #define basename_BDK_OCX_RLKX_BLK_ERR(a) "OCX_RLKX_BLK_ERR"
3204 #define device_bar_BDK_OCX_RLKX_BLK_ERR(a) 0x0 /* PF_BAR0 */
3205 #define busnum_BDK_OCX_RLKX_BLK_ERR(a) (a)
3206 #define arguments_BDK_OCX_RLKX_BLK_ERR(a) (a),-1,-1,-1
3207
3208 /**
3209 * Register (RSL) ocx_rlk#_ecc_ctl
3210 *
3211 * OCX Receive ECC Control Registers
3212 */
3213 union bdk_ocx_rlkx_ecc_ctl
3214 {
3215 uint64_t u;
3216 struct bdk_ocx_rlkx_ecc_ctl_s
3217 {
3218 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3219 uint64_t reserved_36_63 : 28;
3220 uint64_t fifo1_flip : 2; /**< [ 35: 34](R/W) Test pattern to cause ECC errors in top RX FIFO syndromes. */
3221 uint64_t fifo0_flip : 2; /**< [ 33: 32](R/W) Test pattern to cause ECC errors in bottom RX FIFO syndromes. */
3222 uint64_t reserved_2_31 : 30;
3223 uint64_t fifo1_cdis : 1; /**< [ 1: 1](R/W) ECC correction disable for top RX FIFO RAM. */
3224 uint64_t fifo0_cdis : 1; /**< [ 0: 0](R/W) ECC correction disable for bottom RX FIFO RAM. */
3225 #else /* Word 0 - Little Endian */
3226 uint64_t fifo0_cdis : 1; /**< [ 0: 0](R/W) ECC correction disable for bottom RX FIFO RAM. */
3227 uint64_t fifo1_cdis : 1; /**< [ 1: 1](R/W) ECC correction disable for top RX FIFO RAM. */
3228 uint64_t reserved_2_31 : 30;
3229 uint64_t fifo0_flip : 2; /**< [ 33: 32](R/W) Test pattern to cause ECC errors in bottom RX FIFO syndromes. */
3230 uint64_t fifo1_flip : 2; /**< [ 35: 34](R/W) Test pattern to cause ECC errors in top RX FIFO syndromes. */
3231 uint64_t reserved_36_63 : 28;
3232 #endif /* Word 0 - End */
3233 } s;
3234 /* struct bdk_ocx_rlkx_ecc_ctl_s cn; */
3235 };
3236 typedef union bdk_ocx_rlkx_ecc_ctl bdk_ocx_rlkx_ecc_ctl_t;
3237
3238 static inline uint64_t BDK_OCX_RLKX_ECC_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_RLKX_ECC_CTL(unsigned long a)3239 static inline uint64_t BDK_OCX_RLKX_ECC_CTL(unsigned long a)
3240 {
3241 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
3242 return 0x87e011018018ll + 0x2000ll * ((a) & 0x3);
3243 __bdk_csr_fatal("OCX_RLKX_ECC_CTL", 1, a, 0, 0, 0);
3244 }
3245
3246 #define typedef_BDK_OCX_RLKX_ECC_CTL(a) bdk_ocx_rlkx_ecc_ctl_t
3247 #define bustype_BDK_OCX_RLKX_ECC_CTL(a) BDK_CSR_TYPE_RSL
3248 #define basename_BDK_OCX_RLKX_ECC_CTL(a) "OCX_RLKX_ECC_CTL"
3249 #define device_bar_BDK_OCX_RLKX_ECC_CTL(a) 0x0 /* PF_BAR0 */
3250 #define busnum_BDK_OCX_RLKX_ECC_CTL(a) (a)
3251 #define arguments_BDK_OCX_RLKX_ECC_CTL(a) (a),-1,-1,-1
3252
3253 /**
3254 * Register (RSL) ocx_rlk#_enables
3255 *
3256 * OCX Receive Link Enable Registers
3257 */
3258 union bdk_ocx_rlkx_enables
3259 {
3260 uint64_t u;
3261 struct bdk_ocx_rlkx_enables_s
3262 {
3263 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3264 uint64_t reserved_5_63 : 59;
3265 uint64_t mcd : 1; /**< [ 4: 4](R/W) Master enable for all inbound MCD bits. This bit must be enabled by software. once any
3266 trusted-mode validation has occurred and before any [MCD] traffic is generated. [MCD]
3267 traffic
3268 is typically controlled by the OCX_TLK(0..2)_MCD_CTL register. */
3269 uint64_t m_req : 1; /**< [ 3: 3](R/W/H) Master enable for all inbound memory requests. This bit is typically set at reset but is
3270 cleared when operating in trusted-mode and must be enabled by software. */
3271 uint64_t io_req : 1; /**< [ 2: 2](R/W/H) Master enable for all inbound I/O requests. This bit is typically set at reset but is
3272 cleared when operating in trusted-mode and must be enabled by software. */
3273 uint64_t fwd : 1; /**< [ 1: 1](R/W/H) Master enable for all inbound forward commands. This bit is typically set at reset but is
3274 cleared when operating in trusted-mode and must be enabled by software. */
3275 uint64_t co_proc : 1; /**< [ 0: 0](R/W/H) Master enable for all inbound coprocessor commands. This bit is typically set at reset but
3276 is cleared when operating in trusted-mode and must be enabled by software. */
3277 #else /* Word 0 - Little Endian */
3278 uint64_t co_proc : 1; /**< [ 0: 0](R/W/H) Master enable for all inbound coprocessor commands. This bit is typically set at reset but
3279 is cleared when operating in trusted-mode and must be enabled by software. */
3280 uint64_t fwd : 1; /**< [ 1: 1](R/W/H) Master enable for all inbound forward commands. This bit is typically set at reset but is
3281 cleared when operating in trusted-mode and must be enabled by software. */
3282 uint64_t io_req : 1; /**< [ 2: 2](R/W/H) Master enable for all inbound I/O requests. This bit is typically set at reset but is
3283 cleared when operating in trusted-mode and must be enabled by software. */
3284 uint64_t m_req : 1; /**< [ 3: 3](R/W/H) Master enable for all inbound memory requests. This bit is typically set at reset but is
3285 cleared when operating in trusted-mode and must be enabled by software. */
3286 uint64_t mcd : 1; /**< [ 4: 4](R/W) Master enable for all inbound MCD bits. This bit must be enabled by software. once any
3287 trusted-mode validation has occurred and before any [MCD] traffic is generated. [MCD]
3288 traffic
3289 is typically controlled by the OCX_TLK(0..2)_MCD_CTL register. */
3290 uint64_t reserved_5_63 : 59;
3291 #endif /* Word 0 - End */
3292 } s;
3293 /* struct bdk_ocx_rlkx_enables_s cn; */
3294 };
3295 typedef union bdk_ocx_rlkx_enables bdk_ocx_rlkx_enables_t;
3296
3297 static inline uint64_t BDK_OCX_RLKX_ENABLES(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_RLKX_ENABLES(unsigned long a)3298 static inline uint64_t BDK_OCX_RLKX_ENABLES(unsigned long a)
3299 {
3300 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
3301 return 0x87e011018000ll + 0x2000ll * ((a) & 0x3);
3302 __bdk_csr_fatal("OCX_RLKX_ENABLES", 1, a, 0, 0, 0);
3303 }
3304
3305 #define typedef_BDK_OCX_RLKX_ENABLES(a) bdk_ocx_rlkx_enables_t
3306 #define bustype_BDK_OCX_RLKX_ENABLES(a) BDK_CSR_TYPE_RSL
3307 #define basename_BDK_OCX_RLKX_ENABLES(a) "OCX_RLKX_ENABLES"
3308 #define device_bar_BDK_OCX_RLKX_ENABLES(a) 0x0 /* PF_BAR0 */
3309 #define busnum_BDK_OCX_RLKX_ENABLES(a) (a)
3310 #define arguments_BDK_OCX_RLKX_ENABLES(a) (a),-1,-1,-1
3311
3312 /**
3313 * Register (RSL) ocx_rlk#_fifo#_cnt
3314 *
3315 * OCX Receive Link FIFO Count Registers
3316 */
3317 union bdk_ocx_rlkx_fifox_cnt
3318 {
3319 uint64_t u;
3320 struct bdk_ocx_rlkx_fifox_cnt_s
3321 {
3322 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3323 uint64_t reserved_16_63 : 48;
3324 uint64_t count : 16; /**< [ 15: 0](RO/H) RX FIFO count of 64-bit words to send to core. VC13 traffic is used immediately so the
3325 FIFO count is always 0. See OCX_RLK(0..2)_LNK_DATA. */
3326 #else /* Word 0 - Little Endian */
3327 uint64_t count : 16; /**< [ 15: 0](RO/H) RX FIFO count of 64-bit words to send to core. VC13 traffic is used immediately so the
3328 FIFO count is always 0. See OCX_RLK(0..2)_LNK_DATA. */
3329 uint64_t reserved_16_63 : 48;
3330 #endif /* Word 0 - End */
3331 } s;
3332 /* struct bdk_ocx_rlkx_fifox_cnt_s cn; */
3333 };
3334 typedef union bdk_ocx_rlkx_fifox_cnt bdk_ocx_rlkx_fifox_cnt_t;
3335
3336 static inline uint64_t BDK_OCX_RLKX_FIFOX_CNT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCX_RLKX_FIFOX_CNT(unsigned long a,unsigned long b)3337 static inline uint64_t BDK_OCX_RLKX_FIFOX_CNT(unsigned long a, unsigned long b)
3338 {
3339 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=2) && (b<=13)))
3340 return 0x87e011018100ll + 0x2000ll * ((a) & 0x3) + 8ll * ((b) & 0xf);
3341 __bdk_csr_fatal("OCX_RLKX_FIFOX_CNT", 2, a, b, 0, 0);
3342 }
3343
3344 #define typedef_BDK_OCX_RLKX_FIFOX_CNT(a,b) bdk_ocx_rlkx_fifox_cnt_t
3345 #define bustype_BDK_OCX_RLKX_FIFOX_CNT(a,b) BDK_CSR_TYPE_RSL
3346 #define basename_BDK_OCX_RLKX_FIFOX_CNT(a,b) "OCX_RLKX_FIFOX_CNT"
3347 #define device_bar_BDK_OCX_RLKX_FIFOX_CNT(a,b) 0x0 /* PF_BAR0 */
3348 #define busnum_BDK_OCX_RLKX_FIFOX_CNT(a,b) (a)
3349 #define arguments_BDK_OCX_RLKX_FIFOX_CNT(a,b) (a),(b),-1,-1
3350
3351 /**
3352 * Register (RSL) ocx_rlk#_key_high#
3353 *
3354 * OCX Receive Encryption Key Registers
3355 */
3356 union bdk_ocx_rlkx_key_highx
3357 {
3358 uint64_t u;
3359 struct bdk_ocx_rlkx_key_highx_s
3360 {
3361 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3362 uint64_t data : 64; /**< [ 63: 0](WO) Transmit key data \<127:64\>.
3363 Reads as zero if OCX_RLK(0..2)_PROTECT[WO_KEY] = 1. */
3364 #else /* Word 0 - Little Endian */
3365 uint64_t data : 64; /**< [ 63: 0](WO) Transmit key data \<127:64\>.
3366 Reads as zero if OCX_RLK(0..2)_PROTECT[WO_KEY] = 1. */
3367 #endif /* Word 0 - End */
3368 } s;
3369 /* struct bdk_ocx_rlkx_key_highx_s cn; */
3370 };
3371 typedef union bdk_ocx_rlkx_key_highx bdk_ocx_rlkx_key_highx_t;
3372
3373 static inline uint64_t BDK_OCX_RLKX_KEY_HIGHX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCX_RLKX_KEY_HIGHX(unsigned long a,unsigned long b)3374 static inline uint64_t BDK_OCX_RLKX_KEY_HIGHX(unsigned long a, unsigned long b)
3375 {
3376 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=2) && (b<=2)))
3377 return 0x87e011018208ll + 0x2000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3);
3378 __bdk_csr_fatal("OCX_RLKX_KEY_HIGHX", 2, a, b, 0, 0);
3379 }
3380
3381 #define typedef_BDK_OCX_RLKX_KEY_HIGHX(a,b) bdk_ocx_rlkx_key_highx_t
3382 #define bustype_BDK_OCX_RLKX_KEY_HIGHX(a,b) BDK_CSR_TYPE_RSL
3383 #define basename_BDK_OCX_RLKX_KEY_HIGHX(a,b) "OCX_RLKX_KEY_HIGHX"
3384 #define device_bar_BDK_OCX_RLKX_KEY_HIGHX(a,b) 0x0 /* PF_BAR0 */
3385 #define busnum_BDK_OCX_RLKX_KEY_HIGHX(a,b) (a)
3386 #define arguments_BDK_OCX_RLKX_KEY_HIGHX(a,b) (a),(b),-1,-1
3387
3388 /**
3389 * Register (RSL) ocx_rlk#_key_low#
3390 *
3391 * OCX Receive Encryption Key Registers
3392 */
3393 union bdk_ocx_rlkx_key_lowx
3394 {
3395 uint64_t u;
3396 struct bdk_ocx_rlkx_key_lowx_s
3397 {
3398 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3399 uint64_t data : 64; /**< [ 63: 0](WO) Receive key data \<63:0\>.
3400 Reads as zero if OCX_RLK(0..2)_PROTECT[WO_KEY] = 1. */
3401 #else /* Word 0 - Little Endian */
3402 uint64_t data : 64; /**< [ 63: 0](WO) Receive key data \<63:0\>.
3403 Reads as zero if OCX_RLK(0..2)_PROTECT[WO_KEY] = 1. */
3404 #endif /* Word 0 - End */
3405 } s;
3406 /* struct bdk_ocx_rlkx_key_lowx_s cn; */
3407 };
3408 typedef union bdk_ocx_rlkx_key_lowx bdk_ocx_rlkx_key_lowx_t;
3409
3410 static inline uint64_t BDK_OCX_RLKX_KEY_LOWX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCX_RLKX_KEY_LOWX(unsigned long a,unsigned long b)3411 static inline uint64_t BDK_OCX_RLKX_KEY_LOWX(unsigned long a, unsigned long b)
3412 {
3413 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=2) && (b<=2)))
3414 return 0x87e011018200ll + 0x2000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3);
3415 __bdk_csr_fatal("OCX_RLKX_KEY_LOWX", 2, a, b, 0, 0);
3416 }
3417
3418 #define typedef_BDK_OCX_RLKX_KEY_LOWX(a,b) bdk_ocx_rlkx_key_lowx_t
3419 #define bustype_BDK_OCX_RLKX_KEY_LOWX(a,b) BDK_CSR_TYPE_RSL
3420 #define basename_BDK_OCX_RLKX_KEY_LOWX(a,b) "OCX_RLKX_KEY_LOWX"
3421 #define device_bar_BDK_OCX_RLKX_KEY_LOWX(a,b) 0x0 /* PF_BAR0 */
3422 #define busnum_BDK_OCX_RLKX_KEY_LOWX(a,b) (a)
3423 #define arguments_BDK_OCX_RLKX_KEY_LOWX(a,b) (a),(b),-1,-1
3424
3425 /**
3426 * Register (RSL) ocx_rlk#_lnk_data
3427 *
3428 * OCX Receive Link Data Registers
3429 */
3430 union bdk_ocx_rlkx_lnk_data
3431 {
3432 uint64_t u;
3433 struct bdk_ocx_rlkx_lnk_data_s
3434 {
3435 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3436 uint64_t rcvd : 1; /**< [ 63: 63](RO/H) Reads state of OCX_COM_LINK(0..2)_INT[LNK_DATA]; set by hardware when a link data block is
3437 received. */
3438 uint64_t reserved_56_62 : 7;
3439 uint64_t data : 56; /**< [ 55: 0](RO/H) Contents of this register are received from the OCX_TLK(0..2)_LNK_DATA register on the
3440 link partner. Each time a new value is received the RX_LDAT interrupt is generated. */
3441 #else /* Word 0 - Little Endian */
3442 uint64_t data : 56; /**< [ 55: 0](RO/H) Contents of this register are received from the OCX_TLK(0..2)_LNK_DATA register on the
3443 link partner. Each time a new value is received the RX_LDAT interrupt is generated. */
3444 uint64_t reserved_56_62 : 7;
3445 uint64_t rcvd : 1; /**< [ 63: 63](RO/H) Reads state of OCX_COM_LINK(0..2)_INT[LNK_DATA]; set by hardware when a link data block is
3446 received. */
3447 #endif /* Word 0 - End */
3448 } s;
3449 /* struct bdk_ocx_rlkx_lnk_data_s cn; */
3450 };
3451 typedef union bdk_ocx_rlkx_lnk_data bdk_ocx_rlkx_lnk_data_t;
3452
3453 static inline uint64_t BDK_OCX_RLKX_LNK_DATA(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_RLKX_LNK_DATA(unsigned long a)3454 static inline uint64_t BDK_OCX_RLKX_LNK_DATA(unsigned long a)
3455 {
3456 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
3457 return 0x87e011018028ll + 0x2000ll * ((a) & 0x3);
3458 __bdk_csr_fatal("OCX_RLKX_LNK_DATA", 1, a, 0, 0, 0);
3459 }
3460
3461 #define typedef_BDK_OCX_RLKX_LNK_DATA(a) bdk_ocx_rlkx_lnk_data_t
3462 #define bustype_BDK_OCX_RLKX_LNK_DATA(a) BDK_CSR_TYPE_RSL
3463 #define basename_BDK_OCX_RLKX_LNK_DATA(a) "OCX_RLKX_LNK_DATA"
3464 #define device_bar_BDK_OCX_RLKX_LNK_DATA(a) 0x0 /* PF_BAR0 */
3465 #define busnum_BDK_OCX_RLKX_LNK_DATA(a) (a)
3466 #define arguments_BDK_OCX_RLKX_LNK_DATA(a) (a),-1,-1,-1
3467
3468 /**
3469 * Register (RSL) ocx_rlk#_mcd_ctl
3470 *
3471 * OCX Receive MCD Control Registers
3472 * This debug register captures which new MCD bits have been received from the link partner. The
3473 * MCD bits are received when the both the OCX_RLK(0..2)_ENABLES[MCD] bit is set and the MCD was
3474 * not previously transmitted.
3475 */
3476 union bdk_ocx_rlkx_mcd_ctl
3477 {
3478 uint64_t u;
3479 struct bdk_ocx_rlkx_mcd_ctl_s
3480 {
3481 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3482 uint64_t reserved_3_63 : 61;
3483 uint64_t clr : 3; /**< [ 2: 0](R/W1C/H) Shows the inbound MCD value being driven by link(0..2). Set by hardware
3484 receiving an MCD packet and cleared by this register. */
3485 #else /* Word 0 - Little Endian */
3486 uint64_t clr : 3; /**< [ 2: 0](R/W1C/H) Shows the inbound MCD value being driven by link(0..2). Set by hardware
3487 receiving an MCD packet and cleared by this register. */
3488 uint64_t reserved_3_63 : 61;
3489 #endif /* Word 0 - End */
3490 } s;
3491 /* struct bdk_ocx_rlkx_mcd_ctl_s cn; */
3492 };
3493 typedef union bdk_ocx_rlkx_mcd_ctl bdk_ocx_rlkx_mcd_ctl_t;
3494
3495 static inline uint64_t BDK_OCX_RLKX_MCD_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_RLKX_MCD_CTL(unsigned long a)3496 static inline uint64_t BDK_OCX_RLKX_MCD_CTL(unsigned long a)
3497 {
3498 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
3499 return 0x87e011018020ll + 0x2000ll * ((a) & 0x3);
3500 __bdk_csr_fatal("OCX_RLKX_MCD_CTL", 1, a, 0, 0, 0);
3501 }
3502
3503 #define typedef_BDK_OCX_RLKX_MCD_CTL(a) bdk_ocx_rlkx_mcd_ctl_t
3504 #define bustype_BDK_OCX_RLKX_MCD_CTL(a) BDK_CSR_TYPE_RSL
3505 #define basename_BDK_OCX_RLKX_MCD_CTL(a) "OCX_RLKX_MCD_CTL"
3506 #define device_bar_BDK_OCX_RLKX_MCD_CTL(a) 0x0 /* PF_BAR0 */
3507 #define busnum_BDK_OCX_RLKX_MCD_CTL(a) (a)
3508 #define arguments_BDK_OCX_RLKX_MCD_CTL(a) (a),-1,-1,-1
3509
3510 /**
3511 * Register (RSL) ocx_rlk#_protect
3512 *
3513 * OCX Receive Data Protection Control Registers
3514 */
3515 union bdk_ocx_rlkx_protect
3516 {
3517 uint64_t u;
3518 struct bdk_ocx_rlkx_protect_s
3519 {
3520 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3521 uint64_t reserved_8_63 : 56;
3522 uint64_t wo_key : 1; /**< [ 7: 7](R/W1S) Reserved. Setting this bit blocks read access to OCX_RLK()_KEY_LOW,
3523 OCX_RLK()_KEY_HIGH, OCX_RLK()_SALT_LOW and OCX_RLK()_SALT_HIGH registers. */
3524 uint64_t reserved_1_6 : 6;
3525 uint64_t enable : 1; /**< [ 0: 0](RO/H) Data encryption enabled. This bit is set and cleared by the transmitting link
3526 partner. */
3527 #else /* Word 0 - Little Endian */
3528 uint64_t enable : 1; /**< [ 0: 0](RO/H) Data encryption enabled. This bit is set and cleared by the transmitting link
3529 partner. */
3530 uint64_t reserved_1_6 : 6;
3531 uint64_t wo_key : 1; /**< [ 7: 7](R/W1S) Reserved. Setting this bit blocks read access to OCX_RLK()_KEY_LOW,
3532 OCX_RLK()_KEY_HIGH, OCX_RLK()_SALT_LOW and OCX_RLK()_SALT_HIGH registers. */
3533 uint64_t reserved_8_63 : 56;
3534 #endif /* Word 0 - End */
3535 } s;
3536 /* struct bdk_ocx_rlkx_protect_s cn; */
3537 };
3538 typedef union bdk_ocx_rlkx_protect bdk_ocx_rlkx_protect_t;
3539
3540 static inline uint64_t BDK_OCX_RLKX_PROTECT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_RLKX_PROTECT(unsigned long a)3541 static inline uint64_t BDK_OCX_RLKX_PROTECT(unsigned long a)
3542 {
3543 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
3544 return 0x87e0110182c0ll + 0x2000ll * ((a) & 0x3);
3545 __bdk_csr_fatal("OCX_RLKX_PROTECT", 1, a, 0, 0, 0);
3546 }
3547
3548 #define typedef_BDK_OCX_RLKX_PROTECT(a) bdk_ocx_rlkx_protect_t
3549 #define bustype_BDK_OCX_RLKX_PROTECT(a) BDK_CSR_TYPE_RSL
3550 #define basename_BDK_OCX_RLKX_PROTECT(a) "OCX_RLKX_PROTECT"
3551 #define device_bar_BDK_OCX_RLKX_PROTECT(a) 0x0 /* PF_BAR0 */
3552 #define busnum_BDK_OCX_RLKX_PROTECT(a) (a)
3553 #define arguments_BDK_OCX_RLKX_PROTECT(a) (a),-1,-1,-1
3554
3555 /**
3556 * Register (RSL) ocx_rlk#_salt_high
3557 *
3558 * OCX Receive Encryption Salt Registers
3559 */
3560 union bdk_ocx_rlkx_salt_high
3561 {
3562 uint64_t u;
3563 struct bdk_ocx_rlkx_salt_high_s
3564 {
3565 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3566 uint64_t data : 64; /**< [ 63: 0](WO) Receive salt data \<127:64\>.
3567 Reads as zero if OCX_RLK(0..2)_PROTECT[WO_KEY] = 1. */
3568 #else /* Word 0 - Little Endian */
3569 uint64_t data : 64; /**< [ 63: 0](WO) Receive salt data \<127:64\>.
3570 Reads as zero if OCX_RLK(0..2)_PROTECT[WO_KEY] = 1. */
3571 #endif /* Word 0 - End */
3572 } s;
3573 /* struct bdk_ocx_rlkx_salt_high_s cn; */
3574 };
3575 typedef union bdk_ocx_rlkx_salt_high bdk_ocx_rlkx_salt_high_t;
3576
3577 static inline uint64_t BDK_OCX_RLKX_SALT_HIGH(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_RLKX_SALT_HIGH(unsigned long a)3578 static inline uint64_t BDK_OCX_RLKX_SALT_HIGH(unsigned long a)
3579 {
3580 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
3581 return 0x87e011018288ll + 0x2000ll * ((a) & 0x3);
3582 __bdk_csr_fatal("OCX_RLKX_SALT_HIGH", 1, a, 0, 0, 0);
3583 }
3584
3585 #define typedef_BDK_OCX_RLKX_SALT_HIGH(a) bdk_ocx_rlkx_salt_high_t
3586 #define bustype_BDK_OCX_RLKX_SALT_HIGH(a) BDK_CSR_TYPE_RSL
3587 #define basename_BDK_OCX_RLKX_SALT_HIGH(a) "OCX_RLKX_SALT_HIGH"
3588 #define device_bar_BDK_OCX_RLKX_SALT_HIGH(a) 0x0 /* PF_BAR0 */
3589 #define busnum_BDK_OCX_RLKX_SALT_HIGH(a) (a)
3590 #define arguments_BDK_OCX_RLKX_SALT_HIGH(a) (a),-1,-1,-1
3591
3592 /**
3593 * Register (RSL) ocx_rlk#_salt_low
3594 *
3595 * OCX Receive Encryption Salt Registers
3596 */
3597 union bdk_ocx_rlkx_salt_low
3598 {
3599 uint64_t u;
3600 struct bdk_ocx_rlkx_salt_low_s
3601 {
3602 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3603 uint64_t data : 64; /**< [ 63: 0](WO) Receive salt data \<63:0\>.
3604 Reads as zero if OCX_RLK(0..2)_PROTECT[WO_KEY] = 1. */
3605 #else /* Word 0 - Little Endian */
3606 uint64_t data : 64; /**< [ 63: 0](WO) Receive salt data \<63:0\>.
3607 Reads as zero if OCX_RLK(0..2)_PROTECT[WO_KEY] = 1. */
3608 #endif /* Word 0 - End */
3609 } s;
3610 /* struct bdk_ocx_rlkx_salt_low_s cn; */
3611 };
3612 typedef union bdk_ocx_rlkx_salt_low bdk_ocx_rlkx_salt_low_t;
3613
3614 static inline uint64_t BDK_OCX_RLKX_SALT_LOW(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_RLKX_SALT_LOW(unsigned long a)3615 static inline uint64_t BDK_OCX_RLKX_SALT_LOW(unsigned long a)
3616 {
3617 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
3618 return 0x87e011018280ll + 0x2000ll * ((a) & 0x3);
3619 __bdk_csr_fatal("OCX_RLKX_SALT_LOW", 1, a, 0, 0, 0);
3620 }
3621
3622 #define typedef_BDK_OCX_RLKX_SALT_LOW(a) bdk_ocx_rlkx_salt_low_t
3623 #define bustype_BDK_OCX_RLKX_SALT_LOW(a) BDK_CSR_TYPE_RSL
3624 #define basename_BDK_OCX_RLKX_SALT_LOW(a) "OCX_RLKX_SALT_LOW"
3625 #define device_bar_BDK_OCX_RLKX_SALT_LOW(a) 0x0 /* PF_BAR0 */
3626 #define busnum_BDK_OCX_RLKX_SALT_LOW(a) (a)
3627 #define arguments_BDK_OCX_RLKX_SALT_LOW(a) (a),-1,-1,-1
3628
3629 /**
3630 * Register (RSL) ocx_strap
3631 *
3632 * OCX Strap Register
3633 * This register provide read-only access to OCI straps.
3634 */
3635 union bdk_ocx_strap
3636 {
3637 uint64_t u;
3638 struct bdk_ocx_strap_s
3639 {
3640 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3641 uint64_t reserved_26_63 : 38;
3642 uint64_t oci3_lnk1 : 1; /**< [ 25: 25](RO) OCI3_LNK1 strap. */
3643 uint64_t oci2_lnk1 : 1; /**< [ 24: 24](RO) OCI2_LNK1 strap. */
3644 uint64_t reserved_17_23 : 7;
3645 uint64_t oci_fixed_node : 1; /**< [ 16: 16](RO) OCI_FIXED_NODE strap. */
3646 uint64_t reserved_10_15 : 6;
3647 uint64_t oci_node_id : 2; /**< [ 9: 8](RO) OCI_NODE_ID\<1:0\> straps. */
3648 uint64_t reserved_4_7 : 4;
3649 uint64_t oci_spd : 4; /**< [ 3: 0](RO) OCI_SPD\<3:0\> straps. */
3650 #else /* Word 0 - Little Endian */
3651 uint64_t oci_spd : 4; /**< [ 3: 0](RO) OCI_SPD\<3:0\> straps. */
3652 uint64_t reserved_4_7 : 4;
3653 uint64_t oci_node_id : 2; /**< [ 9: 8](RO) OCI_NODE_ID\<1:0\> straps. */
3654 uint64_t reserved_10_15 : 6;
3655 uint64_t oci_fixed_node : 1; /**< [ 16: 16](RO) OCI_FIXED_NODE strap. */
3656 uint64_t reserved_17_23 : 7;
3657 uint64_t oci2_lnk1 : 1; /**< [ 24: 24](RO) OCI2_LNK1 strap. */
3658 uint64_t oci3_lnk1 : 1; /**< [ 25: 25](RO) OCI3_LNK1 strap. */
3659 uint64_t reserved_26_63 : 38;
3660 #endif /* Word 0 - End */
3661 } s;
3662 /* struct bdk_ocx_strap_s cn; */
3663 };
3664 typedef union bdk_ocx_strap bdk_ocx_strap_t;
3665
3666 #define BDK_OCX_STRAP BDK_OCX_STRAP_FUNC()
3667 static inline uint64_t BDK_OCX_STRAP_FUNC(void) __attribute__ ((pure, always_inline));
BDK_OCX_STRAP_FUNC(void)3668 static inline uint64_t BDK_OCX_STRAP_FUNC(void)
3669 {
3670 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X))
3671 return 0x87e01100ff08ll;
3672 __bdk_csr_fatal("OCX_STRAP", 0, 0, 0, 0, 0);
3673 }
3674
3675 #define typedef_BDK_OCX_STRAP bdk_ocx_strap_t
3676 #define bustype_BDK_OCX_STRAP BDK_CSR_TYPE_RSL
3677 #define basename_BDK_OCX_STRAP "OCX_STRAP"
3678 #define device_bar_BDK_OCX_STRAP 0x0 /* PF_BAR0 */
3679 #define busnum_BDK_OCX_STRAP 0
3680 #define arguments_BDK_OCX_STRAP -1,-1,-1,-1
3681
3682 /**
3683 * Register (RSL) ocx_tlk#_bist_status
3684 *
3685 * OCX Link REPLAY Memories and TX FIFOs BIST Status Register
3686 * Contains status from last memory BIST for all TX FIFO memories and REPLAY memories in this
3687 * link. RX FIFO status can be found in OCX_COM_BIST_STATUS.
3688 */
3689 union bdk_ocx_tlkx_bist_status
3690 {
3691 uint64_t u;
3692 struct bdk_ocx_tlkx_bist_status_s
3693 {
3694 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3695 uint64_t reserved_16_63 : 48;
3696 uint64_t status : 16; /**< [ 15: 0](RO/H) \<15:14\> = REPLAY Memories BIST Status \<1:0\>.
3697 \<13:12\> = MOC TX_FIFO BIST Status \<1:0\>.
3698 \<11:0\> = TX_FIFO\<11:0\> by Link VC number. */
3699 #else /* Word 0 - Little Endian */
3700 uint64_t status : 16; /**< [ 15: 0](RO/H) \<15:14\> = REPLAY Memories BIST Status \<1:0\>.
3701 \<13:12\> = MOC TX_FIFO BIST Status \<1:0\>.
3702 \<11:0\> = TX_FIFO\<11:0\> by Link VC number. */
3703 uint64_t reserved_16_63 : 48;
3704 #endif /* Word 0 - End */
3705 } s;
3706 /* struct bdk_ocx_tlkx_bist_status_s cn; */
3707 };
3708 typedef union bdk_ocx_tlkx_bist_status bdk_ocx_tlkx_bist_status_t;
3709
3710 static inline uint64_t BDK_OCX_TLKX_BIST_STATUS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_BIST_STATUS(unsigned long a)3711 static inline uint64_t BDK_OCX_TLKX_BIST_STATUS(unsigned long a)
3712 {
3713 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
3714 return 0x87e011010008ll + 0x2000ll * ((a) & 0x3);
3715 __bdk_csr_fatal("OCX_TLKX_BIST_STATUS", 1, a, 0, 0, 0);
3716 }
3717
3718 #define typedef_BDK_OCX_TLKX_BIST_STATUS(a) bdk_ocx_tlkx_bist_status_t
3719 #define bustype_BDK_OCX_TLKX_BIST_STATUS(a) BDK_CSR_TYPE_RSL
3720 #define basename_BDK_OCX_TLKX_BIST_STATUS(a) "OCX_TLKX_BIST_STATUS"
3721 #define device_bar_BDK_OCX_TLKX_BIST_STATUS(a) 0x0 /* PF_BAR0 */
3722 #define busnum_BDK_OCX_TLKX_BIST_STATUS(a) (a)
3723 #define arguments_BDK_OCX_TLKX_BIST_STATUS(a) (a),-1,-1,-1
3724
3725 /**
3726 * Register (RSL) ocx_tlk#_byp_ctl
3727 *
3728 * OCX Transmit FIFO Bypass Control Registers
3729 * This register is for diagnostic use.
3730 */
3731 union bdk_ocx_tlkx_byp_ctl
3732 {
3733 uint64_t u;
3734 struct bdk_ocx_tlkx_byp_ctl_s
3735 {
3736 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3737 uint64_t reserved_12_63 : 52;
3738 uint64_t vc_dis : 11; /**< [ 11: 1](R/W) VC bypass disable. When set, the corresponding VC is restricted from using
3739 the low latency TX FIFO bypass logic. This logic is typically disabled for
3740 VC0 only. For diagnostic use only. */
3741 uint64_t reserved_0 : 1;
3742 #else /* Word 0 - Little Endian */
3743 uint64_t reserved_0 : 1;
3744 uint64_t vc_dis : 11; /**< [ 11: 1](R/W) VC bypass disable. When set, the corresponding VC is restricted from using
3745 the low latency TX FIFO bypass logic. This logic is typically disabled for
3746 VC0 only. For diagnostic use only. */
3747 uint64_t reserved_12_63 : 52;
3748 #endif /* Word 0 - End */
3749 } s;
3750 /* struct bdk_ocx_tlkx_byp_ctl_s cn; */
3751 };
3752 typedef union bdk_ocx_tlkx_byp_ctl bdk_ocx_tlkx_byp_ctl_t;
3753
3754 static inline uint64_t BDK_OCX_TLKX_BYP_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_BYP_CTL(unsigned long a)3755 static inline uint64_t BDK_OCX_TLKX_BYP_CTL(unsigned long a)
3756 {
3757 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X) && (a<=2))
3758 return 0x87e011010030ll + 0x2000ll * ((a) & 0x3);
3759 __bdk_csr_fatal("OCX_TLKX_BYP_CTL", 1, a, 0, 0, 0);
3760 }
3761
3762 #define typedef_BDK_OCX_TLKX_BYP_CTL(a) bdk_ocx_tlkx_byp_ctl_t
3763 #define bustype_BDK_OCX_TLKX_BYP_CTL(a) BDK_CSR_TYPE_RSL
3764 #define basename_BDK_OCX_TLKX_BYP_CTL(a) "OCX_TLKX_BYP_CTL"
3765 #define device_bar_BDK_OCX_TLKX_BYP_CTL(a) 0x0 /* PF_BAR0 */
3766 #define busnum_BDK_OCX_TLKX_BYP_CTL(a) (a)
3767 #define arguments_BDK_OCX_TLKX_BYP_CTL(a) (a),-1,-1,-1
3768
3769 /**
3770 * Register (RSL) ocx_tlk#_ecc_ctl
3771 *
3772 * OCX Transmit Link ECC Control Registers
3773 */
3774 union bdk_ocx_tlkx_ecc_ctl
3775 {
3776 uint64_t u;
3777 struct bdk_ocx_tlkx_ecc_ctl_s
3778 {
3779 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3780 uint64_t reserved_38_63 : 26;
3781 uint64_t rply1_flip : 2; /**< [ 37: 36](R/W) Test pattern to cause ECC errors in RPLY1 RAM. */
3782 uint64_t rply0_flip : 2; /**< [ 35: 34](R/W) Test pattern to cause ECC errors in RPLY0 RAM. */
3783 uint64_t fifo_flip : 2; /**< [ 33: 32](R/W) Test pattern to cause ECC errors in TX FIFO RAM. */
3784 uint64_t reserved_3_31 : 29;
3785 uint64_t rply1_cdis : 1; /**< [ 2: 2](R/W) ECC correction disable for replay top memories. */
3786 uint64_t rply0_cdis : 1; /**< [ 1: 1](R/W) ECC correction disable for replay bottom memories. */
3787 uint64_t fifo_cdis : 1; /**< [ 0: 0](R/W) ECC correction disable for TX FIFO memories. */
3788 #else /* Word 0 - Little Endian */
3789 uint64_t fifo_cdis : 1; /**< [ 0: 0](R/W) ECC correction disable for TX FIFO memories. */
3790 uint64_t rply0_cdis : 1; /**< [ 1: 1](R/W) ECC correction disable for replay bottom memories. */
3791 uint64_t rply1_cdis : 1; /**< [ 2: 2](R/W) ECC correction disable for replay top memories. */
3792 uint64_t reserved_3_31 : 29;
3793 uint64_t fifo_flip : 2; /**< [ 33: 32](R/W) Test pattern to cause ECC errors in TX FIFO RAM. */
3794 uint64_t rply0_flip : 2; /**< [ 35: 34](R/W) Test pattern to cause ECC errors in RPLY0 RAM. */
3795 uint64_t rply1_flip : 2; /**< [ 37: 36](R/W) Test pattern to cause ECC errors in RPLY1 RAM. */
3796 uint64_t reserved_38_63 : 26;
3797 #endif /* Word 0 - End */
3798 } s;
3799 /* struct bdk_ocx_tlkx_ecc_ctl_s cn; */
3800 };
3801 typedef union bdk_ocx_tlkx_ecc_ctl bdk_ocx_tlkx_ecc_ctl_t;
3802
3803 static inline uint64_t BDK_OCX_TLKX_ECC_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_ECC_CTL(unsigned long a)3804 static inline uint64_t BDK_OCX_TLKX_ECC_CTL(unsigned long a)
3805 {
3806 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
3807 return 0x87e011010018ll + 0x2000ll * ((a) & 0x3);
3808 __bdk_csr_fatal("OCX_TLKX_ECC_CTL", 1, a, 0, 0, 0);
3809 }
3810
3811 #define typedef_BDK_OCX_TLKX_ECC_CTL(a) bdk_ocx_tlkx_ecc_ctl_t
3812 #define bustype_BDK_OCX_TLKX_ECC_CTL(a) BDK_CSR_TYPE_RSL
3813 #define basename_BDK_OCX_TLKX_ECC_CTL(a) "OCX_TLKX_ECC_CTL"
3814 #define device_bar_BDK_OCX_TLKX_ECC_CTL(a) 0x0 /* PF_BAR0 */
3815 #define busnum_BDK_OCX_TLKX_ECC_CTL(a) (a)
3816 #define arguments_BDK_OCX_TLKX_ECC_CTL(a) (a),-1,-1,-1
3817
3818 /**
3819 * Register (RSL) ocx_tlk#_fifo#_cnt
3820 *
3821 * OCX Transmit Link FIFO Count Registers
3822 */
3823 union bdk_ocx_tlkx_fifox_cnt
3824 {
3825 uint64_t u;
3826 struct bdk_ocx_tlkx_fifox_cnt_s
3827 {
3828 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3829 uint64_t reserved_16_63 : 48;
3830 uint64_t count : 16; /**< [ 15: 0](RO/H) TX FIFO count of bus cycles to send. */
3831 #else /* Word 0 - Little Endian */
3832 uint64_t count : 16; /**< [ 15: 0](RO/H) TX FIFO count of bus cycles to send. */
3833 uint64_t reserved_16_63 : 48;
3834 #endif /* Word 0 - End */
3835 } s;
3836 /* struct bdk_ocx_tlkx_fifox_cnt_s cn; */
3837 };
3838 typedef union bdk_ocx_tlkx_fifox_cnt bdk_ocx_tlkx_fifox_cnt_t;
3839
3840 static inline uint64_t BDK_OCX_TLKX_FIFOX_CNT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_FIFOX_CNT(unsigned long a,unsigned long b)3841 static inline uint64_t BDK_OCX_TLKX_FIFOX_CNT(unsigned long a, unsigned long b)
3842 {
3843 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=2) && (b<=13)))
3844 return 0x87e011010100ll + 0x2000ll * ((a) & 0x3) + 8ll * ((b) & 0xf);
3845 __bdk_csr_fatal("OCX_TLKX_FIFOX_CNT", 2, a, b, 0, 0);
3846 }
3847
3848 #define typedef_BDK_OCX_TLKX_FIFOX_CNT(a,b) bdk_ocx_tlkx_fifox_cnt_t
3849 #define bustype_BDK_OCX_TLKX_FIFOX_CNT(a,b) BDK_CSR_TYPE_RSL
3850 #define basename_BDK_OCX_TLKX_FIFOX_CNT(a,b) "OCX_TLKX_FIFOX_CNT"
3851 #define device_bar_BDK_OCX_TLKX_FIFOX_CNT(a,b) 0x0 /* PF_BAR0 */
3852 #define busnum_BDK_OCX_TLKX_FIFOX_CNT(a,b) (a)
3853 #define arguments_BDK_OCX_TLKX_FIFOX_CNT(a,b) (a),(b),-1,-1
3854
3855 /**
3856 * Register (RSL) ocx_tlk#_key_high#
3857 *
3858 * OCX Transmit Encryption Key Registers
3859 */
3860 union bdk_ocx_tlkx_key_highx
3861 {
3862 uint64_t u;
3863 struct bdk_ocx_tlkx_key_highx_s
3864 {
3865 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3866 uint64_t data : 64; /**< [ 63: 0](WO) Transmit encryption key \<127:64\>.
3867 Reads as zero if OCX_TLK(0..2)_PROTECT[WO_KEY] = 1. */
3868 #else /* Word 0 - Little Endian */
3869 uint64_t data : 64; /**< [ 63: 0](WO) Transmit encryption key \<127:64\>.
3870 Reads as zero if OCX_TLK(0..2)_PROTECT[WO_KEY] = 1. */
3871 #endif /* Word 0 - End */
3872 } s;
3873 /* struct bdk_ocx_tlkx_key_highx_s cn; */
3874 };
3875 typedef union bdk_ocx_tlkx_key_highx bdk_ocx_tlkx_key_highx_t;
3876
3877 static inline uint64_t BDK_OCX_TLKX_KEY_HIGHX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_KEY_HIGHX(unsigned long a,unsigned long b)3878 static inline uint64_t BDK_OCX_TLKX_KEY_HIGHX(unsigned long a, unsigned long b)
3879 {
3880 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=2) && (b<=2)))
3881 return 0x87e011010708ll + 0x2000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3);
3882 __bdk_csr_fatal("OCX_TLKX_KEY_HIGHX", 2, a, b, 0, 0);
3883 }
3884
3885 #define typedef_BDK_OCX_TLKX_KEY_HIGHX(a,b) bdk_ocx_tlkx_key_highx_t
3886 #define bustype_BDK_OCX_TLKX_KEY_HIGHX(a,b) BDK_CSR_TYPE_RSL
3887 #define basename_BDK_OCX_TLKX_KEY_HIGHX(a,b) "OCX_TLKX_KEY_HIGHX"
3888 #define device_bar_BDK_OCX_TLKX_KEY_HIGHX(a,b) 0x0 /* PF_BAR0 */
3889 #define busnum_BDK_OCX_TLKX_KEY_HIGHX(a,b) (a)
3890 #define arguments_BDK_OCX_TLKX_KEY_HIGHX(a,b) (a),(b),-1,-1
3891
3892 /**
3893 * Register (RSL) ocx_tlk#_key_low#
3894 *
3895 * OCX Transmit Encryption Key Registers
3896 */
3897 union bdk_ocx_tlkx_key_lowx
3898 {
3899 uint64_t u;
3900 struct bdk_ocx_tlkx_key_lowx_s
3901 {
3902 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3903 uint64_t data : 64; /**< [ 63: 0](WO) Transmit encryption key \<63:0\>.
3904 Reads as zero if OCX_TLK(0..2)_PROTECT[WO_KEY] = 1. */
3905 #else /* Word 0 - Little Endian */
3906 uint64_t data : 64; /**< [ 63: 0](WO) Transmit encryption key \<63:0\>.
3907 Reads as zero if OCX_TLK(0..2)_PROTECT[WO_KEY] = 1. */
3908 #endif /* Word 0 - End */
3909 } s;
3910 /* struct bdk_ocx_tlkx_key_lowx_s cn; */
3911 };
3912 typedef union bdk_ocx_tlkx_key_lowx bdk_ocx_tlkx_key_lowx_t;
3913
3914 static inline uint64_t BDK_OCX_TLKX_KEY_LOWX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_KEY_LOWX(unsigned long a,unsigned long b)3915 static inline uint64_t BDK_OCX_TLKX_KEY_LOWX(unsigned long a, unsigned long b)
3916 {
3917 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=2) && (b<=2)))
3918 return 0x87e011010700ll + 0x2000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x3);
3919 __bdk_csr_fatal("OCX_TLKX_KEY_LOWX", 2, a, b, 0, 0);
3920 }
3921
3922 #define typedef_BDK_OCX_TLKX_KEY_LOWX(a,b) bdk_ocx_tlkx_key_lowx_t
3923 #define bustype_BDK_OCX_TLKX_KEY_LOWX(a,b) BDK_CSR_TYPE_RSL
3924 #define basename_BDK_OCX_TLKX_KEY_LOWX(a,b) "OCX_TLKX_KEY_LOWX"
3925 #define device_bar_BDK_OCX_TLKX_KEY_LOWX(a,b) 0x0 /* PF_BAR0 */
3926 #define busnum_BDK_OCX_TLKX_KEY_LOWX(a,b) (a)
3927 #define arguments_BDK_OCX_TLKX_KEY_LOWX(a,b) (a),(b),-1,-1
3928
3929 /**
3930 * Register (RSL) ocx_tlk#_lnk_data
3931 *
3932 * OCX Transmit Link Data Registers
3933 */
3934 union bdk_ocx_tlkx_lnk_data
3935 {
3936 uint64_t u;
3937 struct bdk_ocx_tlkx_lnk_data_s
3938 {
3939 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3940 uint64_t reserved_56_63 : 8;
3941 uint64_t data : 56; /**< [ 55: 0](R/W) Writes to this register transfer the contents to the OCX_RLK(0..2)_LNK_DATA register on
3942 the receiving link. */
3943 #else /* Word 0 - Little Endian */
3944 uint64_t data : 56; /**< [ 55: 0](R/W) Writes to this register transfer the contents to the OCX_RLK(0..2)_LNK_DATA register on
3945 the receiving link. */
3946 uint64_t reserved_56_63 : 8;
3947 #endif /* Word 0 - End */
3948 } s;
3949 /* struct bdk_ocx_tlkx_lnk_data_s cn; */
3950 };
3951 typedef union bdk_ocx_tlkx_lnk_data bdk_ocx_tlkx_lnk_data_t;
3952
3953 static inline uint64_t BDK_OCX_TLKX_LNK_DATA(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_LNK_DATA(unsigned long a)3954 static inline uint64_t BDK_OCX_TLKX_LNK_DATA(unsigned long a)
3955 {
3956 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
3957 return 0x87e011010028ll + 0x2000ll * ((a) & 0x3);
3958 __bdk_csr_fatal("OCX_TLKX_LNK_DATA", 1, a, 0, 0, 0);
3959 }
3960
3961 #define typedef_BDK_OCX_TLKX_LNK_DATA(a) bdk_ocx_tlkx_lnk_data_t
3962 #define bustype_BDK_OCX_TLKX_LNK_DATA(a) BDK_CSR_TYPE_RSL
3963 #define basename_BDK_OCX_TLKX_LNK_DATA(a) "OCX_TLKX_LNK_DATA"
3964 #define device_bar_BDK_OCX_TLKX_LNK_DATA(a) 0x0 /* PF_BAR0 */
3965 #define busnum_BDK_OCX_TLKX_LNK_DATA(a) (a)
3966 #define arguments_BDK_OCX_TLKX_LNK_DATA(a) (a),-1,-1,-1
3967
3968 /**
3969 * Register (RSL) ocx_tlk#_lnk_vc#_cnt
3970 *
3971 * OCX Transmit Link VC Credits Registers
3972 */
3973 union bdk_ocx_tlkx_lnk_vcx_cnt
3974 {
3975 uint64_t u;
3976 struct bdk_ocx_tlkx_lnk_vcx_cnt_s
3977 {
3978 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3979 uint64_t reserved_16_63 : 48;
3980 uint64_t count : 16; /**< [ 15: 0](RO/H) Link VC credits available for use. VC13 always reads 1 since credits are not required. */
3981 #else /* Word 0 - Little Endian */
3982 uint64_t count : 16; /**< [ 15: 0](RO/H) Link VC credits available for use. VC13 always reads 1 since credits are not required. */
3983 uint64_t reserved_16_63 : 48;
3984 #endif /* Word 0 - End */
3985 } s;
3986 /* struct bdk_ocx_tlkx_lnk_vcx_cnt_s cn; */
3987 };
3988 typedef union bdk_ocx_tlkx_lnk_vcx_cnt bdk_ocx_tlkx_lnk_vcx_cnt_t;
3989
3990 static inline uint64_t BDK_OCX_TLKX_LNK_VCX_CNT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_LNK_VCX_CNT(unsigned long a,unsigned long b)3991 static inline uint64_t BDK_OCX_TLKX_LNK_VCX_CNT(unsigned long a, unsigned long b)
3992 {
3993 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=2) && (b<=13)))
3994 return 0x87e011010200ll + 0x2000ll * ((a) & 0x3) + 8ll * ((b) & 0xf);
3995 __bdk_csr_fatal("OCX_TLKX_LNK_VCX_CNT", 2, a, b, 0, 0);
3996 }
3997
3998 #define typedef_BDK_OCX_TLKX_LNK_VCX_CNT(a,b) bdk_ocx_tlkx_lnk_vcx_cnt_t
3999 #define bustype_BDK_OCX_TLKX_LNK_VCX_CNT(a,b) BDK_CSR_TYPE_RSL
4000 #define basename_BDK_OCX_TLKX_LNK_VCX_CNT(a,b) "OCX_TLKX_LNK_VCX_CNT"
4001 #define device_bar_BDK_OCX_TLKX_LNK_VCX_CNT(a,b) 0x0 /* PF_BAR0 */
4002 #define busnum_BDK_OCX_TLKX_LNK_VCX_CNT(a,b) (a)
4003 #define arguments_BDK_OCX_TLKX_LNK_VCX_CNT(a,b) (a),(b),-1,-1
4004
4005 /**
4006 * Register (RSL) ocx_tlk#_mcd_ctl
4007 *
4008 * OCX Transmit Link MCD Control Registers
4009 * This register controls which MCD bits are transported via the link. For proper operation
4010 * only one link must be enabled in both directions between each pair of link partners.
4011 *
4012 * Internal:
4013 * If N chips are connected over OCX, N-1 links should have MCD enabled.
4014 * A single "central" chip should connect all MCD buses and have a single MCD enabled link
4015 * to each of the other chips. No MCD enabled links should connect between chips that don't
4016 * include the "central" chip.
4017 */
4018 union bdk_ocx_tlkx_mcd_ctl
4019 {
4020 uint64_t u;
4021 struct bdk_ocx_tlkx_mcd_ctl_s
4022 {
4023 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4024 uint64_t reserved_3_63 : 61;
4025 uint64_t tx_enb : 3; /**< [ 2: 0](R/W) Transmission enable signals for MCD bits \<2:0\>. */
4026 #else /* Word 0 - Little Endian */
4027 uint64_t tx_enb : 3; /**< [ 2: 0](R/W) Transmission enable signals for MCD bits \<2:0\>. */
4028 uint64_t reserved_3_63 : 61;
4029 #endif /* Word 0 - End */
4030 } s;
4031 /* struct bdk_ocx_tlkx_mcd_ctl_s cn; */
4032 };
4033 typedef union bdk_ocx_tlkx_mcd_ctl bdk_ocx_tlkx_mcd_ctl_t;
4034
4035 static inline uint64_t BDK_OCX_TLKX_MCD_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_MCD_CTL(unsigned long a)4036 static inline uint64_t BDK_OCX_TLKX_MCD_CTL(unsigned long a)
4037 {
4038 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
4039 return 0x87e011010020ll + 0x2000ll * ((a) & 0x3);
4040 __bdk_csr_fatal("OCX_TLKX_MCD_CTL", 1, a, 0, 0, 0);
4041 }
4042
4043 #define typedef_BDK_OCX_TLKX_MCD_CTL(a) bdk_ocx_tlkx_mcd_ctl_t
4044 #define bustype_BDK_OCX_TLKX_MCD_CTL(a) BDK_CSR_TYPE_RSL
4045 #define basename_BDK_OCX_TLKX_MCD_CTL(a) "OCX_TLKX_MCD_CTL"
4046 #define device_bar_BDK_OCX_TLKX_MCD_CTL(a) 0x0 /* PF_BAR0 */
4047 #define busnum_BDK_OCX_TLKX_MCD_CTL(a) (a)
4048 #define arguments_BDK_OCX_TLKX_MCD_CTL(a) (a),-1,-1,-1
4049
4050 /**
4051 * Register (RSL) ocx_tlk#_protect
4052 *
4053 * OCX Transmit Data Protection Control Registers
4054 */
4055 union bdk_ocx_tlkx_protect
4056 {
4057 uint64_t u;
4058 struct bdk_ocx_tlkx_protect_s
4059 {
4060 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4061 uint64_t reserved_8_63 : 56;
4062 uint64_t wo_key : 1; /**< [ 7: 7](R/W1S) Setting this bit blocks read access to the OCX_TLK(0..2)_KEY and
4063 OCX_TLK(0..2)_SALT registers. Once set this bit cannot be cleared until reset. */
4064 uint64_t reserved_3_6 : 4;
4065 uint64_t busy : 1; /**< [ 2: 2](RO/H) When set, LOAD and/or BUSY signals are being transmitted to the link
4066 partner. Hold off any updates to the OCX_TLK()_KEY_LOW, OCX_TLK()_KEY_HIGH,
4067 OCX_TLK()_SALT_LOW, OCX_TLK()_SALT_HIGH and OCX_TLK()_PROTECT registers while
4068 this bit is set. */
4069 uint64_t load : 1; /**< [ 1: 1](WO) Seting this bit loads the current set of keys written to the
4070 OCX_TLK()_KEY_LOW, OCX_TLK()_KEY_HIGH, OCX_TLK()_SALT_LOW, OCX_TLK()_SALT_HIGH
4071 and forces the receive side of the link parter to do likewise. */
4072 uint64_t enable : 1; /**< [ 0: 0](R/W) Enable data encryption. When set this bit enables encryption on the
4073 transmitter and the receiving link partner.
4074
4075 Internal:
4076 Encryption is non-functional on pass 1. */
4077 #else /* Word 0 - Little Endian */
4078 uint64_t enable : 1; /**< [ 0: 0](R/W) Enable data encryption. When set this bit enables encryption on the
4079 transmitter and the receiving link partner.
4080
4081 Internal:
4082 Encryption is non-functional on pass 1. */
4083 uint64_t load : 1; /**< [ 1: 1](WO) Seting this bit loads the current set of keys written to the
4084 OCX_TLK()_KEY_LOW, OCX_TLK()_KEY_HIGH, OCX_TLK()_SALT_LOW, OCX_TLK()_SALT_HIGH
4085 and forces the receive side of the link parter to do likewise. */
4086 uint64_t busy : 1; /**< [ 2: 2](RO/H) When set, LOAD and/or BUSY signals are being transmitted to the link
4087 partner. Hold off any updates to the OCX_TLK()_KEY_LOW, OCX_TLK()_KEY_HIGH,
4088 OCX_TLK()_SALT_LOW, OCX_TLK()_SALT_HIGH and OCX_TLK()_PROTECT registers while
4089 this bit is set. */
4090 uint64_t reserved_3_6 : 4;
4091 uint64_t wo_key : 1; /**< [ 7: 7](R/W1S) Setting this bit blocks read access to the OCX_TLK(0..2)_KEY and
4092 OCX_TLK(0..2)_SALT registers. Once set this bit cannot be cleared until reset. */
4093 uint64_t reserved_8_63 : 56;
4094 #endif /* Word 0 - End */
4095 } s;
4096 /* struct bdk_ocx_tlkx_protect_s cn; */
4097 };
4098 typedef union bdk_ocx_tlkx_protect bdk_ocx_tlkx_protect_t;
4099
4100 static inline uint64_t BDK_OCX_TLKX_PROTECT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_PROTECT(unsigned long a)4101 static inline uint64_t BDK_OCX_TLKX_PROTECT(unsigned long a)
4102 {
4103 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
4104 return 0x87e0110107c0ll + 0x2000ll * ((a) & 0x3);
4105 __bdk_csr_fatal("OCX_TLKX_PROTECT", 1, a, 0, 0, 0);
4106 }
4107
4108 #define typedef_BDK_OCX_TLKX_PROTECT(a) bdk_ocx_tlkx_protect_t
4109 #define bustype_BDK_OCX_TLKX_PROTECT(a) BDK_CSR_TYPE_RSL
4110 #define basename_BDK_OCX_TLKX_PROTECT(a) "OCX_TLKX_PROTECT"
4111 #define device_bar_BDK_OCX_TLKX_PROTECT(a) 0x0 /* PF_BAR0 */
4112 #define busnum_BDK_OCX_TLKX_PROTECT(a) (a)
4113 #define arguments_BDK_OCX_TLKX_PROTECT(a) (a),-1,-1,-1
4114
4115 /**
4116 * Register (RSL) ocx_tlk#_rtn_vc#_cnt
4117 *
4118 * OCX Transmit Link Return VC Credits Registers
4119 */
4120 union bdk_ocx_tlkx_rtn_vcx_cnt
4121 {
4122 uint64_t u;
4123 struct bdk_ocx_tlkx_rtn_vcx_cnt_s
4124 {
4125 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4126 uint64_t reserved_16_63 : 48;
4127 uint64_t count : 16; /**< [ 15: 0](RO/H) Link VC credits to return. VC13 always reads 0 since credits are never returned. */
4128 #else /* Word 0 - Little Endian */
4129 uint64_t count : 16; /**< [ 15: 0](RO/H) Link VC credits to return. VC13 always reads 0 since credits are never returned. */
4130 uint64_t reserved_16_63 : 48;
4131 #endif /* Word 0 - End */
4132 } s;
4133 /* struct bdk_ocx_tlkx_rtn_vcx_cnt_s cn; */
4134 };
4135 typedef union bdk_ocx_tlkx_rtn_vcx_cnt bdk_ocx_tlkx_rtn_vcx_cnt_t;
4136
4137 static inline uint64_t BDK_OCX_TLKX_RTN_VCX_CNT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_RTN_VCX_CNT(unsigned long a,unsigned long b)4138 static inline uint64_t BDK_OCX_TLKX_RTN_VCX_CNT(unsigned long a, unsigned long b)
4139 {
4140 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=2) && (b<=13)))
4141 return 0x87e011010300ll + 0x2000ll * ((a) & 0x3) + 8ll * ((b) & 0xf);
4142 __bdk_csr_fatal("OCX_TLKX_RTN_VCX_CNT", 2, a, b, 0, 0);
4143 }
4144
4145 #define typedef_BDK_OCX_TLKX_RTN_VCX_CNT(a,b) bdk_ocx_tlkx_rtn_vcx_cnt_t
4146 #define bustype_BDK_OCX_TLKX_RTN_VCX_CNT(a,b) BDK_CSR_TYPE_RSL
4147 #define basename_BDK_OCX_TLKX_RTN_VCX_CNT(a,b) "OCX_TLKX_RTN_VCX_CNT"
4148 #define device_bar_BDK_OCX_TLKX_RTN_VCX_CNT(a,b) 0x0 /* PF_BAR0 */
4149 #define busnum_BDK_OCX_TLKX_RTN_VCX_CNT(a,b) (a)
4150 #define arguments_BDK_OCX_TLKX_RTN_VCX_CNT(a,b) (a),(b),-1,-1
4151
4152 /**
4153 * Register (RSL) ocx_tlk#_salt_high
4154 *
4155 * OCX Transmit Encryption Salt Registers
4156 */
4157 union bdk_ocx_tlkx_salt_high
4158 {
4159 uint64_t u;
4160 struct bdk_ocx_tlkx_salt_high_s
4161 {
4162 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4163 uint64_t data : 64; /**< [ 63: 0](WO) Transmit salt data \<127:64\>.
4164 Reads as zero if OCX_TLK(0..2)_PROTECT[WO_KEY] = 1. */
4165 #else /* Word 0 - Little Endian */
4166 uint64_t data : 64; /**< [ 63: 0](WO) Transmit salt data \<127:64\>.
4167 Reads as zero if OCX_TLK(0..2)_PROTECT[WO_KEY] = 1. */
4168 #endif /* Word 0 - End */
4169 } s;
4170 /* struct bdk_ocx_tlkx_salt_high_s cn; */
4171 };
4172 typedef union bdk_ocx_tlkx_salt_high bdk_ocx_tlkx_salt_high_t;
4173
4174 static inline uint64_t BDK_OCX_TLKX_SALT_HIGH(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_SALT_HIGH(unsigned long a)4175 static inline uint64_t BDK_OCX_TLKX_SALT_HIGH(unsigned long a)
4176 {
4177 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
4178 return 0x87e011010788ll + 0x2000ll * ((a) & 0x3);
4179 __bdk_csr_fatal("OCX_TLKX_SALT_HIGH", 1, a, 0, 0, 0);
4180 }
4181
4182 #define typedef_BDK_OCX_TLKX_SALT_HIGH(a) bdk_ocx_tlkx_salt_high_t
4183 #define bustype_BDK_OCX_TLKX_SALT_HIGH(a) BDK_CSR_TYPE_RSL
4184 #define basename_BDK_OCX_TLKX_SALT_HIGH(a) "OCX_TLKX_SALT_HIGH"
4185 #define device_bar_BDK_OCX_TLKX_SALT_HIGH(a) 0x0 /* PF_BAR0 */
4186 #define busnum_BDK_OCX_TLKX_SALT_HIGH(a) (a)
4187 #define arguments_BDK_OCX_TLKX_SALT_HIGH(a) (a),-1,-1,-1
4188
4189 /**
4190 * Register (RSL) ocx_tlk#_salt_low
4191 *
4192 * OCX Transmit Encryption Salt Registers
4193 */
4194 union bdk_ocx_tlkx_salt_low
4195 {
4196 uint64_t u;
4197 struct bdk_ocx_tlkx_salt_low_s
4198 {
4199 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4200 uint64_t data : 64; /**< [ 63: 0](WO) Transmit salt data \<63:0\>.
4201 Reads as zero if OCX_TLK(0..2)_PROTECT[WO_KEY] = 1. */
4202 #else /* Word 0 - Little Endian */
4203 uint64_t data : 64; /**< [ 63: 0](WO) Transmit salt data \<63:0\>.
4204 Reads as zero if OCX_TLK(0..2)_PROTECT[WO_KEY] = 1. */
4205 #endif /* Word 0 - End */
4206 } s;
4207 /* struct bdk_ocx_tlkx_salt_low_s cn; */
4208 };
4209 typedef union bdk_ocx_tlkx_salt_low bdk_ocx_tlkx_salt_low_t;
4210
4211 static inline uint64_t BDK_OCX_TLKX_SALT_LOW(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_SALT_LOW(unsigned long a)4212 static inline uint64_t BDK_OCX_TLKX_SALT_LOW(unsigned long a)
4213 {
4214 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
4215 return 0x87e011010780ll + 0x2000ll * ((a) & 0x3);
4216 __bdk_csr_fatal("OCX_TLKX_SALT_LOW", 1, a, 0, 0, 0);
4217 }
4218
4219 #define typedef_BDK_OCX_TLKX_SALT_LOW(a) bdk_ocx_tlkx_salt_low_t
4220 #define bustype_BDK_OCX_TLKX_SALT_LOW(a) BDK_CSR_TYPE_RSL
4221 #define basename_BDK_OCX_TLKX_SALT_LOW(a) "OCX_TLKX_SALT_LOW"
4222 #define device_bar_BDK_OCX_TLKX_SALT_LOW(a) 0x0 /* PF_BAR0 */
4223 #define busnum_BDK_OCX_TLKX_SALT_LOW(a) (a)
4224 #define arguments_BDK_OCX_TLKX_SALT_LOW(a) (a),-1,-1,-1
4225
4226 /**
4227 * Register (RSL) ocx_tlk#_stat_ctl
4228 *
4229 * OCX Transmit Link Statistics Control Registers
4230 */
4231 union bdk_ocx_tlkx_stat_ctl
4232 {
4233 uint64_t u;
4234 struct bdk_ocx_tlkx_stat_ctl_s
4235 {
4236 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4237 uint64_t reserved_2_63 : 62;
4238 uint64_t clear : 1; /**< [ 1: 1](WO) Setting this bit clears all OCX_TLK(a)_STAT_*CNT, OCX_TLK(a)_STAT_*CMD,
4239 OCX_TLK(a)_STAT_*PKT and OCX_TLK(0..2)_STAT_*CON registers. */
4240 uint64_t enable : 1; /**< [ 0: 0](R/W) This bit controls the capture of statistics to the OCX_TLK(a)_STAT_*CNT,
4241 OCX_TLK(a)_STAT_*CMD, OCX_TLK(a)_STAT_*PKT and OCX_TLK(a)_STAT_*CON registers. When set,
4242 traffic increments the corresponding registers. When cleared, traffic is ignored. */
4243 #else /* Word 0 - Little Endian */
4244 uint64_t enable : 1; /**< [ 0: 0](R/W) This bit controls the capture of statistics to the OCX_TLK(a)_STAT_*CNT,
4245 OCX_TLK(a)_STAT_*CMD, OCX_TLK(a)_STAT_*PKT and OCX_TLK(a)_STAT_*CON registers. When set,
4246 traffic increments the corresponding registers. When cleared, traffic is ignored. */
4247 uint64_t clear : 1; /**< [ 1: 1](WO) Setting this bit clears all OCX_TLK(a)_STAT_*CNT, OCX_TLK(a)_STAT_*CMD,
4248 OCX_TLK(a)_STAT_*PKT and OCX_TLK(0..2)_STAT_*CON registers. */
4249 uint64_t reserved_2_63 : 62;
4250 #endif /* Word 0 - End */
4251 } s;
4252 /* struct bdk_ocx_tlkx_stat_ctl_s cn; */
4253 };
4254 typedef union bdk_ocx_tlkx_stat_ctl bdk_ocx_tlkx_stat_ctl_t;
4255
4256 static inline uint64_t BDK_OCX_TLKX_STAT_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_STAT_CTL(unsigned long a)4257 static inline uint64_t BDK_OCX_TLKX_STAT_CTL(unsigned long a)
4258 {
4259 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
4260 return 0x87e011010040ll + 0x2000ll * ((a) & 0x3);
4261 __bdk_csr_fatal("OCX_TLKX_STAT_CTL", 1, a, 0, 0, 0);
4262 }
4263
4264 #define typedef_BDK_OCX_TLKX_STAT_CTL(a) bdk_ocx_tlkx_stat_ctl_t
4265 #define bustype_BDK_OCX_TLKX_STAT_CTL(a) BDK_CSR_TYPE_RSL
4266 #define basename_BDK_OCX_TLKX_STAT_CTL(a) "OCX_TLKX_STAT_CTL"
4267 #define device_bar_BDK_OCX_TLKX_STAT_CTL(a) 0x0 /* PF_BAR0 */
4268 #define busnum_BDK_OCX_TLKX_STAT_CTL(a) (a)
4269 #define arguments_BDK_OCX_TLKX_STAT_CTL(a) (a),-1,-1,-1
4270
4271 /**
4272 * Register (RSL) ocx_tlk#_stat_data_cnt
4273 *
4274 * OCX Transmit Link Statistics Data Count Registers
4275 */
4276 union bdk_ocx_tlkx_stat_data_cnt
4277 {
4278 uint64_t u;
4279 struct bdk_ocx_tlkx_stat_data_cnt_s
4280 {
4281 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4282 uint64_t count : 64; /**< [ 63: 0](R/W) Indicates the number of data blocks transferred over the CCPI link while
4283 OCX_TLK()_STAT_CTL[ENABLE] has been set. */
4284 #else /* Word 0 - Little Endian */
4285 uint64_t count : 64; /**< [ 63: 0](R/W) Indicates the number of data blocks transferred over the CCPI link while
4286 OCX_TLK()_STAT_CTL[ENABLE] has been set. */
4287 #endif /* Word 0 - End */
4288 } s;
4289 /* struct bdk_ocx_tlkx_stat_data_cnt_s cn; */
4290 };
4291 typedef union bdk_ocx_tlkx_stat_data_cnt bdk_ocx_tlkx_stat_data_cnt_t;
4292
4293 static inline uint64_t BDK_OCX_TLKX_STAT_DATA_CNT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_STAT_DATA_CNT(unsigned long a)4294 static inline uint64_t BDK_OCX_TLKX_STAT_DATA_CNT(unsigned long a)
4295 {
4296 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
4297 return 0x87e011010408ll + 0x2000ll * ((a) & 0x3);
4298 __bdk_csr_fatal("OCX_TLKX_STAT_DATA_CNT", 1, a, 0, 0, 0);
4299 }
4300
4301 #define typedef_BDK_OCX_TLKX_STAT_DATA_CNT(a) bdk_ocx_tlkx_stat_data_cnt_t
4302 #define bustype_BDK_OCX_TLKX_STAT_DATA_CNT(a) BDK_CSR_TYPE_RSL
4303 #define basename_BDK_OCX_TLKX_STAT_DATA_CNT(a) "OCX_TLKX_STAT_DATA_CNT"
4304 #define device_bar_BDK_OCX_TLKX_STAT_DATA_CNT(a) 0x0 /* PF_BAR0 */
4305 #define busnum_BDK_OCX_TLKX_STAT_DATA_CNT(a) (a)
4306 #define arguments_BDK_OCX_TLKX_STAT_DATA_CNT(a) (a),-1,-1,-1
4307
4308 /**
4309 * Register (RSL) ocx_tlk#_stat_err_cnt
4310 *
4311 * OCX Transmit Link Statistics Error Count Registers
4312 */
4313 union bdk_ocx_tlkx_stat_err_cnt
4314 {
4315 uint64_t u;
4316 struct bdk_ocx_tlkx_stat_err_cnt_s
4317 {
4318 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4319 uint64_t count : 64; /**< [ 63: 0](R/W) Number of blocks received with an error over the CCPI link while
4320 OCX_TLK(0..2)_STAT_CTL[ENABLE] has been set. */
4321 #else /* Word 0 - Little Endian */
4322 uint64_t count : 64; /**< [ 63: 0](R/W) Number of blocks received with an error over the CCPI link while
4323 OCX_TLK(0..2)_STAT_CTL[ENABLE] has been set. */
4324 #endif /* Word 0 - End */
4325 } s;
4326 /* struct bdk_ocx_tlkx_stat_err_cnt_s cn; */
4327 };
4328 typedef union bdk_ocx_tlkx_stat_err_cnt bdk_ocx_tlkx_stat_err_cnt_t;
4329
4330 static inline uint64_t BDK_OCX_TLKX_STAT_ERR_CNT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_STAT_ERR_CNT(unsigned long a)4331 static inline uint64_t BDK_OCX_TLKX_STAT_ERR_CNT(unsigned long a)
4332 {
4333 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
4334 return 0x87e011010420ll + 0x2000ll * ((a) & 0x3);
4335 __bdk_csr_fatal("OCX_TLKX_STAT_ERR_CNT", 1, a, 0, 0, 0);
4336 }
4337
4338 #define typedef_BDK_OCX_TLKX_STAT_ERR_CNT(a) bdk_ocx_tlkx_stat_err_cnt_t
4339 #define bustype_BDK_OCX_TLKX_STAT_ERR_CNT(a) BDK_CSR_TYPE_RSL
4340 #define basename_BDK_OCX_TLKX_STAT_ERR_CNT(a) "OCX_TLKX_STAT_ERR_CNT"
4341 #define device_bar_BDK_OCX_TLKX_STAT_ERR_CNT(a) 0x0 /* PF_BAR0 */
4342 #define busnum_BDK_OCX_TLKX_STAT_ERR_CNT(a) (a)
4343 #define arguments_BDK_OCX_TLKX_STAT_ERR_CNT(a) (a),-1,-1,-1
4344
4345 /**
4346 * Register (RSL) ocx_tlk#_stat_idle_cnt
4347 *
4348 * OCX Transmit Link Statistics Idle Count Registers
4349 */
4350 union bdk_ocx_tlkx_stat_idle_cnt
4351 {
4352 uint64_t u;
4353 struct bdk_ocx_tlkx_stat_idle_cnt_s
4354 {
4355 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4356 uint64_t count : 64; /**< [ 63: 0](R/W) Number of idle blocks transferred over the CCPI link while OCX_TLK(0..2)_STAT_CTL[ENABLE]
4357 has been set. */
4358 #else /* Word 0 - Little Endian */
4359 uint64_t count : 64; /**< [ 63: 0](R/W) Number of idle blocks transferred over the CCPI link while OCX_TLK(0..2)_STAT_CTL[ENABLE]
4360 has been set. */
4361 #endif /* Word 0 - End */
4362 } s;
4363 /* struct bdk_ocx_tlkx_stat_idle_cnt_s cn; */
4364 };
4365 typedef union bdk_ocx_tlkx_stat_idle_cnt bdk_ocx_tlkx_stat_idle_cnt_t;
4366
4367 static inline uint64_t BDK_OCX_TLKX_STAT_IDLE_CNT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_STAT_IDLE_CNT(unsigned long a)4368 static inline uint64_t BDK_OCX_TLKX_STAT_IDLE_CNT(unsigned long a)
4369 {
4370 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
4371 return 0x87e011010400ll + 0x2000ll * ((a) & 0x3);
4372 __bdk_csr_fatal("OCX_TLKX_STAT_IDLE_CNT", 1, a, 0, 0, 0);
4373 }
4374
4375 #define typedef_BDK_OCX_TLKX_STAT_IDLE_CNT(a) bdk_ocx_tlkx_stat_idle_cnt_t
4376 #define bustype_BDK_OCX_TLKX_STAT_IDLE_CNT(a) BDK_CSR_TYPE_RSL
4377 #define basename_BDK_OCX_TLKX_STAT_IDLE_CNT(a) "OCX_TLKX_STAT_IDLE_CNT"
4378 #define device_bar_BDK_OCX_TLKX_STAT_IDLE_CNT(a) 0x0 /* PF_BAR0 */
4379 #define busnum_BDK_OCX_TLKX_STAT_IDLE_CNT(a) (a)
4380 #define arguments_BDK_OCX_TLKX_STAT_IDLE_CNT(a) (a),-1,-1,-1
4381
4382 /**
4383 * Register (RSL) ocx_tlk#_stat_mat#_cnt
4384 *
4385 * OCX Transmit Link Statistics Match Count Registers
4386 */
4387 union bdk_ocx_tlkx_stat_matx_cnt
4388 {
4389 uint64_t u;
4390 struct bdk_ocx_tlkx_stat_matx_cnt_s
4391 {
4392 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4393 uint64_t count : 64; /**< [ 63: 0](R/W) Number of packets that have matched OCX_TLK(a)_STAT_MATCH0 and have been transferred over
4394 the CCPI link while OCX_TLK(0..2)_STAT_CTL[ENABLE] has been set. */
4395 #else /* Word 0 - Little Endian */
4396 uint64_t count : 64; /**< [ 63: 0](R/W) Number of packets that have matched OCX_TLK(a)_STAT_MATCH0 and have been transferred over
4397 the CCPI link while OCX_TLK(0..2)_STAT_CTL[ENABLE] has been set. */
4398 #endif /* Word 0 - End */
4399 } s;
4400 /* struct bdk_ocx_tlkx_stat_matx_cnt_s cn; */
4401 };
4402 typedef union bdk_ocx_tlkx_stat_matx_cnt bdk_ocx_tlkx_stat_matx_cnt_t;
4403
4404 static inline uint64_t BDK_OCX_TLKX_STAT_MATX_CNT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_STAT_MATX_CNT(unsigned long a,unsigned long b)4405 static inline uint64_t BDK_OCX_TLKX_STAT_MATX_CNT(unsigned long a, unsigned long b)
4406 {
4407 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=2) && (b<=3)))
4408 return 0x87e011010440ll + 0x2000ll * ((a) & 0x3) + 8ll * ((b) & 0x3);
4409 __bdk_csr_fatal("OCX_TLKX_STAT_MATX_CNT", 2, a, b, 0, 0);
4410 }
4411
4412 #define typedef_BDK_OCX_TLKX_STAT_MATX_CNT(a,b) bdk_ocx_tlkx_stat_matx_cnt_t
4413 #define bustype_BDK_OCX_TLKX_STAT_MATX_CNT(a,b) BDK_CSR_TYPE_RSL
4414 #define basename_BDK_OCX_TLKX_STAT_MATX_CNT(a,b) "OCX_TLKX_STAT_MATX_CNT"
4415 #define device_bar_BDK_OCX_TLKX_STAT_MATX_CNT(a,b) 0x0 /* PF_BAR0 */
4416 #define busnum_BDK_OCX_TLKX_STAT_MATX_CNT(a,b) (a)
4417 #define arguments_BDK_OCX_TLKX_STAT_MATX_CNT(a,b) (a),(b),-1,-1
4418
4419 /**
4420 * Register (RSL) ocx_tlk#_stat_match#
4421 *
4422 * OCX Transmit Link Statistics Match Registers
4423 */
4424 union bdk_ocx_tlkx_stat_matchx
4425 {
4426 uint64_t u;
4427 struct bdk_ocx_tlkx_stat_matchx_s
4428 {
4429 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4430 uint64_t reserved_25_63 : 39;
4431 uint64_t mask : 9; /**< [ 24: 16](R/W) Setting these bits mask (really matches) the corresponding bit comparison for each packet. */
4432 uint64_t reserved_9_15 : 7;
4433 uint64_t cmd : 5; /**< [ 8: 4](R/W) These bits are compared against the command for each packet sent over the link. If both
4434 the unmasked [VC] and [CMD] bits match then OCX_TLK(0..2)_STAT_MAT(0..3)_CNT is
4435 incremented. */
4436 uint64_t vc : 4; /**< [ 3: 0](R/W) These bits are compared against the link VC number for each packet sent over the link.
4437 If both the unmasked [VC] and [CMD] bits match, then OCX_TLK(0..2)_STAT_MAT(0..3)_CNT is
4438 incremented. Only memory and I/O traffic are monitored. Matches are limited to
4439 VC0 through VC11. */
4440 #else /* Word 0 - Little Endian */
4441 uint64_t vc : 4; /**< [ 3: 0](R/W) These bits are compared against the link VC number for each packet sent over the link.
4442 If both the unmasked [VC] and [CMD] bits match, then OCX_TLK(0..2)_STAT_MAT(0..3)_CNT is
4443 incremented. Only memory and I/O traffic are monitored. Matches are limited to
4444 VC0 through VC11. */
4445 uint64_t cmd : 5; /**< [ 8: 4](R/W) These bits are compared against the command for each packet sent over the link. If both
4446 the unmasked [VC] and [CMD] bits match then OCX_TLK(0..2)_STAT_MAT(0..3)_CNT is
4447 incremented. */
4448 uint64_t reserved_9_15 : 7;
4449 uint64_t mask : 9; /**< [ 24: 16](R/W) Setting these bits mask (really matches) the corresponding bit comparison for each packet. */
4450 uint64_t reserved_25_63 : 39;
4451 #endif /* Word 0 - End */
4452 } s;
4453 /* struct bdk_ocx_tlkx_stat_matchx_s cn; */
4454 };
4455 typedef union bdk_ocx_tlkx_stat_matchx bdk_ocx_tlkx_stat_matchx_t;
4456
4457 static inline uint64_t BDK_OCX_TLKX_STAT_MATCHX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_STAT_MATCHX(unsigned long a,unsigned long b)4458 static inline uint64_t BDK_OCX_TLKX_STAT_MATCHX(unsigned long a, unsigned long b)
4459 {
4460 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=2) && (b<=3)))
4461 return 0x87e011010080ll + 0x2000ll * ((a) & 0x3) + 8ll * ((b) & 0x3);
4462 __bdk_csr_fatal("OCX_TLKX_STAT_MATCHX", 2, a, b, 0, 0);
4463 }
4464
4465 #define typedef_BDK_OCX_TLKX_STAT_MATCHX(a,b) bdk_ocx_tlkx_stat_matchx_t
4466 #define bustype_BDK_OCX_TLKX_STAT_MATCHX(a,b) BDK_CSR_TYPE_RSL
4467 #define basename_BDK_OCX_TLKX_STAT_MATCHX(a,b) "OCX_TLKX_STAT_MATCHX"
4468 #define device_bar_BDK_OCX_TLKX_STAT_MATCHX(a,b) 0x0 /* PF_BAR0 */
4469 #define busnum_BDK_OCX_TLKX_STAT_MATCHX(a,b) (a)
4470 #define arguments_BDK_OCX_TLKX_STAT_MATCHX(a,b) (a),(b),-1,-1
4471
4472 /**
4473 * Register (RSL) ocx_tlk#_stat_retry_cnt
4474 *
4475 * OCX Transmit Link Statistics Retry Count Registers
4476 */
4477 union bdk_ocx_tlkx_stat_retry_cnt
4478 {
4479 uint64_t u;
4480 struct bdk_ocx_tlkx_stat_retry_cnt_s
4481 {
4482 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4483 uint64_t count : 64; /**< [ 63: 0](R/W) Specifies the number of data blocks repeated over the CCPI link while
4484 OCX_TLK(0..2)_STAT_CTL[ENABLE] has
4485 been set. */
4486 #else /* Word 0 - Little Endian */
4487 uint64_t count : 64; /**< [ 63: 0](R/W) Specifies the number of data blocks repeated over the CCPI link while
4488 OCX_TLK(0..2)_STAT_CTL[ENABLE] has
4489 been set. */
4490 #endif /* Word 0 - End */
4491 } s;
4492 /* struct bdk_ocx_tlkx_stat_retry_cnt_s cn; */
4493 };
4494 typedef union bdk_ocx_tlkx_stat_retry_cnt bdk_ocx_tlkx_stat_retry_cnt_t;
4495
4496 static inline uint64_t BDK_OCX_TLKX_STAT_RETRY_CNT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_STAT_RETRY_CNT(unsigned long a)4497 static inline uint64_t BDK_OCX_TLKX_STAT_RETRY_CNT(unsigned long a)
4498 {
4499 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
4500 return 0x87e011010418ll + 0x2000ll * ((a) & 0x3);
4501 __bdk_csr_fatal("OCX_TLKX_STAT_RETRY_CNT", 1, a, 0, 0, 0);
4502 }
4503
4504 #define typedef_BDK_OCX_TLKX_STAT_RETRY_CNT(a) bdk_ocx_tlkx_stat_retry_cnt_t
4505 #define bustype_BDK_OCX_TLKX_STAT_RETRY_CNT(a) BDK_CSR_TYPE_RSL
4506 #define basename_BDK_OCX_TLKX_STAT_RETRY_CNT(a) "OCX_TLKX_STAT_RETRY_CNT"
4507 #define device_bar_BDK_OCX_TLKX_STAT_RETRY_CNT(a) 0x0 /* PF_BAR0 */
4508 #define busnum_BDK_OCX_TLKX_STAT_RETRY_CNT(a) (a)
4509 #define arguments_BDK_OCX_TLKX_STAT_RETRY_CNT(a) (a),-1,-1,-1
4510
4511 /**
4512 * Register (RSL) ocx_tlk#_stat_sync_cnt
4513 *
4514 * OCX Transmit Link Statistics Sync Count Registers
4515 */
4516 union bdk_ocx_tlkx_stat_sync_cnt
4517 {
4518 uint64_t u;
4519 struct bdk_ocx_tlkx_stat_sync_cnt_s
4520 {
4521 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4522 uint64_t count : 64; /**< [ 63: 0](R/W) Indicates the number of sync (control) blocks transferred over the CCPI link while
4523 OCX_TLK(0..2)_STAT_CTL[ENABLE] has been set. */
4524 #else /* Word 0 - Little Endian */
4525 uint64_t count : 64; /**< [ 63: 0](R/W) Indicates the number of sync (control) blocks transferred over the CCPI link while
4526 OCX_TLK(0..2)_STAT_CTL[ENABLE] has been set. */
4527 #endif /* Word 0 - End */
4528 } s;
4529 /* struct bdk_ocx_tlkx_stat_sync_cnt_s cn; */
4530 };
4531 typedef union bdk_ocx_tlkx_stat_sync_cnt bdk_ocx_tlkx_stat_sync_cnt_t;
4532
4533 static inline uint64_t BDK_OCX_TLKX_STAT_SYNC_CNT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_STAT_SYNC_CNT(unsigned long a)4534 static inline uint64_t BDK_OCX_TLKX_STAT_SYNC_CNT(unsigned long a)
4535 {
4536 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
4537 return 0x87e011010410ll + 0x2000ll * ((a) & 0x3);
4538 __bdk_csr_fatal("OCX_TLKX_STAT_SYNC_CNT", 1, a, 0, 0, 0);
4539 }
4540
4541 #define typedef_BDK_OCX_TLKX_STAT_SYNC_CNT(a) bdk_ocx_tlkx_stat_sync_cnt_t
4542 #define bustype_BDK_OCX_TLKX_STAT_SYNC_CNT(a) BDK_CSR_TYPE_RSL
4543 #define basename_BDK_OCX_TLKX_STAT_SYNC_CNT(a) "OCX_TLKX_STAT_SYNC_CNT"
4544 #define device_bar_BDK_OCX_TLKX_STAT_SYNC_CNT(a) 0x0 /* PF_BAR0 */
4545 #define busnum_BDK_OCX_TLKX_STAT_SYNC_CNT(a) (a)
4546 #define arguments_BDK_OCX_TLKX_STAT_SYNC_CNT(a) (a),-1,-1,-1
4547
4548 /**
4549 * Register (RSL) ocx_tlk#_stat_vc#_cmd
4550 *
4551 * OCX Transmit Link Statistics VC Commands Count Registers
4552 */
4553 union bdk_ocx_tlkx_stat_vcx_cmd
4554 {
4555 uint64_t u;
4556 struct bdk_ocx_tlkx_stat_vcx_cmd_s
4557 {
4558 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4559 uint64_t count : 64; /**< [ 63: 0](R/W) Number of commands on this VC that have been transfered over the CCPI link while
4560 OCX_TLK(0..2)_STAT_CTL[ENABLE] has been set. For VCs 6 through 13 the number of commands
4561 is equal to the number of packets. */
4562 #else /* Word 0 - Little Endian */
4563 uint64_t count : 64; /**< [ 63: 0](R/W) Number of commands on this VC that have been transfered over the CCPI link while
4564 OCX_TLK(0..2)_STAT_CTL[ENABLE] has been set. For VCs 6 through 13 the number of commands
4565 is equal to the number of packets. */
4566 #endif /* Word 0 - End */
4567 } s;
4568 /* struct bdk_ocx_tlkx_stat_vcx_cmd_s cn; */
4569 };
4570 typedef union bdk_ocx_tlkx_stat_vcx_cmd bdk_ocx_tlkx_stat_vcx_cmd_t;
4571
4572 static inline uint64_t BDK_OCX_TLKX_STAT_VCX_CMD(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_STAT_VCX_CMD(unsigned long a,unsigned long b)4573 static inline uint64_t BDK_OCX_TLKX_STAT_VCX_CMD(unsigned long a, unsigned long b)
4574 {
4575 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=2) && (b<=5)))
4576 return 0x87e011010480ll + 0x2000ll * ((a) & 0x3) + 8ll * ((b) & 0x7);
4577 __bdk_csr_fatal("OCX_TLKX_STAT_VCX_CMD", 2, a, b, 0, 0);
4578 }
4579
4580 #define typedef_BDK_OCX_TLKX_STAT_VCX_CMD(a,b) bdk_ocx_tlkx_stat_vcx_cmd_t
4581 #define bustype_BDK_OCX_TLKX_STAT_VCX_CMD(a,b) BDK_CSR_TYPE_RSL
4582 #define basename_BDK_OCX_TLKX_STAT_VCX_CMD(a,b) "OCX_TLKX_STAT_VCX_CMD"
4583 #define device_bar_BDK_OCX_TLKX_STAT_VCX_CMD(a,b) 0x0 /* PF_BAR0 */
4584 #define busnum_BDK_OCX_TLKX_STAT_VCX_CMD(a,b) (a)
4585 #define arguments_BDK_OCX_TLKX_STAT_VCX_CMD(a,b) (a),(b),-1,-1
4586
4587 /**
4588 * Register (RSL) ocx_tlk#_stat_vc#_con
4589 *
4590 * OCX Transmit Link Statistics VC Conflict Count Registers
4591 */
4592 union bdk_ocx_tlkx_stat_vcx_con
4593 {
4594 uint64_t u;
4595 struct bdk_ocx_tlkx_stat_vcx_con_s
4596 {
4597 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4598 uint64_t count : 64; /**< [ 63: 0](R/W) Number of conflicts on this VC while OCX_TLK(0..2)_STAT_CTL[ENABLE] has been set. A
4599 conflict is indicated when a VC has one or more packets to send and no link credits are
4600 available. VC13 does not require credits so no conflicts are ever indicated (i.e. reads
4601 0). */
4602 #else /* Word 0 - Little Endian */
4603 uint64_t count : 64; /**< [ 63: 0](R/W) Number of conflicts on this VC while OCX_TLK(0..2)_STAT_CTL[ENABLE] has been set. A
4604 conflict is indicated when a VC has one or more packets to send and no link credits are
4605 available. VC13 does not require credits so no conflicts are ever indicated (i.e. reads
4606 0). */
4607 #endif /* Word 0 - End */
4608 } s;
4609 /* struct bdk_ocx_tlkx_stat_vcx_con_s cn; */
4610 };
4611 typedef union bdk_ocx_tlkx_stat_vcx_con bdk_ocx_tlkx_stat_vcx_con_t;
4612
4613 static inline uint64_t BDK_OCX_TLKX_STAT_VCX_CON(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_STAT_VCX_CON(unsigned long a,unsigned long b)4614 static inline uint64_t BDK_OCX_TLKX_STAT_VCX_CON(unsigned long a, unsigned long b)
4615 {
4616 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=2) && (b<=13)))
4617 return 0x87e011010580ll + 0x2000ll * ((a) & 0x3) + 8ll * ((b) & 0xf);
4618 __bdk_csr_fatal("OCX_TLKX_STAT_VCX_CON", 2, a, b, 0, 0);
4619 }
4620
4621 #define typedef_BDK_OCX_TLKX_STAT_VCX_CON(a,b) bdk_ocx_tlkx_stat_vcx_con_t
4622 #define bustype_BDK_OCX_TLKX_STAT_VCX_CON(a,b) BDK_CSR_TYPE_RSL
4623 #define basename_BDK_OCX_TLKX_STAT_VCX_CON(a,b) "OCX_TLKX_STAT_VCX_CON"
4624 #define device_bar_BDK_OCX_TLKX_STAT_VCX_CON(a,b) 0x0 /* PF_BAR0 */
4625 #define busnum_BDK_OCX_TLKX_STAT_VCX_CON(a,b) (a)
4626 #define arguments_BDK_OCX_TLKX_STAT_VCX_CON(a,b) (a),(b),-1,-1
4627
4628 /**
4629 * Register (RSL) ocx_tlk#_stat_vc#_pkt
4630 *
4631 * OCX Transmit Link Statistics VC Packet Count Registers
4632 */
4633 union bdk_ocx_tlkx_stat_vcx_pkt
4634 {
4635 uint64_t u;
4636 struct bdk_ocx_tlkx_stat_vcx_pkt_s
4637 {
4638 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4639 uint64_t count : 64; /**< [ 63: 0](R/W) Number of packets on this VC that have been transferred over the CCPI link while
4640 OCX_TLK(0..2)_STAT_CTL[ENABLE] has been set. */
4641 #else /* Word 0 - Little Endian */
4642 uint64_t count : 64; /**< [ 63: 0](R/W) Number of packets on this VC that have been transferred over the CCPI link while
4643 OCX_TLK(0..2)_STAT_CTL[ENABLE] has been set. */
4644 #endif /* Word 0 - End */
4645 } s;
4646 /* struct bdk_ocx_tlkx_stat_vcx_pkt_s cn; */
4647 };
4648 typedef union bdk_ocx_tlkx_stat_vcx_pkt bdk_ocx_tlkx_stat_vcx_pkt_t;
4649
4650 static inline uint64_t BDK_OCX_TLKX_STAT_VCX_PKT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_STAT_VCX_PKT(unsigned long a,unsigned long b)4651 static inline uint64_t BDK_OCX_TLKX_STAT_VCX_PKT(unsigned long a, unsigned long b)
4652 {
4653 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=2) && (b<=13)))
4654 return 0x87e011010500ll + 0x2000ll * ((a) & 0x3) + 8ll * ((b) & 0xf);
4655 __bdk_csr_fatal("OCX_TLKX_STAT_VCX_PKT", 2, a, b, 0, 0);
4656 }
4657
4658 #define typedef_BDK_OCX_TLKX_STAT_VCX_PKT(a,b) bdk_ocx_tlkx_stat_vcx_pkt_t
4659 #define bustype_BDK_OCX_TLKX_STAT_VCX_PKT(a,b) BDK_CSR_TYPE_RSL
4660 #define basename_BDK_OCX_TLKX_STAT_VCX_PKT(a,b) "OCX_TLKX_STAT_VCX_PKT"
4661 #define device_bar_BDK_OCX_TLKX_STAT_VCX_PKT(a,b) 0x0 /* PF_BAR0 */
4662 #define busnum_BDK_OCX_TLKX_STAT_VCX_PKT(a,b) (a)
4663 #define arguments_BDK_OCX_TLKX_STAT_VCX_PKT(a,b) (a),(b),-1,-1
4664
4665 /**
4666 * Register (RSL) ocx_tlk#_status
4667 *
4668 * OCX Transmit Link Status Registers
4669 */
4670 union bdk_ocx_tlkx_status
4671 {
4672 uint64_t u;
4673 struct bdk_ocx_tlkx_status_s
4674 {
4675 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4676 uint64_t reserved_56_63 : 8;
4677 uint64_t rply_fptr : 8; /**< [ 55: 48](RO/H) Replay buffer last free pointer. */
4678 uint64_t tx_seq : 8; /**< [ 47: 40](RO/H) Last block transmitted. */
4679 uint64_t rx_seq : 8; /**< [ 39: 32](RO/H) Last block received. */
4680 uint64_t reserved_23_31 : 9;
4681 uint64_t ackcnt : 7; /**< [ 22: 16](RO/H) Indicates the number of ACKs waiting to be transmitted. */
4682 uint64_t reserved_9_15 : 7;
4683 uint64_t drop : 1; /**< [ 8: 8](RO/H) Link is dropping all requests. */
4684 uint64_t sm : 6; /**< [ 7: 2](RO/H) Block state machine:
4685 Bit\<2\>: Req / Ack (Init or retry only).
4686 Bit\<3\>: Init.
4687 Bit\<4\>: Run.
4688 Bit\<5\>: Retry.
4689 Bit\<6\>: Replay.
4690 Bit\<7\>: Replay Pending. */
4691 uint64_t cnt : 2; /**< [ 1: 0](RO/H) Block subcount. Should always increment 0,1,2,3,0.. except during TX PHY stall. */
4692 #else /* Word 0 - Little Endian */
4693 uint64_t cnt : 2; /**< [ 1: 0](RO/H) Block subcount. Should always increment 0,1,2,3,0.. except during TX PHY stall. */
4694 uint64_t sm : 6; /**< [ 7: 2](RO/H) Block state machine:
4695 Bit\<2\>: Req / Ack (Init or retry only).
4696 Bit\<3\>: Init.
4697 Bit\<4\>: Run.
4698 Bit\<5\>: Retry.
4699 Bit\<6\>: Replay.
4700 Bit\<7\>: Replay Pending. */
4701 uint64_t drop : 1; /**< [ 8: 8](RO/H) Link is dropping all requests. */
4702 uint64_t reserved_9_15 : 7;
4703 uint64_t ackcnt : 7; /**< [ 22: 16](RO/H) Indicates the number of ACKs waiting to be transmitted. */
4704 uint64_t reserved_23_31 : 9;
4705 uint64_t rx_seq : 8; /**< [ 39: 32](RO/H) Last block received. */
4706 uint64_t tx_seq : 8; /**< [ 47: 40](RO/H) Last block transmitted. */
4707 uint64_t rply_fptr : 8; /**< [ 55: 48](RO/H) Replay buffer last free pointer. */
4708 uint64_t reserved_56_63 : 8;
4709 #endif /* Word 0 - End */
4710 } s;
4711 /* struct bdk_ocx_tlkx_status_s cn; */
4712 };
4713 typedef union bdk_ocx_tlkx_status bdk_ocx_tlkx_status_t;
4714
4715 static inline uint64_t BDK_OCX_TLKX_STATUS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_OCX_TLKX_STATUS(unsigned long a)4716 static inline uint64_t BDK_OCX_TLKX_STATUS(unsigned long a)
4717 {
4718 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
4719 return 0x87e011010000ll + 0x2000ll * ((a) & 0x3);
4720 __bdk_csr_fatal("OCX_TLKX_STATUS", 1, a, 0, 0, 0);
4721 }
4722
4723 #define typedef_BDK_OCX_TLKX_STATUS(a) bdk_ocx_tlkx_status_t
4724 #define bustype_BDK_OCX_TLKX_STATUS(a) BDK_CSR_TYPE_RSL
4725 #define basename_BDK_OCX_TLKX_STATUS(a) "OCX_TLKX_STATUS"
4726 #define device_bar_BDK_OCX_TLKX_STATUS(a) 0x0 /* PF_BAR0 */
4727 #define busnum_BDK_OCX_TLKX_STATUS(a) (a)
4728 #define arguments_BDK_OCX_TLKX_STATUS(a) (a),-1,-1,-1
4729
4730 /**
4731 * Register (RSL) ocx_win_cmd
4732 *
4733 * OCX Window Address Register
4734 * For diagnostic use only. This register is typically written by hardware after accesses to the
4735 * SLI_WIN_* registers. Contains the address, read size and write mask to used for the window
4736 * operation. Write data should be written first and placed in the OCX_WIN_WR_DATA register.
4737 * Writing this register starts the operation. A second write operation to this register while an
4738 * operation
4739 * is in progress will stall.
4740 */
4741 union bdk_ocx_win_cmd
4742 {
4743 uint64_t u;
4744 struct bdk_ocx_win_cmd_s
4745 {
4746 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4747 uint64_t wr_mask : 8; /**< [ 63: 56](R/W) Mask for the data to be written. When a bit is 1, the corresponding byte will be written.
4748 The values of this field must be contiguous and for 1, 2, 4, or 8 byte operations and
4749 aligned to operation size. A value of 0 will produce unpredictable results. Field is
4750 ignored during a read (LD_OP=1). */
4751 uint64_t reserved_54_55 : 2;
4752 uint64_t el : 2; /**< [ 53: 52](R/W) Execution level. This field is used to supply the execution level of the generated load
4753 or store command. */
4754 uint64_t nsecure : 1; /**< [ 51: 51](R/W) Nonsecure mode. Setting this bit causes the generated load or store command to be
4755 considered nonsecure. */
4756 uint64_t ld_cmd : 2; /**< [ 50: 49](R/W) The load command sent with the read:
4757 0x0 = Load 1-bytes.
4758 0x1 = Load 2-bytes.
4759 0x2 = Load 4-bytes.
4760 0x3 = Load 8-bytes. */
4761 uint64_t ld_op : 1; /**< [ 48: 48](R/W) Operation type:
4762 0 = Store.
4763 1 = Load operation. */
4764 uint64_t addr : 48; /**< [ 47: 0](R/W) The address used in both the load and store operations:
4765 \<47:46\> = Reserved.
4766 \<45:44\> = CCPI_ID.
4767 \<43:36\> = NCB_ID.
4768 \<35:0\> = Address.
4769
4770 When \<43:36\> NCB_ID is RSL (0x7E) address field is defined as:
4771 \<47:46\> = Reserved.
4772 \<45:44\> = CCPI_ID.
4773 \<43:36\> = 0x7E.
4774 \<35:32\> = Reserved.
4775 \<31:24\> = RSL_ID.
4776 \<23:0\> = RSL register offset.
4777
4778 \<2:0\> are ignored in a store operation. */
4779 #else /* Word 0 - Little Endian */
4780 uint64_t addr : 48; /**< [ 47: 0](R/W) The address used in both the load and store operations:
4781 \<47:46\> = Reserved.
4782 \<45:44\> = CCPI_ID.
4783 \<43:36\> = NCB_ID.
4784 \<35:0\> = Address.
4785
4786 When \<43:36\> NCB_ID is RSL (0x7E) address field is defined as:
4787 \<47:46\> = Reserved.
4788 \<45:44\> = CCPI_ID.
4789 \<43:36\> = 0x7E.
4790 \<35:32\> = Reserved.
4791 \<31:24\> = RSL_ID.
4792 \<23:0\> = RSL register offset.
4793
4794 \<2:0\> are ignored in a store operation. */
4795 uint64_t ld_op : 1; /**< [ 48: 48](R/W) Operation type:
4796 0 = Store.
4797 1 = Load operation. */
4798 uint64_t ld_cmd : 2; /**< [ 50: 49](R/W) The load command sent with the read:
4799 0x0 = Load 1-bytes.
4800 0x1 = Load 2-bytes.
4801 0x2 = Load 4-bytes.
4802 0x3 = Load 8-bytes. */
4803 uint64_t nsecure : 1; /**< [ 51: 51](R/W) Nonsecure mode. Setting this bit causes the generated load or store command to be
4804 considered nonsecure. */
4805 uint64_t el : 2; /**< [ 53: 52](R/W) Execution level. This field is used to supply the execution level of the generated load
4806 or store command. */
4807 uint64_t reserved_54_55 : 2;
4808 uint64_t wr_mask : 8; /**< [ 63: 56](R/W) Mask for the data to be written. When a bit is 1, the corresponding byte will be written.
4809 The values of this field must be contiguous and for 1, 2, 4, or 8 byte operations and
4810 aligned to operation size. A value of 0 will produce unpredictable results. Field is
4811 ignored during a read (LD_OP=1). */
4812 #endif /* Word 0 - End */
4813 } s;
4814 /* struct bdk_ocx_win_cmd_s cn; */
4815 };
4816 typedef union bdk_ocx_win_cmd bdk_ocx_win_cmd_t;
4817
4818 #define BDK_OCX_WIN_CMD BDK_OCX_WIN_CMD_FUNC()
4819 static inline uint64_t BDK_OCX_WIN_CMD_FUNC(void) __attribute__ ((pure, always_inline));
BDK_OCX_WIN_CMD_FUNC(void)4820 static inline uint64_t BDK_OCX_WIN_CMD_FUNC(void)
4821 {
4822 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX))
4823 return 0x87e011000048ll;
4824 __bdk_csr_fatal("OCX_WIN_CMD", 0, 0, 0, 0, 0);
4825 }
4826
4827 #define typedef_BDK_OCX_WIN_CMD bdk_ocx_win_cmd_t
4828 #define bustype_BDK_OCX_WIN_CMD BDK_CSR_TYPE_RSL
4829 #define basename_BDK_OCX_WIN_CMD "OCX_WIN_CMD"
4830 #define device_bar_BDK_OCX_WIN_CMD 0x0 /* PF_BAR0 */
4831 #define busnum_BDK_OCX_WIN_CMD 0
4832 #define arguments_BDK_OCX_WIN_CMD -1,-1,-1,-1
4833
4834 /**
4835 * Register (RSL) ocx_win_rd_data
4836 *
4837 * OCX Window Read Data Register
4838 * For diagnostic use only. This register is the read response data associated with window
4839 * command. Reads all-ones until response is received.
4840 */
4841 union bdk_ocx_win_rd_data
4842 {
4843 uint64_t u;
4844 struct bdk_ocx_win_rd_data_s
4845 {
4846 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4847 uint64_t data : 64; /**< [ 63: 0](RO/H) Read response data. */
4848 #else /* Word 0 - Little Endian */
4849 uint64_t data : 64; /**< [ 63: 0](RO/H) Read response data. */
4850 #endif /* Word 0 - End */
4851 } s;
4852 /* struct bdk_ocx_win_rd_data_s cn; */
4853 };
4854 typedef union bdk_ocx_win_rd_data bdk_ocx_win_rd_data_t;
4855
4856 #define BDK_OCX_WIN_RD_DATA BDK_OCX_WIN_RD_DATA_FUNC()
4857 static inline uint64_t BDK_OCX_WIN_RD_DATA_FUNC(void) __attribute__ ((pure, always_inline));
BDK_OCX_WIN_RD_DATA_FUNC(void)4858 static inline uint64_t BDK_OCX_WIN_RD_DATA_FUNC(void)
4859 {
4860 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX))
4861 return 0x87e011000050ll;
4862 __bdk_csr_fatal("OCX_WIN_RD_DATA", 0, 0, 0, 0, 0);
4863 }
4864
4865 #define typedef_BDK_OCX_WIN_RD_DATA bdk_ocx_win_rd_data_t
4866 #define bustype_BDK_OCX_WIN_RD_DATA BDK_CSR_TYPE_RSL
4867 #define basename_BDK_OCX_WIN_RD_DATA "OCX_WIN_RD_DATA"
4868 #define device_bar_BDK_OCX_WIN_RD_DATA 0x0 /* PF_BAR0 */
4869 #define busnum_BDK_OCX_WIN_RD_DATA 0
4870 #define arguments_BDK_OCX_WIN_RD_DATA -1,-1,-1,-1
4871
4872 /**
4873 * Register (RSL) ocx_win_timer
4874 *
4875 * OCX Window Timer Register
4876 * Number of core clocks before untransmitted WIN request is dropped and interrupt is issued.
4877 */
4878 union bdk_ocx_win_timer
4879 {
4880 uint64_t u;
4881 struct bdk_ocx_win_timer_s
4882 {
4883 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4884 uint64_t reserved_16_63 : 48;
4885 uint64_t tout : 14; /**< [ 15: 2](R/W) Number of core clocks times four. */
4886 uint64_t tout1 : 2; /**< [ 1: 0](RO) Reserved as all-ones. */
4887 #else /* Word 0 - Little Endian */
4888 uint64_t tout1 : 2; /**< [ 1: 0](RO) Reserved as all-ones. */
4889 uint64_t tout : 14; /**< [ 15: 2](R/W) Number of core clocks times four. */
4890 uint64_t reserved_16_63 : 48;
4891 #endif /* Word 0 - End */
4892 } s;
4893 /* struct bdk_ocx_win_timer_s cn; */
4894 };
4895 typedef union bdk_ocx_win_timer bdk_ocx_win_timer_t;
4896
4897 #define BDK_OCX_WIN_TIMER BDK_OCX_WIN_TIMER_FUNC()
4898 static inline uint64_t BDK_OCX_WIN_TIMER_FUNC(void) __attribute__ ((pure, always_inline));
BDK_OCX_WIN_TIMER_FUNC(void)4899 static inline uint64_t BDK_OCX_WIN_TIMER_FUNC(void)
4900 {
4901 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX))
4902 return 0x87e011000058ll;
4903 __bdk_csr_fatal("OCX_WIN_TIMER", 0, 0, 0, 0, 0);
4904 }
4905
4906 #define typedef_BDK_OCX_WIN_TIMER bdk_ocx_win_timer_t
4907 #define bustype_BDK_OCX_WIN_TIMER BDK_CSR_TYPE_RSL
4908 #define basename_BDK_OCX_WIN_TIMER "OCX_WIN_TIMER"
4909 #define device_bar_BDK_OCX_WIN_TIMER 0x0 /* PF_BAR0 */
4910 #define busnum_BDK_OCX_WIN_TIMER 0
4911 #define arguments_BDK_OCX_WIN_TIMER -1,-1,-1,-1
4912
4913 /**
4914 * Register (RSL) ocx_win_wr_data
4915 *
4916 * OCX Window Write Data Register
4917 * For diagnostic use only. This register is typically written by hardware after accesses to the
4918 * SLI_WIN_WR_DATA register. Contains the data to write to the address located in OCX_WIN_CMD.
4919 */
4920 union bdk_ocx_win_wr_data
4921 {
4922 uint64_t u;
4923 struct bdk_ocx_win_wr_data_s
4924 {
4925 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4926 uint64_t wr_data : 64; /**< [ 63: 0](R/W) The data to be written. */
4927 #else /* Word 0 - Little Endian */
4928 uint64_t wr_data : 64; /**< [ 63: 0](R/W) The data to be written. */
4929 #endif /* Word 0 - End */
4930 } s;
4931 /* struct bdk_ocx_win_wr_data_s cn; */
4932 };
4933 typedef union bdk_ocx_win_wr_data bdk_ocx_win_wr_data_t;
4934
4935 #define BDK_OCX_WIN_WR_DATA BDK_OCX_WIN_WR_DATA_FUNC()
4936 static inline uint64_t BDK_OCX_WIN_WR_DATA_FUNC(void) __attribute__ ((pure, always_inline));
BDK_OCX_WIN_WR_DATA_FUNC(void)4937 static inline uint64_t BDK_OCX_WIN_WR_DATA_FUNC(void)
4938 {
4939 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX))
4940 return 0x87e011000040ll;
4941 __bdk_csr_fatal("OCX_WIN_WR_DATA", 0, 0, 0, 0, 0);
4942 }
4943
4944 #define typedef_BDK_OCX_WIN_WR_DATA bdk_ocx_win_wr_data_t
4945 #define bustype_BDK_OCX_WIN_WR_DATA BDK_CSR_TYPE_RSL
4946 #define basename_BDK_OCX_WIN_WR_DATA "OCX_WIN_WR_DATA"
4947 #define device_bar_BDK_OCX_WIN_WR_DATA 0x0 /* PF_BAR0 */
4948 #define busnum_BDK_OCX_WIN_WR_DATA 0
4949 #define arguments_BDK_OCX_WIN_WR_DATA -1,-1,-1,-1
4950
4951 #endif /* __BDK_CSRS_OCX_H__ */
4952