1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <amdblocks/cpu.h>
4 #include <amdblocks/smm.h>
5 #include <commonlib/helpers.h>
6 #include <console/console.h>
7 #include <cpu/amd/microcode.h>
8 #include <cpu/amd/msr.h>
9 #include <cpu/amd/mtrr.h>
10 #include <cpu/cpu.h>
11 #include <cpu/x86/cache.h>
12 #include <cpu/x86/msr.h>
13 #include <cpu/x86/mtrr.h>
14 #include <device/device.h>
15 #include <device/pci.h>
16 #include <smp/node.h>
17
model_16_init(struct device * dev)18 static void model_16_init(struct device *dev)
19 {
20 printk(BIOS_DEBUG, "Model 16 Init.\n");
21
22 msr_t msr;
23 u32 siblings;
24
25 /* zero the machine check error status registers */
26 mca_clear_status();
27
28 siblings = get_cpu_count() - 1; // minus BSP
29
30 if (siblings > 0) {
31 msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
32 msr.lo |= 1 << 28;
33 wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
34
35 msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
36 msr.hi |= 1 << (33 - 32);
37 wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
38 }
39 printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
40
41 /* DisableCf8ExtCfg */
42 msr = rdmsr(NB_CFG_MSR);
43 msr.hi &= ~(1 << (46 - 32));
44 wrmsr(NB_CFG_MSR, msr);
45
46 /* Write protect SMM space with SMMLOCK. */
47 lock_smm();
48
49 amd_update_microcode_from_cbfs();
50
51 display_mtrrs();
52 }
53
54 static struct device_operations cpu_dev_ops = {
55 .init = model_16_init,
56 };
57
58 static const struct cpu_device_id cpu_table[] = {
59 { X86_VENDOR_AMD, CPUID_FROM_FMS(0x16, 0x30, 0), CPUID_ALL_STEPPINGS_MASK },
60 CPU_TABLE_END
61 };
62
63 static const struct cpu_driver model_16 __cpu_driver = {
64 .ops = &cpu_dev_ops,
65 .id_table = cpu_table,
66 };
67