1 /* 2 * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * This file is limited to include the trusted firmware required platform port 7 * definitions for the second generation platforms based on the N2/V2 CPUs. The 8 * common platform support for Arm platforms expect platforms to define certain 9 * definitions and those definitions are referred to as the platform port 10 * definitions. 11 */ 12 13 #ifndef NRD_PLAT_ARM_DEF2_H 14 #define NRD_PLAT_ARM_DEF2_H 15 16 #ifndef __ASSEMBLER__ 17 #include <lib/mmio.h> 18 #endif /* __ASSEMBLER__ */ 19 20 #include <plat/arm/common/arm_def.h> 21 #include <plat/arm/common/arm_spm_def.h> 22 #include <plat/arm/css/common/css_def.h> 23 #include <nrd_css_fw_def2.h> 24 #include <nrd_ros_fw_def2.h> 25 26 /******************************************************************************* 27 * Core count 28 ******************************************************************************/ 29 30 #define PLATFORM_CORE_COUNT (NRD_CHIP_COUNT * \ 31 PLAT_ARM_CLUSTER_COUNT * \ 32 NRD_MAX_CPUS_PER_CLUSTER * \ 33 NRD_MAX_PE_PER_CPU) 34 35 #if (NRD_PLATFORM_VARIANT == 1) 36 #define PLAT_ARM_CLUSTER_COUNT U(8) 37 #elif (NRD_PLATFORM_VARIANT == 2) 38 #define PLAT_ARM_CLUSTER_COUNT U(4) 39 #else 40 #define PLAT_ARM_CLUSTER_COUNT U(16) 41 #endif 42 43 /******************************************************************************* 44 * PA/VA config 45 ******************************************************************************/ 46 47 #ifdef __aarch64__ 48 #define PLAT_PHY_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \ 49 NRD_CHIP_COUNT) 50 #define PLAT_VIRT_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \ 51 NRD_CHIP_COUNT) 52 #else 53 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 54 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 55 #endif 56 57 /******************************************************************************* 58 * XLAT definitions 59 ******************************************************************************/ 60 61 #if defined(IMAGE_BL31) 62 # if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) 63 # define PLAT_ARM_MMAP_ENTRIES (10 + ((NRD_CHIP_COUNT - 1) * 3)) 64 # define MAX_XLAT_TABLES (8 + ((NRD_CHIP_COUNT - 1) * 3)) 65 # define PLAT_SP_IMAGE_MMAP_REGIONS U(12) 66 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES U(14) 67 # else 68 # define PLAT_ARM_MMAP_ENTRIES (5 + ((NRD_CHIP_COUNT - 1) * 3)) 69 # define MAX_XLAT_TABLES (6 + ((NRD_CHIP_COUNT - 1) * 3)) 70 # endif 71 #elif defined(IMAGE_BL32) 72 # define PLAT_ARM_MMAP_ENTRIES U(8) 73 # define MAX_XLAT_TABLES U(5) 74 #elif defined(IMAGE_BL2) 75 # define PLAT_ARM_MMAP_ENTRIES (11 + (NRD_CHIP_COUNT - 1)) 76 77 /* 78 * MAX_XLAT_TABLES entries need to be doubled because when the address width 79 * exceeds 40 bits an additional level of translation is required. In case of 80 * multichip platforms peripherals also fall into address space with width 81 * > 40 bits 82 * 83 */ 84 # define MAX_XLAT_TABLES (7 + ((NRD_CHIP_COUNT - 1) * 2)) 85 #elif !USE_ROMLIB 86 # define PLAT_ARM_MMAP_ENTRIES U(11) 87 # define MAX_XLAT_TABLES U(7) 88 #else 89 # define PLAT_ARM_MMAP_ENTRIES U(12) 90 # define MAX_XLAT_TABLES U(6) 91 #endif 92 93 /******************************************************************************* 94 * BL sizes 95 ******************************************************************************/ 96 97 /* 98 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 99 */ 100 101 #if USE_ROMLIB 102 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 103 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 104 #else 105 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 106 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 107 #endif 108 109 #define PLAT_ARM_MAX_BL1_RW_SIZE NRD_CSS_BL1_RW_SIZE 110 111 /* 112 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 113 * little space for growth. Additional 8KiB space is added per chip in 114 * order to accommodate the additional level of translation required for "TZC" 115 * peripheral access which lies in >4TB address space. 116 * 117 */ 118 #define PLAT_ARM_MAX_BL2_SIZE (NRD_CSS_BL2_SIZE + \ 119 ((NRD_CHIP_COUNT - 1) * 0x2000)) 120 121 #define PLAT_ARM_MAX_BL31_SIZE (NRD_CSS_BL31_SIZE + \ 122 PLAT_ARM_MAX_BL2_SIZE + \ 123 PLAT_ARM_MAX_BL1_RW_SIZE) 124 125 /******************************************************************************* 126 * Stack sizes 127 ******************************************************************************/ 128 129 #if defined(IMAGE_BL1) 130 # if TRUSTED_BOARD_BOOT 131 # define PLATFORM_STACK_SIZE UL(0x1000) 132 # else 133 # define PLATFORM_STACK_SIZE UL(0x440) 134 # endif 135 #elif defined(IMAGE_BL2) 136 # if TRUSTED_BOARD_BOOT 137 # define PLATFORM_STACK_SIZE UL(0x1000) 138 # else 139 # define PLATFORM_STACK_SIZE UL(0x400) 140 # endif 141 #elif defined(IMAGE_BL2U) 142 # define PLATFORM_STACK_SIZE UL(0x400) 143 #elif defined(IMAGE_BL31) 144 # if SPM_MM 145 # define PLATFORM_STACK_SIZE UL(0x500) 146 # else 147 # define PLATFORM_STACK_SIZE UL(0x400) 148 # endif 149 #elif defined(IMAGE_BL32) 150 # define PLATFORM_STACK_SIZE UL(0x440) 151 #endif 152 153 #if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)) && \ 154 ENABLE_FEAT_RAS && FFH_SUPPORT 155 /* 156 * Secure partition stack follows right after the memory space reserved for 157 * CPER buffer memory. 158 */ 159 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 160 PLAT_SP_IMAGE_NS_BUF_SIZE + \ 161 NRD_CSS_SP_CPER_BUF_SIZE) 162 #elif (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)) 163 /* 164 * Secure partition stack follows right after the memory region that is shared 165 * between EL3 and S-EL0. 166 */ 167 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 168 PLAT_SP_IMAGE_NS_BUF_SIZE) 169 #endif /* SPM_MM && ENABLE_FEAT_RAS && FFH_SUPPORT */ 170 171 /******************************************************************************* 172 * Console config 173 ******************************************************************************/ 174 175 #define PLAT_ARM_BOOT_UART_BASE NRD_CSS_SEC_UART_BASE 176 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ 177 178 #define PLAT_ARM_RUN_UART_BASE NRD_CSS_SEC_UART_BASE 179 #define PLAT_ARM_RUN_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ 180 181 #define PLAT_ARM_CRASH_UART_BASE NRD_CSS_SEC_UART_BASE 182 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ 183 184 /******************************************************************************* 185 * SCMI config 186 ******************************************************************************/ 187 188 /* Number of SCMI channels on the platform */ 189 #define PLAT_ARM_SCMI_CHANNEL_COUNT NRD_CHIP_COUNT 190 191 /******************************************************************************* 192 * ROM, SRAM and DRAM config 193 ******************************************************************************/ 194 195 #define PLAT_ARM_TRUSTED_ROM_BASE NRD_CSS_SECURE_ROM_BASE 196 #define PLAT_ARM_TRUSTED_ROM_SIZE NRD_CSS_SECURE_ROM_SIZE 197 198 #define PLAT_ARM_DRAM2_BASE NRD_CSS_DRAM2_BASE 199 #define PLAT_ARM_DRAM2_SIZE NRD_CSS_DRAM2_SIZE 200 201 #define PLAT_ARM_TRUSTED_SRAM_SIZE NRD_CSS_SECURE_SRAM_SIZE 202 203 #define PLAT_ARM_NSTIMER_FRAME_ID 0 204 205 #define PLAT_ARM_NSRAM_BASE NRD_CSS_NS_SRAM_BASE 206 #define PLAT_ARM_NSRAM_SIZE NRD_CSS_NS_SRAM_SIZE 207 /* 208 * Required platform porting definitions common to all ARM CSS SoCs 209 */ 210 /* 2MB used for SCP DDR retraining */ 211 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x00200000) 212 213 /******************************************************************************* 214 * GIC/EHF config 215 ******************************************************************************/ 216 217 /* GIC related constants */ 218 #define PLAT_ARM_GICD_BASE NRD_CSS_GIC_BASE 219 220 #if (NRD_PLATFORM_VARIANT == 1) 221 #define PLAT_ARM_GICR_BASE NRD_CSS_GIC_BASE + UL(0x00100000) 222 #elif (NRD_PLATFORM_VARIANT == 3) 223 #define PLAT_ARM_GICR_BASE NRD_CSS_GIC_BASE + UL(0x00300000) 224 #else 225 #define PLAT_ARM_GICR_BASE NRD_CSS_GIC_BASE + UL(0x001C0000) 226 #endif 227 228 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) 229 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 230 231 #if ENABLE_FEAT_RAS && FFH_SUPPORT 232 #define PLAT_SP_PRI PLAT_RAS_PRI 233 #else 234 #define PLAT_SP_PRI (0x10) 235 #endif 236 237 /* Interrupt priority level for shutdown/reboot */ 238 #define PLAT_REBOOT_PRI GIC_HIGHEST_SEC_PRIORITY 239 #define PLAT_EHF_DESC EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_REBOOT_PRI) 240 241 /******************************************************************************* 242 * Secure world config 243 ******************************************************************************/ 244 245 #define SECURE_PARTITION_COUNT 1 246 #define NS_PARTITION_COUNT 1 247 #define MAX_EL3_LP_DESCS_COUNT 1 248 249 /******************************************************************************* 250 * MHU config 251 ******************************************************************************/ 252 253 #define PLAT_CSS_MHU_BASE NRD_CSS_AP_SCP_S_MHU_BASE 254 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 255 256 /******************************************************************************* 257 * Power config 258 ******************************************************************************/ 259 260 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 261 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 262 263 /******************************************************************************* 264 * TZ config 265 ******************************************************************************/ 266 267 #define PLAT_ARM_TZC_BASE NRD_ROS_MEMCNTRL_BASE + UL(0x00720000) 268 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 269 270 /******************************************************************************* 271 * SDS config 272 ******************************************************************************/ 273 274 /* SDS ID for unusable CPU MPID list structure */ 275 #define SDS_ISOLATED_CPU_LIST_ID U(128) 276 277 /* Index of SDS region used in the communication with SCP */ 278 #define SDS_SCP_AP_REGION_ID U(0) 279 280 /******************************************************************************* 281 * Flash config 282 ******************************************************************************/ 283 284 #define MAX_IO_DEVICES U(3) 285 #define MAX_IO_HANDLES U(4) 286 287 #define V2M_SYS_LED U(0x8) 288 289 #define V2M_SYS_LED_SS_SHIFT U(0) 290 #define V2M_SYS_LED_EL_SHIFT U(1) 291 #define V2M_SYS_LED_EC_SHIFT U(3) 292 293 #define V2M_SYS_LED_SS_MASK U(0x01) 294 #define V2M_SYS_LED_EL_MASK U(0x03) 295 #define V2M_SYS_LED_EC_MASK U(0x1f) 296 297 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000) 298 299 #define V2M_SYSREGS_BASE NRD_ROS_SYSTEM_PERIPH_BASE + \ 300 UL(0x00010000) 301 #define V2M_FLASH0_BASE NRD_ROS_SMC0_BASE 302 #define V2M_FLASH0_SIZE NRD_ROS_SMC0_SIZE 303 #define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */ 304 305 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 306 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 307 308 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 309 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 310 311 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 312 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 313 314 /******************************************************************************* 315 * Platform type identification macro 316 ******************************************************************************/ 317 318 /* Platform ID related accessors */ 319 #define BOARD_CSS_PLAT_ID_REG_ID_MASK U(0x0F) 320 #define BOARD_CSS_PLAT_ID_REG_ID_SHIFT U(0x00) 321 #define BOARD_CSS_PLAT_ID_REG_VERSION_MASK U(0xF00) 322 #define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT U(0x08) 323 #define BOARD_CSS_PLAT_TYPE_RTL U(0x00) 324 #define BOARD_CSS_PLAT_TYPE_FPGA U(0x01) 325 #define BOARD_CSS_PLAT_TYPE_EMULATOR U(0x02) 326 #define BOARD_CSS_PLAT_TYPE_FVP U(0x03) 327 328 #ifndef __ASSEMBLER__ 329 #define BOARD_CSS_GET_PLAT_TYPE(addr) \ 330 ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \ 331 >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT) 332 #endif /* __ASSEMBLER__ */ 333 334 /* Platform ID address */ 335 #define BOARD_CSS_PLAT_ID_REG_ADDR NRD_ROS_PLATFORM_PERIPH_BASE + \ 336 UL(0x00FE00E0) 337 338 /******************************************************************************* 339 * ROS peripheral config 340 ******************************************************************************/ 341 342 /* Non-volatile counters */ 343 #define SOC_TRUSTED_NVCTR_BASE NRD_ROS_PLATFORM_PERIPH_BASE + \ 344 UL(0x00E70000) 345 #define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0000) 346 #define TFW_NVCTR_SIZE U(4) 347 #define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004) 348 #define NTFW_CTR_SIZE U(4) 349 350 /******************************************************************************* 351 * MMU config 352 ******************************************************************************/ 353 354 #define V2M_MAP_FLASH0_RW \ 355 MAP_REGION_FLAT( \ 356 V2M_FLASH0_BASE, \ 357 V2M_FLASH0_SIZE, \ 358 MT_DEVICE | MT_RW | MT_SECURE) 359 360 #define V2M_MAP_FLASH0_RO \ 361 MAP_REGION_FLAT( \ 362 V2M_FLASH0_BASE, \ 363 V2M_FLASH0_SIZE, \ 364 MT_RO_DATA | MT_SECURE) 365 366 #endif /* NRD_PLAT_ARM_DEF2_H */ 367