1 /* 2 * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * This file is limited to include the RoS firmware specific definitions for the 7 * second generation platforms based on the N2/V2 CPUs. RoS (Rest Of System) is 8 * used to refer to the part of the reference design platform that excludes CSS. 9 */ 10 11 #ifndef NRD_ROS_FW_DEF2_H 12 #define NRD_ROS_FW_DEF2_H 13 14 #include <nrd_ros_def2.h> 15 16 /******************************************************************************* 17 * MMU mapping 18 ******************************************************************************/ 19 20 #define NRD_ROS_PLATFORM_PERIPH_MMAP \ 21 MAP_REGION_FLAT( \ 22 NRD_ROS_PLATFORM_PERIPH_BASE, \ 23 NRD_ROS_PLATFORM_PERIPH_SIZE, \ 24 MT_DEVICE | MT_RW | MT_SECURE) 25 26 #if SPM_MM 27 28 #define NRD_ROS_PLATFORM_PERIPH_USER_MMAP \ 29 MAP_REGION_FLAT( \ 30 NRD_ROS_PLATFORM_PERIPH_BASE, \ 31 NRD_ROS_PLATFORM_PERIPH_SIZE, \ 32 MT_DEVICE | MT_RW | MT_SECURE | MT_USER) 33 #endif 34 35 #define NRD_ROS_SYSTEM_PERIPH_MMAP \ 36 MAP_REGION_FLAT( \ 37 NRD_ROS_SYSTEM_PERIPH_BASE, \ 38 NRD_ROS_SYSTEM_PERIPH_SIZE, \ 39 MT_DEVICE | MT_RW | MT_SECURE) 40 41 #define NRD_ROS_MEMCNTRL_MMAP(n) \ 42 MAP_REGION_FLAT( \ 43 NRD_REMOTE_CHIP_MEM_OFFSET(n) + \ 44 NRD_ROS_MEMCNTRL_BASE, \ 45 NRD_ROS_MEMCNTRL_SIZE, \ 46 MT_DEVICE | MT_RW | MT_SECURE) 47 48 #define NRD_ROS_SECURE_SYSTEMREG_USER_MMAP \ 49 MAP_REGION_FLAT( \ 50 NRD_ROS_SYSTEMREG_BASE, \ 51 NRD_ROS_SYSTEMREG_SIZE, \ 52 MT_DEVICE | MT_RW | MT_SECURE | MT_USER) 53 54 #define NRD_ROS_SECURE_NOR2_USER_MMAP \ 55 MAP_REGION_FLAT( \ 56 NRD_ROS_NOR2_FLASH_BASE, \ 57 NRD_ROS_NOR2_FLASH_SIZE, \ 58 MT_DEVICE | MT_RW | MT_SECURE | MT_USER) 59 60 61 #define NRD_ROS_FLASH0_RO_MMAP \ 62 MAP_REGION_FLAT( \ 63 V2M_FLASH0_BASE, \ 64 V2M_FLASH0_SIZE, \ 65 MT_DEVICE | MT_RO | MT_SECURE) 66 67 /******************************************************************************* 68 * TZ config 69 ******************************************************************************/ 70 71 /* 72 * Mapping definition of the TrustZone Controller for Arm Neoverse RD platforms 73 * where both the DRAM regions are marked for non-secure access. This applies 74 * to multi-chip platforms. 75 */ 76 #define NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(n) \ 77 {NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE, \ 78 NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END, \ 79 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 80 {NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE, \ 81 NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END, \ 82 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS} 83 84 #endif /* NRD_ROS_FW_DEF2_H */ 85