1 /*
2 * Copyright (c) 2019-2024, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
4 * Copyright (c) 2024, Altera Corporation. All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include <assert.h>
10 #include <arch.h>
11 #include <arch_helpers.h>
12 #include <common/bl_common.h>
13 #include <drivers/arm/gic_common.h>
14 #include <drivers/arm/gicv3.h>
15 #include <drivers/ti/uart/uart_16550.h>
16 #include <lib/mmio.h>
17 #include <lib/xlat_tables/xlat_mmu_helpers.h>
18 #include <lib/xlat_tables/xlat_tables_v2.h>
19 #include <plat/common/platform.h>
20
21 #include "agilex5_cache.h"
22 #include "agilex5_power_manager.h"
23 #include "ccu/ncore_ccu.h"
24 #include "socfpga_mailbox.h"
25 #include "socfpga_private.h"
26 #include "socfpga_reset_manager.h"
27
28 /* Get non-secure SPSR for BL33. Zephyr and Linux */
29 uint32_t arm_get_spsr_for_bl33_entry(void);
30
31 static entry_point_info_t bl32_image_ep_info;
32 static entry_point_info_t bl33_image_ep_info;
33
34 /* The GICv3 driver only needs to be initialized in EL3 */
35 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
36
37 #define SMMU_SDMMC
38
bl31_plat_get_next_image_ep_info(uint32_t type)39 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
40 {
41 entry_point_info_t *next_image_info;
42
43 next_image_info = (type == NON_SECURE) ?
44 &bl33_image_ep_info : &bl32_image_ep_info;
45
46 /* None of the images on this platform can have 0x0 as the entrypoint */
47 if (next_image_info->pc)
48 return next_image_info;
49 else
50 return NULL;
51 }
52
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)53 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
54 u_register_t arg2, u_register_t arg3)
55 {
56 static console_t console;
57
58 mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
59
60 console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
61 PLAT_BAUDRATE, &console);
62
63 setup_smmu_stream_id();
64
65 /*
66 * Check params passed from BL31 should not be NULL,
67 */
68 void *from_bl2 = (void *) arg0;
69
70 #if RESET_TO_BL31
71 /* There are no parameters from BL2 if BL31 is a reset vector */
72 assert(from_bl2 == NULL);
73 void *plat_params_from_bl2 = (void *) arg3;
74
75 assert(plat_params_from_bl2 == NULL);
76
77 /* Populate entry point information for BL33 */
78 SET_PARAM_HEAD(&bl33_image_ep_info,
79 PARAM_EP,
80 VERSION_1,
81 0);
82
83 # if ARM_LINUX_KERNEL_AS_BL33
84 /*
85 * According to the file ``Documentation/arm64/booting.txt`` of the
86 * Linux kernel tree, Linux expects the physical address of the device
87 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
88 * must be 0.
89 */
90 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
91 bl33_image_ep_info.args.arg1 = 0U;
92 bl33_image_ep_info.args.arg2 = 0U;
93 bl33_image_ep_info.args.arg3 = 0U;
94 # endif
95
96 #else /* RESET_TO_BL31 */
97 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
98
99 assert(params_from_bl2 != NULL);
100
101 /*
102 * Copy BL32 (if populated by BL31) and BL33 entry point information.
103 * They are stored in Secure RAM, in BL31's address space.
104 */
105
106 if (params_from_bl2->h.type == PARAM_BL_PARAMS &&
107 params_from_bl2->h.version >= VERSION_2) {
108
109 bl_params_node_t *bl_params = params_from_bl2->head;
110
111 while (bl_params) {
112 if (bl_params->image_id == BL33_IMAGE_ID) {
113 bl33_image_ep_info = *bl_params->ep_info;
114 }
115 bl_params = bl_params->next_params_info;
116 }
117 } else {
118 struct socfpga_bl31_params *arg_from_bl2 =
119 (struct socfpga_bl31_params *) from_bl2;
120
121 assert(arg_from_bl2->h.type == PARAM_BL31);
122 assert(arg_from_bl2->h.version >= VERSION_1);
123
124 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
125 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
126 }
127
128 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
129 bl33_image_ep_info.args.arg1 = 0U;
130 bl33_image_ep_info.args.arg2 = 0U;
131 bl33_image_ep_info.args.arg3 = 0U;
132 #endif
133
134 /*
135 * Tell BL31 where the non-trusted software image
136 * is located and the entry state information
137 */
138 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
139 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
140
141 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
142 }
143
144 static const interrupt_prop_t agx5_interrupt_props[] = {
145 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(INTR_GROUP1S),
146 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(INTR_GROUP0)
147 };
148
149 static const gicv3_driver_data_t plat_gicv3_gic_data = {
150 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE,
151 .gicr_base = PLAT_INTEL_SOCFPGA_GICR_BASE,
152 .interrupt_props = agx5_interrupt_props,
153 .interrupt_props_num = ARRAY_SIZE(agx5_interrupt_props),
154 .rdistif_num = PLATFORM_CORE_COUNT,
155 .rdistif_base_addrs = rdistif_base_addrs,
156 };
157
158 /*******************************************************************************
159 * Perform any BL3-1 platform setup code
160 ******************************************************************************/
bl31_platform_setup(void)161 void bl31_platform_setup(void)
162 {
163 socfpga_delay_timer_init();
164
165 /* Initialize the gic cpu and distributor interfaces */
166 gicv3_driver_init(&plat_gicv3_gic_data);
167 gicv3_distif_init();
168 gicv3_rdistif_init(plat_my_core_pos());
169 gicv3_cpuif_enable(plat_my_core_pos());
170 mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
171 }
172
173 const mmap_region_t plat_agilex_mmap[] = {
174 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
175 MAP_REGION_FLAT(PSS_BASE, PSS_SIZE, MT_DEVICE | MT_RW | MT_NS),
176 MAP_REGION_FLAT(MPFE_BASE, MPFE_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
177 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, MT_NON_CACHEABLE | MT_RW | MT_SECURE),
178 MAP_REGION_FLAT(CCU_BASE, CCU_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
179 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS),
180 MAP_REGION_FLAT(GIC_BASE, GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
181 {0}
182 };
183
184 /*******************************************************************************
185 * Perform the very early platform specific architectural setup here. At the
186 * moment this is only initializes the mmu in a quick and dirty way.
187 ******************************************************************************/
bl31_plat_arch_setup(void)188 void bl31_plat_arch_setup(void)
189 {
190 uint32_t boot_core = 0x00;
191 uint32_t cpuid = 0x00;
192
193 cpuid = MPIDR_AFFLVL1_VAL(read_mpidr());
194 boot_core = ((mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00) >> 10);
195 NOTICE("BL31: Boot Core = %x\n", boot_core);
196 NOTICE("BL31: CPU ID = %x\n", cpuid);
197 INFO("BL31: Invalidate Data cache\n");
198 invalidate_dcache_all();
199 }
200
201 /* Get non-secure image entrypoint for BL33. Zephyr and Linux */
plat_get_ns_image_entrypoint(void)202 uintptr_t plat_get_ns_image_entrypoint(void)
203 {
204 #ifdef PRELOADED_BL33_BASE
205 return PRELOADED_BL33_BASE;
206 #else
207 return PLAT_NS_IMAGE_OFFSET;
208 #endif
209 }
210
211 /* Get non-secure SPSR for BL33. Zephyr and Linux */
arm_get_spsr_for_bl33_entry(void)212 uint32_t arm_get_spsr_for_bl33_entry(void)
213 {
214 unsigned int mode;
215 uint32_t spsr;
216
217 /* Figure out what mode we enter the non-secure world in */
218 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
219
220 /*
221 * TODO: Consider the possibility of specifying the SPSR in
222 * the FIP ToC and allowing the platform to have a say as
223 * well.
224 */
225 spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
226 return spsr;
227 }
228
229 /* SMP: Secondary cores BL31 setup reset vector */
bl31_plat_set_secondary_cpu_entrypoint(unsigned int cpu_id)230 void bl31_plat_set_secondary_cpu_entrypoint(unsigned int cpu_id)
231 {
232 unsigned int pch_cpu = 0x00;
233 unsigned int pchctlr_old = 0x00;
234 unsigned int pchctlr_new = 0x00;
235 uint32_t boot_core = 0x00;
236
237 /* Store magic number for SMP secondary cores boot */
238 mmio_write_32(L2_RESET_DONE_REG, SMP_SEC_CORE_BOOT_REQ);
239
240 boot_core = (mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00);
241 /* Update the p-channel based on cpu id */
242 pch_cpu = 1 << cpu_id;
243
244 if (boot_core == 0x00) {
245 /* Update reset vector to 0x00 */
246 mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU2,
247 (uint64_t) plat_secondary_cpus_bl31_entry >> 2);
248 } else {
249 /* Update reset vector to 0x00 */
250 mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU0,
251 (uint64_t) plat_secondary_cpus_bl31_entry >> 2);
252 }
253
254 /* Update reset vector to 0x00 */
255 mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU1, (uint64_t) plat_secondary_cpus_bl31_entry >> 2);
256 mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU3, (uint64_t) plat_secondary_cpus_bl31_entry >> 2);
257
258 /* On all cores - temporary */
259 pchctlr_old = mmio_read_32(AGX5_PWRMGR(MPU_PCHCTLR));
260 pchctlr_new = pchctlr_old | (pch_cpu<<1);
261 mmio_write_32(AGX5_PWRMGR(MPU_PCHCTLR), pchctlr_new);
262
263 /* We will only release the target secondary CPUs */
264 /* Bit mask for each CPU BIT0-3 */
265 mmio_write_32(RSTMGR_CPUSTRELEASE_CPUx, pch_cpu);
266 }
267
bl31_plat_set_secondary_cpu_off(void)268 void bl31_plat_set_secondary_cpu_off(void)
269 {
270 unsigned int pch_cpu = 0x00;
271 unsigned int pch_cpu_off = 0x00;
272 unsigned int cpu_id = plat_my_core_pos();
273
274 pch_cpu_off = 1 << cpu_id;
275
276 pch_cpu = mmio_read_32(AGX5_PWRMGR(MPU_PCHCTLR));
277 pch_cpu = pch_cpu & ~(pch_cpu_off << 1);
278
279 mmio_write_32(AGX5_PWRMGR(MPU_PCHCTLR), pch_cpu);
280 }
281
bl31_plat_enable_mmu(uint32_t flags)282 void bl31_plat_enable_mmu(uint32_t flags)
283 {
284 /* TODO: Enable mmu when needed */
285 }
286