1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __MAINBOARD_EMU_Q35_H__ 4 #define __MAINBOARD_EMU_Q35_H__ 5 6 #include <device/pci_type.h> 7 #include <types.h> 8 9 #define HOST_BRIDGE PCI_DEV(0, 0, 0) 10 11 #define D0F0_PCIEXBAR_LO 0x60 12 #define D0F0_PCIEXBAR_HI 0x64 13 14 #define D0F0_PAM(x) (0x90 + (x)) /* 0-6 */ 15 16 #define SMRAMC 0x9d 17 #define G_SMRAME (1 << 3) 18 #define D_LCK (1 << 4) 19 #define D_CLS (1 << 5) 20 #define D_OPEN (1 << 6) 21 22 #define ESMRAMC 0x9e 23 #define T_EN (1 << 0) 24 #define TSEG_SZ_MASK (3 << 1) 25 #define H_SMRAME (1 << 7) 26 27 uint32_t make_pciexbar(void); 28 29 void mainboard_machine_check(void); 30 31 #endif 32