1 // SPDX-License-Identifier: MIT 2 #ifndef R600_FORMATS_H 3 #define R600_FORMATS_H 4 5 #include "util/format/u_format.h" 6 #include "util/u_endian.h" 7 8 /* list of formats from R700 ISA document - apply across GPUs in different registers */ 9 #define FMT_INVALID 0x00000000 10 #define FMT_8 0x00000001 11 #define FMT_4_4 0x00000002 12 #define FMT_3_3_2 0x00000003 13 #define FMT_16 0x00000005 14 #define FMT_16_FLOAT 0x00000006 15 #define FMT_8_8 0x00000007 16 #define FMT_5_6_5 0x00000008 17 #define FMT_6_5_5 0x00000009 18 #define FMT_1_5_5_5 0x0000000A 19 #define FMT_4_4_4_4 0x0000000B 20 #define FMT_5_5_5_1 0x0000000C 21 #define FMT_32 0x0000000D 22 #define FMT_32_FLOAT 0x0000000E 23 #define FMT_16_16 0x0000000F 24 #define FMT_16_16_FLOAT 0x00000010 25 #define FMT_8_24 0x00000011 26 #define FMT_8_24_FLOAT 0x00000012 27 #define FMT_24_8 0x00000013 28 #define FMT_24_8_FLOAT 0x00000014 29 #define FMT_10_11_11 0x00000015 30 #define FMT_10_11_11_FLOAT 0x00000016 31 #define FMT_11_11_10 0x00000017 32 #define FMT_11_11_10_FLOAT 0x00000018 33 #define FMT_2_10_10_10 0x00000019 34 #define FMT_8_8_8_8 0x0000001A 35 #define FMT_10_10_10_2 0x0000001B 36 #define FMT_X24_8_32_FLOAT 0x0000001C 37 #define FMT_32_32 0x0000001D 38 #define FMT_32_32_FLOAT 0x0000001E 39 #define FMT_16_16_16_16 0x0000001F 40 #define FMT_16_16_16_16_FLOAT 0x00000020 41 #define FMT_32_32_32_32 0x00000022 42 #define FMT_32_32_32_32_FLOAT 0x00000023 43 #define FMT_1 0x00000025 44 #define FMT_1_REVERSED 0x00000026 45 #define FMT_GB_GR 0x00000027 46 #define FMT_BG_RG 0x00000028 47 #define FMT_32_AS_8 0x00000029 48 #define FMT_32_AS_8_8 0x0000002a 49 #define FMT_5_9_9_9_SHAREDEXP 0x0000002b 50 #define FMT_8_8_8 0x0000002c 51 #define FMT_16_16_16 0x0000002d 52 #define FMT_16_16_16_FLOAT 0x0000002e 53 #define FMT_32_32_32 0x0000002f 54 #define FMT_32_32_32_FLOAT 0x00000030 55 #define FMT_BC1 0x00000031 56 #define FMT_BC2 0x00000032 57 #define FMT_BC3 0x00000033 58 #define FMT_BC4 0x00000034 59 #define FMT_BC5 0x00000035 60 #define FMT_BC6 0x00000036 61 #define FMT_BC7 0x00000037 62 #define FMT_32_AS_32_32_32_32 0x00000038 63 64 #define ENDIAN_NONE 0 65 #define ENDIAN_8IN16 1 66 #define ENDIAN_8IN32 2 67 #define ENDIAN_8IN64 3 68 r600_endian_swap(unsigned size)69static inline unsigned r600_endian_swap(unsigned size) 70 { 71 if (UTIL_ARCH_BIG_ENDIAN) { 72 switch (size) { 73 case 64: 74 return ENDIAN_8IN64; 75 case 32: 76 return ENDIAN_8IN32; 77 case 16: 78 return ENDIAN_8IN16; 79 default: 80 return ENDIAN_NONE; 81 } 82 } else { 83 return ENDIAN_NONE; 84 } 85 } 86 r600_is_buffer_format_supported(enum pipe_format format,bool for_vbo)87static inline bool r600_is_buffer_format_supported(enum pipe_format format, bool for_vbo) 88 { 89 const struct util_format_description *desc = util_format_description(format); 90 unsigned i; 91 92 if (format == PIPE_FORMAT_R11G11B10_FLOAT) 93 return true; 94 95 i = util_format_get_first_non_void_channel(format); 96 if (i == -1) 97 return false; 98 99 /* No fixed, no double. */ 100 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN || 101 (desc->channel[i].size == 64 && 102 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) || 103 desc->channel[i].type == UTIL_FORMAT_TYPE_FIXED) 104 return false; 105 106 /* No scaled/norm formats with 32 bits per channel. */ 107 if (desc->channel[i].size == 32 && 108 !desc->channel[i].pure_integer && 109 (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED || 110 desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED)) 111 return false; 112 113 /* No 8 bit 3 channel formats for TBOs */ 114 if (desc->channel[i].size == 8 && desc->nr_channels == 3) 115 return for_vbo; 116 117 return true; 118 } 119 r600_is_index_format_supported(enum pipe_format format)120static inline bool r600_is_index_format_supported(enum pipe_format format) 121 { 122 switch (format) { 123 case PIPE_FORMAT_R8_UINT: 124 case PIPE_FORMAT_R16_UINT: 125 case PIPE_FORMAT_R32_UINT: 126 return true; 127 128 default: 129 return false; 130 } 131 } 132 133 #endif 134