1 /**************************************************************************
2 *
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 **************************************************************************/
8
9 #include "pipe/p_video_codec.h"
10 #include "radeon_uvd_enc.h"
11 #include "radeon_video.h"
12 #include "radeon_bitstream.h"
13 #include "radeonsi/si_pipe.h"
14 #include "util/u_memory.h"
15 #include "util/u_video.h"
16 #include "vl/vl_video_buffer.h"
17
18 #include <stdio.h>
19
20 #define RADEON_ENC_CS(value) (enc->cs.current.buf[enc->cs.current.cdw++] = (value))
21 #define RADEON_ENC_BEGIN(cmd) \
22 { \
23 uint32_t *begin = &enc->cs.current.buf[enc->cs.current.cdw++]; \
24 RADEON_ENC_CS(cmd)
25 #define RADEON_ENC_READ(buf, domain, off) \
26 radeon_uvd_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
27 #define RADEON_ENC_WRITE(buf, domain, off) \
28 radeon_uvd_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
29 #define RADEON_ENC_READWRITE(buf, domain, off) \
30 radeon_uvd_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
31 #define RADEON_ENC_END() \
32 *begin = (&enc->cs.current.buf[enc->cs.current.cdw] - begin) * 4; \
33 enc->total_task_size += *begin; \
34 }
35
radeon_uvd_enc_add_buffer(struct radeon_uvd_encoder * enc,struct pb_buffer_lean * buf,unsigned usage,enum radeon_bo_domain domain,signed offset)36 static void radeon_uvd_enc_add_buffer(struct radeon_uvd_encoder *enc, struct pb_buffer_lean *buf,
37 unsigned usage, enum radeon_bo_domain domain,
38 signed offset)
39 {
40 enc->ws->cs_add_buffer(&enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
41 uint64_t addr;
42 addr = enc->ws->buffer_get_virtual_address(buf);
43 addr = addr + offset;
44 RADEON_ENC_CS(addr >> 32);
45 RADEON_ENC_CS(addr);
46 }
47
radeon_uvd_enc_session_info(struct radeon_uvd_encoder * enc)48 static void radeon_uvd_enc_session_info(struct radeon_uvd_encoder *enc)
49 {
50 unsigned int interface_version =
51 ((RENC_UVD_FW_INTERFACE_MAJOR_VERSION << RENC_UVD_IF_MAJOR_VERSION_SHIFT) |
52 (RENC_UVD_FW_INTERFACE_MINOR_VERSION << RENC_UVD_IF_MINOR_VERSION_SHIFT));
53 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SESSION_INFO);
54 RADEON_ENC_CS(0x00000000); // reserved
55 RADEON_ENC_CS(interface_version);
56 RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0);
57 RADEON_ENC_END();
58 }
59
radeon_uvd_enc_task_info(struct radeon_uvd_encoder * enc,bool need_feedback)60 static void radeon_uvd_enc_task_info(struct radeon_uvd_encoder *enc, bool need_feedback)
61 {
62 enc->enc_pic.task_info.task_id++;
63
64 if (need_feedback)
65 enc->enc_pic.task_info.allowed_max_num_feedbacks = 1;
66 else
67 enc->enc_pic.task_info.allowed_max_num_feedbacks = 0;
68
69 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_TASK_INFO);
70 enc->p_task_size = &enc->cs.current.buf[enc->cs.current.cdw++];
71 RADEON_ENC_CS(enc->enc_pic.task_info.task_id);
72 RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks);
73 RADEON_ENC_END();
74 }
75
radeon_uvd_enc_session_init_hevc(struct radeon_uvd_encoder * enc)76 static void radeon_uvd_enc_session_init_hevc(struct radeon_uvd_encoder *enc)
77 {
78 uint32_t padding_width = 0;
79 uint32_t padding_height = 0;
80 uint32_t max_padding_width = 64 - 2;
81 uint32_t max_padding_height = 16 - 2;
82
83 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
84 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
85
86 if (enc->enc_pic.session_init.aligned_picture_width > enc->source->width)
87 padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->source->width;
88 if (enc->enc_pic.session_init.aligned_picture_height > enc->source->height)
89 padding_height = enc->enc_pic.session_init.aligned_picture_height - enc->source->height;
90
91 /* Input surface can be smaller if the difference is within padding bounds. */
92 if (padding_width > max_padding_width || padding_height > max_padding_height)
93 RVID_ERR("Input surface size doesn't match aligned size\n");
94
95 if (enc->enc_pic.desc->seq.conformance_window_flag) {
96 uint32_t pad_w =
97 (enc->enc_pic.desc->seq.conf_win_left_offset + enc->enc_pic.desc->seq.conf_win_right_offset) * 2;
98 uint32_t pad_h =
99 (enc->enc_pic.desc->seq.conf_win_top_offset + enc->enc_pic.desc->seq.conf_win_bottom_offset) * 2;
100 padding_width = CLAMP(pad_w, padding_width, max_padding_width);
101 padding_height = CLAMP(pad_h, padding_height, max_padding_height);
102 }
103
104 enc->enc_pic.session_init.padding_width = padding_width;
105 enc->enc_pic.session_init.padding_height = padding_height;
106
107 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SESSION_INIT);
108 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
109 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
110 RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
111 RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
112 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
113 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
114 RADEON_ENC_END();
115 }
116
radeon_uvd_enc_layer_control(struct radeon_uvd_encoder * enc)117 static void radeon_uvd_enc_layer_control(struct radeon_uvd_encoder *enc)
118 {
119 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_LAYER_CONTROL);
120 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
121 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
122 RADEON_ENC_END();
123 }
124
radeon_uvd_enc_layer_select(struct radeon_uvd_encoder * enc)125 static void radeon_uvd_enc_layer_select(struct radeon_uvd_encoder *enc)
126 {
127 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_LAYER_SELECT);
128 RADEON_ENC_CS(enc->enc_pic.layer_sel.temporal_layer_index);
129 RADEON_ENC_END();
130 }
131
radeon_uvd_enc_slice_control_hevc(struct radeon_uvd_encoder * enc,struct pipe_picture_desc * picture)132 static void radeon_uvd_enc_slice_control_hevc(struct radeon_uvd_encoder *enc,
133 struct pipe_picture_desc *picture)
134 {
135 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
136 uint32_t num_ctbs_total, num_ctbs_in_slice;
137
138 num_ctbs_total =
139 DIV_ROUND_UP(enc->base.width, 64) * DIV_ROUND_UP(enc->base.height, 64);
140
141 if (pic->num_slice_descriptors <= 1) {
142 num_ctbs_in_slice = num_ctbs_total;
143 } else {
144 bool use_app_config = true;
145 num_ctbs_in_slice = pic->slices_descriptors[0].num_ctu_in_slice;
146
147 /* All slices must have equal size */
148 for (unsigned i = 1; i < pic->num_slice_descriptors - 1; i++) {
149 if (num_ctbs_in_slice != pic->slices_descriptors[i].num_ctu_in_slice)
150 use_app_config = false;
151 }
152 /* Except last one can be smaller */
153 if (pic->slices_descriptors[pic->num_slice_descriptors - 1].num_ctu_in_slice > num_ctbs_in_slice)
154 use_app_config = false;
155
156 if (!use_app_config) {
157 assert(num_ctbs_total >= pic->num_slice_descriptors);
158 num_ctbs_in_slice =
159 (num_ctbs_total + pic->num_slice_descriptors - 1) / pic->num_slice_descriptors;
160 }
161 }
162
163 enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENC_UVD_SLICE_CONTROL_MODE_FIXED_CTBS;
164 enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice =
165 num_ctbs_in_slice;
166 enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment =
167 num_ctbs_in_slice;
168
169 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SLICE_CONTROL);
170 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
171 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
172 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
173 RADEON_ENC_END();
174 }
175
radeon_uvd_enc_spec_misc_hevc(struct radeon_uvd_encoder * enc,struct pipe_picture_desc * picture)176 static void radeon_uvd_enc_spec_misc_hevc(struct radeon_uvd_encoder *enc,
177 struct pipe_picture_desc *picture)
178 {
179 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
180 enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 =
181 pic->seq.log2_min_luma_coding_block_size_minus3;
182 enc->enc_pic.hevc_spec_misc.amp_disabled = !pic->seq.amp_enabled_flag;
183 enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled =
184 pic->seq.strong_intra_smoothing_enabled_flag;
185 enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag = pic->pic.constrained_intra_pred_flag;
186 enc->enc_pic.hevc_spec_misc.cabac_init_flag = pic->slice.cabac_init_flag;
187 enc->enc_pic.hevc_spec_misc.half_pel_enabled = 1;
188 enc->enc_pic.hevc_spec_misc.quarter_pel_enabled = 1;
189
190 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SPEC_MISC);
191 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
192 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
193 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
194 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
195 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
196 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
197 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
198 RADEON_ENC_END();
199 }
200
radeon_uvd_enc_rc_session_init(struct radeon_uvd_encoder * enc,struct pipe_picture_desc * picture)201 static void radeon_uvd_enc_rc_session_init(struct radeon_uvd_encoder *enc,
202 struct pipe_picture_desc *picture)
203 {
204 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
205 enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rc[0].vbv_buf_lv;
206 switch (pic->rc[0].rate_ctrl_method) {
207 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_DISABLE:
208 enc->enc_pic.rc_session_init.rate_control_method = RENC_UVD_RATE_CONTROL_METHOD_NONE;
209 break;
210 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
211 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT:
212 enc->enc_pic.rc_session_init.rate_control_method = RENC_UVD_RATE_CONTROL_METHOD_CBR;
213 break;
214 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
215 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE:
216 enc->enc_pic.rc_session_init.rate_control_method =
217 RENC_UVD_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
218 break;
219 default:
220 enc->enc_pic.rc_session_init.rate_control_method = RENC_UVD_RATE_CONTROL_METHOD_NONE;
221 }
222
223 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_RATE_CONTROL_SESSION_INIT);
224 RADEON_ENC_CS(enc->enc_pic.rc_session_init.rate_control_method);
225 RADEON_ENC_CS(enc->enc_pic.rc_session_init.vbv_buffer_level);
226 RADEON_ENC_END();
227 }
228
radeon_uvd_enc_rc_layer_init(struct radeon_uvd_encoder * enc)229 static void radeon_uvd_enc_rc_layer_init(struct radeon_uvd_encoder *enc)
230 {
231 uint32_t i = enc->enc_pic.layer_sel.temporal_layer_index;
232
233 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_RATE_CONTROL_LAYER_INIT);
234 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].target_bit_rate);
235 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].peak_bit_rate);
236 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].frame_rate_num);
237 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].frame_rate_den);
238 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].vbv_buffer_size);
239 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].avg_target_bits_per_picture);
240 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_integer);
241 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_fractional);
242 RADEON_ENC_END();
243 }
244
radeon_uvd_enc_deblocking_filter_hevc(struct radeon_uvd_encoder * enc,struct pipe_picture_desc * picture)245 static void radeon_uvd_enc_deblocking_filter_hevc(struct radeon_uvd_encoder *enc,
246 struct pipe_picture_desc *picture)
247 {
248 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
249 enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled =
250 pic->pic.pps_loop_filter_across_slices_enabled_flag;
251 enc->enc_pic.hevc_deblock.deblocking_filter_disabled =
252 pic->slice.slice_deblocking_filter_disabled_flag;
253 enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2;
254 enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2;
255 enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset;
256 enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset;
257
258 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_DEBLOCKING_FILTER);
259 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
260 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
261 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
262 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
263 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
264 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
265 RADEON_ENC_END();
266 }
267
radeon_uvd_enc_quality_params(struct radeon_uvd_encoder * enc)268 static void radeon_uvd_enc_quality_params(struct radeon_uvd_encoder *enc)
269 {
270 enc->enc_pic.quality_params.scene_change_sensitivity = 0;
271 enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
272
273 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_QUALITY_PARAMS);
274 RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
275 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
276 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
277 RADEON_ENC_END();
278 }
279
radeon_uvd_enc_write_sps(struct radeon_uvd_encoder * enc,uint8_t * out)280 unsigned int radeon_uvd_enc_write_sps(struct radeon_uvd_encoder *enc, uint8_t *out)
281 {
282 struct radeon_bitstream bs;
283 struct pipe_h265_enc_seq_param *sps = &enc->enc_pic.desc->seq;
284 int i;
285
286 radeon_bs_reset(&bs, out, NULL);
287 radeon_bs_set_emulation_prevention(&bs, false);
288 radeon_bs_code_fixed_bits(&bs, 0x00000001, 32);
289 radeon_bs_code_fixed_bits(&bs, 0x4201, 16);
290 radeon_bs_set_emulation_prevention(&bs, true);
291 radeon_bs_code_fixed_bits(&bs, 0x0, 4); /* sps_video_parameter_set_id */
292 radeon_bs_code_fixed_bits(&bs, sps->sps_max_sub_layers_minus1, 3);
293 radeon_bs_code_fixed_bits(&bs, sps->sps_temporal_id_nesting_flag, 1);
294 radeon_bs_hevc_profile_tier_level(&bs, sps->sps_max_sub_layers_minus1, &sps->profile_tier_level);
295 radeon_bs_code_ue(&bs, 0x0); /* sps_seq_parameter_set_id */
296 radeon_bs_code_ue(&bs, sps->chroma_format_idc);
297 radeon_bs_code_ue(&bs, enc->enc_pic.session_init.aligned_picture_width);
298 radeon_bs_code_ue(&bs, enc->enc_pic.session_init.aligned_picture_height);
299
300 radeon_bs_code_fixed_bits(&bs, sps->conformance_window_flag, 1);
301 if (sps->conformance_window_flag) {
302 radeon_bs_code_ue(&bs, sps->conf_win_left_offset);
303 radeon_bs_code_ue(&bs, sps->conf_win_right_offset);
304 radeon_bs_code_ue(&bs, sps->conf_win_top_offset);
305 radeon_bs_code_ue(&bs, sps->conf_win_bottom_offset);
306 }
307
308 radeon_bs_code_ue(&bs, sps->bit_depth_luma_minus8);
309 radeon_bs_code_ue(&bs, sps->bit_depth_chroma_minus8);
310 radeon_bs_code_ue(&bs, sps->log2_max_pic_order_cnt_lsb_minus4);
311 radeon_bs_code_fixed_bits(&bs, sps->sps_sub_layer_ordering_info_present_flag, 1);
312 i = sps->sps_sub_layer_ordering_info_present_flag ? 0 : sps->sps_max_sub_layers_minus1;
313 for (; i <= sps->sps_max_sub_layers_minus1; i++) {
314 radeon_bs_code_ue(&bs, sps->sps_max_dec_pic_buffering_minus1[i]);
315 radeon_bs_code_ue(&bs, sps->sps_max_num_reorder_pics[i]);
316 radeon_bs_code_ue(&bs, sps->sps_max_latency_increase_plus1[i]);
317 }
318
319 unsigned log2_diff_max_min_luma_coding_block_size =
320 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3);
321 unsigned log2_min_transform_block_size_minus2 =
322 enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3;
323 unsigned log2_diff_max_min_transform_block_size = log2_diff_max_min_luma_coding_block_size;
324 unsigned max_transform_hierarchy_depth_inter = log2_diff_max_min_luma_coding_block_size + 1;
325 unsigned max_transform_hierarchy_depth_intra = max_transform_hierarchy_depth_inter;
326
327 radeon_bs_code_ue(&bs, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
328 radeon_bs_code_ue(&bs, log2_diff_max_min_luma_coding_block_size);
329 radeon_bs_code_ue(&bs, log2_min_transform_block_size_minus2);
330 radeon_bs_code_ue(&bs, log2_diff_max_min_transform_block_size);
331 radeon_bs_code_ue(&bs, max_transform_hierarchy_depth_inter);
332 radeon_bs_code_ue(&bs, max_transform_hierarchy_depth_intra);
333
334 radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* scaling_list_enabled_flag */
335 radeon_bs_code_fixed_bits(&bs, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
336 radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* sample_adaptive_offset_enabled_flag */
337 radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* pcm_enabled_flag */
338
339 radeon_bs_code_ue(&bs, sps->num_short_term_ref_pic_sets);
340 for (i = 0; i < sps->num_short_term_ref_pic_sets; i++)
341 radeon_bs_hevc_st_ref_pic_set(&bs, i, sps->num_short_term_ref_pic_sets, sps->st_ref_pic_set);
342
343 radeon_bs_code_fixed_bits(&bs, sps->long_term_ref_pics_present_flag, 1);
344 if (sps->long_term_ref_pics_present_flag) {
345 radeon_bs_code_ue(&bs, sps->num_long_term_ref_pics_sps);
346 for (i = 0; i < sps->num_long_term_ref_pics_sps; i++) {
347 radeon_bs_code_fixed_bits(&bs, sps->lt_ref_pic_poc_lsb_sps[i], sps->log2_max_pic_order_cnt_lsb_minus4 + 4);
348 radeon_bs_code_fixed_bits(&bs, sps->used_by_curr_pic_lt_sps_flag[i], 1);
349 }
350 }
351
352 radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* sps_temporal_mvp_enabled_flag */
353 radeon_bs_code_fixed_bits(&bs, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1);
354
355 /* VUI parameters present flag */
356 radeon_bs_code_fixed_bits(&bs, (sps->vui_parameters_present_flag), 1);
357 if (sps->vui_parameters_present_flag) {
358 /* aspect ratio present flag */
359 radeon_bs_code_fixed_bits(&bs, (sps->vui_flags.aspect_ratio_info_present_flag), 1);
360 if (sps->vui_flags.aspect_ratio_info_present_flag) {
361 radeon_bs_code_fixed_bits(&bs, (sps->aspect_ratio_idc), 8);
362 if (sps->aspect_ratio_idc == PIPE_H2645_EXTENDED_SAR) {
363 radeon_bs_code_fixed_bits(&bs, (sps->sar_width), 16);
364 radeon_bs_code_fixed_bits(&bs, (sps->sar_height), 16);
365 }
366 }
367 radeon_bs_code_fixed_bits(&bs, sps->vui_flags.overscan_info_present_flag, 1);
368 if (sps->vui_flags.overscan_info_present_flag)
369 radeon_bs_code_fixed_bits(&bs, sps->vui_flags.overscan_appropriate_flag, 1);
370 /* video signal type present flag */
371 radeon_bs_code_fixed_bits(&bs, sps->vui_flags.video_signal_type_present_flag, 1);
372 if (sps->vui_flags.video_signal_type_present_flag) {
373 radeon_bs_code_fixed_bits(&bs, sps->video_format, 3);
374 radeon_bs_code_fixed_bits(&bs, sps->video_full_range_flag, 1);
375 radeon_bs_code_fixed_bits(&bs, sps->vui_flags.colour_description_present_flag, 1);
376 if (sps->vui_flags.colour_description_present_flag) {
377 radeon_bs_code_fixed_bits(&bs, sps->colour_primaries, 8);
378 radeon_bs_code_fixed_bits(&bs, sps->transfer_characteristics, 8);
379 radeon_bs_code_fixed_bits(&bs, sps->matrix_coefficients, 8);
380 }
381 }
382 /* chroma loc info present flag */
383 radeon_bs_code_fixed_bits(&bs, sps->vui_flags.chroma_loc_info_present_flag, 1);
384 if (sps->vui_flags.chroma_loc_info_present_flag) {
385 radeon_bs_code_ue(&bs, sps->chroma_sample_loc_type_top_field);
386 radeon_bs_code_ue(&bs, sps->chroma_sample_loc_type_bottom_field);
387 }
388 radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* neutral chroma indication flag */
389 radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* field seq flag */
390 radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* frame field info present flag */
391 radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* default display windows flag */
392 /* vui timing info present flag */
393 radeon_bs_code_fixed_bits(&bs, (sps->vui_flags.timing_info_present_flag), 1);
394 if (sps->vui_flags.timing_info_present_flag) {
395 radeon_bs_code_fixed_bits(&bs, (sps->num_units_in_tick), 32);
396 radeon_bs_code_fixed_bits(&bs, (sps->time_scale), 32);
397 radeon_bs_code_fixed_bits(&bs, sps->vui_flags.poc_proportional_to_timing_flag, 1);
398 if (sps->vui_flags.poc_proportional_to_timing_flag)
399 radeon_bs_code_ue(&bs, sps->num_ticks_poc_diff_one_minus1);
400 radeon_bs_code_fixed_bits(&bs, sps->vui_flags.hrd_parameters_present_flag, 1);
401 if (sps->vui_flags.hrd_parameters_present_flag)
402 radeon_bs_hevc_hrd_parameters(&bs, 1, sps->sps_max_sub_layers_minus1, &sps->hrd_parameters);
403 }
404 radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* bitstream restriction flag */
405 }
406 radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* sps extension present flag */
407
408 radeon_bs_code_fixed_bits(&bs, 0x1, 1);
409 radeon_bs_byte_align(&bs);
410
411 return bs.bits_output / 8;
412 }
413
radeon_uvd_enc_write_pps(struct radeon_uvd_encoder * enc,uint8_t * out)414 unsigned int radeon_uvd_enc_write_pps(struct radeon_uvd_encoder *enc, uint8_t *out)
415 {
416 struct radeon_bitstream bs;
417 struct pipe_h265_enc_pic_param *pps = &enc->enc_pic.desc->pic;
418
419 radeon_bs_reset(&bs, out, NULL);
420 radeon_bs_set_emulation_prevention(&bs, false);
421 radeon_bs_code_fixed_bits(&bs, 0x00000001, 32);
422 radeon_bs_code_fixed_bits(&bs, 0x4401, 16);
423 radeon_bs_set_emulation_prevention(&bs, true);
424 radeon_bs_code_ue(&bs, 0x0); /* pps_pic_parameter_set_id */
425 radeon_bs_code_ue(&bs, 0x0); /* pps_seq_parameter_set_id */
426 radeon_bs_code_fixed_bits(&bs, 0x1, 1); /* dependent_slice_segments_enabled_flag */
427 radeon_bs_code_fixed_bits(&bs, pps->output_flag_present_flag, 1);
428 radeon_bs_code_fixed_bits(&bs, 0x0, 3); /* num_extra_slice_header_bits */
429 radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* sign_data_hiding_enabled_flag */
430 radeon_bs_code_fixed_bits(&bs, 0x1, 1); /* cabac_init_present_flag */
431 radeon_bs_code_ue(&bs, pps->num_ref_idx_l0_default_active_minus1);
432 radeon_bs_code_ue(&bs, pps->num_ref_idx_l1_default_active_minus1);
433 radeon_bs_code_se(&bs, 0x0); /* init_qp_minus26 */
434 radeon_bs_code_fixed_bits(&bs, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
435 radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* transform_skip_enabled */
436 bool cu_qp_delta_enabled_flag =
437 enc->enc_pic.rc_session_init.rate_control_method != RENC_UVD_RATE_CONTROL_METHOD_NONE;
438 radeon_bs_code_fixed_bits(&bs, cu_qp_delta_enabled_flag, 1);
439 if (cu_qp_delta_enabled_flag)
440 radeon_bs_code_ue(&bs, 0x0); /* diff_cu_qp_delta_depth */
441 radeon_bs_code_se(&bs, enc->enc_pic.hevc_deblock.cb_qp_offset);
442 radeon_bs_code_se(&bs, enc->enc_pic.hevc_deblock.cr_qp_offset);
443 radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* pps_slice_chroma_qp_offsets_present_flag */
444 radeon_bs_code_fixed_bits(&bs, 0x0, 2); /* weighted_pred_flag + weighted_bipred_flag */
445 radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* transquant_bypass_enabled_flag */
446 radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* tiles_enabled_flag */
447 radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* entropy_coding_sync_enabled_flag */
448 radeon_bs_code_fixed_bits(&bs, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
449 radeon_bs_code_fixed_bits(&bs, 0x1, 1); /* deblocking_filter_control_present_flag */
450 radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* deblocking_filter_override_enabled_flag */
451 radeon_bs_code_fixed_bits(&bs, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
452
453 if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
454 radeon_bs_code_se(&bs, enc->enc_pic.hevc_deblock.beta_offset_div2);
455 radeon_bs_code_se(&bs, enc->enc_pic.hevc_deblock.tc_offset_div2);
456 }
457
458 radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* pps_scaling_list_data_present_flag */
459 radeon_bs_code_fixed_bits(&bs, pps->lists_modification_present_flag, 1);
460 radeon_bs_code_ue(&bs, pps->log2_parallel_merge_level_minus2);
461 radeon_bs_code_fixed_bits(&bs, 0x0, 2);
462
463 radeon_bs_code_fixed_bits(&bs, 0x1, 1);
464 radeon_bs_byte_align(&bs);
465
466 return bs.bits_output / 8;
467 }
468
radeon_uvd_enc_write_vps(struct radeon_uvd_encoder * enc,uint8_t * out)469 unsigned int radeon_uvd_enc_write_vps(struct radeon_uvd_encoder *enc, uint8_t *out)
470 {
471 struct radeon_bitstream bs;
472 struct pipe_h265_enc_vid_param *vps = &enc->enc_pic.desc->vid;
473 int i;
474
475 radeon_bs_reset(&bs, out, NULL);
476 radeon_bs_set_emulation_prevention(&bs, false);
477 radeon_bs_code_fixed_bits(&bs, 0x00000001, 32);
478 radeon_bs_code_fixed_bits(&bs, 0x4001, 16);
479 radeon_bs_set_emulation_prevention(&bs, true);
480 radeon_bs_code_fixed_bits(&bs, 0x0, 4); /* vps_video_parameter_set_id*/
481 radeon_bs_code_fixed_bits(&bs, vps->vps_base_layer_internal_flag, 1);
482 radeon_bs_code_fixed_bits(&bs, vps->vps_base_layer_available_flag, 1);
483 radeon_bs_code_fixed_bits(&bs, 0x0, 6); /* vps_max_layers_minus1 */
484 radeon_bs_code_fixed_bits(&bs, vps->vps_max_sub_layers_minus1, 3);
485 radeon_bs_code_fixed_bits(&bs, vps->vps_temporal_id_nesting_flag, 1);
486 radeon_bs_code_fixed_bits(&bs, 0xffff, 16); /* vps_reserved_0xffff_16bits */
487 radeon_bs_hevc_profile_tier_level(&bs, vps->vps_max_sub_layers_minus1, &vps->profile_tier_level);
488 radeon_bs_code_fixed_bits(&bs, vps->vps_sub_layer_ordering_info_present_flag, 1);
489 i = vps->vps_sub_layer_ordering_info_present_flag ? 0 : vps->vps_max_sub_layers_minus1;
490 for (; i <= vps->vps_max_sub_layers_minus1; i++) {
491 radeon_bs_code_ue(&bs, vps->vps_max_dec_pic_buffering_minus1[i]);
492 radeon_bs_code_ue(&bs, vps->vps_max_num_reorder_pics[i]);
493 radeon_bs_code_ue(&bs, vps->vps_max_latency_increase_plus1[i]);
494 }
495 radeon_bs_code_fixed_bits(&bs, 0x0, 6); /* vps_max_layer_id */
496 radeon_bs_code_ue(&bs, 0x0); /* vps_num_layer_sets_minus1 */
497 radeon_bs_code_fixed_bits(&bs, vps->vps_timing_info_present_flag, 1);
498 if (vps->vps_timing_info_present_flag) {
499 radeon_bs_code_fixed_bits(&bs, vps->vps_num_units_in_tick, 32);
500 radeon_bs_code_fixed_bits(&bs, vps->vps_time_scale, 32);
501 radeon_bs_code_fixed_bits(&bs, vps->vps_poc_proportional_to_timing_flag, 1);
502 if (vps->vps_poc_proportional_to_timing_flag)
503 radeon_bs_code_ue(&bs, vps->vps_num_ticks_poc_diff_one_minus1);
504 radeon_bs_code_ue(&bs, 0x0); /* vps_num_hrd_parameters */
505 }
506 radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* vps_extension_flag */
507
508 radeon_bs_code_fixed_bits(&bs, 0x1, 1);
509 radeon_bs_byte_align(&bs);
510
511 return bs.bits_output / 8;
512 }
513
radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder * enc)514 static void radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder *enc)
515 {
516 struct radeon_bitstream bs;
517 struct pipe_h265_enc_seq_param *sps = &enc->enc_pic.desc->seq;
518 struct pipe_h265_enc_pic_param *pps = &enc->enc_pic.desc->pic;
519 struct pipe_h265_enc_slice_param *slice = &enc->enc_pic.desc->slice;
520 uint32_t instruction[RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
521 uint32_t num_bits[RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
522 unsigned int inst_index = 0;
523 unsigned int cdw_start = 0;
524 unsigned int cdw_filled = 0;
525 unsigned int bits_copied = 0;
526 unsigned int num_pic_total_curr = 0;
527
528 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SLICE_HEADER);
529 radeon_bs_reset(&bs, NULL, &enc->cs);
530 radeon_bs_set_emulation_prevention(&bs, false);
531
532 cdw_start = enc->cs.current.cdw;
533 radeon_bs_code_fixed_bits(&bs, 0x0, 1);
534 radeon_bs_code_fixed_bits(&bs, enc->enc_pic.nal_unit_type, 6);
535 radeon_bs_code_fixed_bits(&bs, 0x0, 6);
536 radeon_bs_code_fixed_bits(&bs, enc->enc_pic.temporal_id + 1, 3);
537
538 radeon_bs_flush_headers(&bs);
539 instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_COPY;
540 num_bits[inst_index] = bs.bits_output - bits_copied;
541 bits_copied = bs.bits_output;
542 inst_index++;
543
544 instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_FIRST_SLICE;
545 inst_index++;
546
547 if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
548 radeon_bs_code_fixed_bits(&bs, slice->no_output_of_prior_pics_flag, 1);
549
550 radeon_bs_code_ue(&bs, 0x0); /* slice_pic_parameter_set_id */
551
552 radeon_bs_flush_headers(&bs);
553 instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_COPY;
554 num_bits[inst_index] = bs.bits_output - bits_copied;
555 bits_copied = bs.bits_output;
556 inst_index++;
557
558 instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_SLICE_SEGMENT;
559 inst_index++;
560
561 instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
562 inst_index++;
563
564 switch (enc->enc_pic.picture_type) {
565 case PIPE_H2645_ENC_PICTURE_TYPE_I:
566 case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
567 radeon_bs_code_ue(&bs, 0x2);
568 break;
569 case PIPE_H2645_ENC_PICTURE_TYPE_P:
570 case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
571 default:
572 radeon_bs_code_ue(&bs, 0x1);
573 break;
574 }
575
576 if (pps->output_flag_present_flag)
577 radeon_bs_code_fixed_bits(&bs, slice->pic_output_flag, 1);
578
579 if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
580 radeon_bs_code_fixed_bits(&bs, slice->slice_pic_order_cnt_lsb, sps->log2_max_pic_order_cnt_lsb_minus4 + 4);
581 radeon_bs_code_fixed_bits(&bs, slice->short_term_ref_pic_set_sps_flag, 1);
582 if (!slice->short_term_ref_pic_set_sps_flag) {
583 num_pic_total_curr =
584 radeon_bs_hevc_st_ref_pic_set(&bs, sps->num_short_term_ref_pic_sets,
585 sps->num_short_term_ref_pic_sets, sps->st_ref_pic_set);
586 } else if (sps->num_short_term_ref_pic_sets > 1) {
587 radeon_bs_code_fixed_bits(&bs, slice->short_term_ref_pic_set_idx,
588 util_logbase2_ceil(sps->num_short_term_ref_pic_sets));
589 }
590 if (sps->long_term_ref_pics_present_flag) {
591 if (sps->num_long_term_ref_pics_sps > 0)
592 radeon_bs_code_ue(&bs, slice->num_long_term_sps);
593 radeon_bs_code_ue(&bs, slice->num_long_term_pics);
594 for (unsigned i = 0; i < slice->num_long_term_sps + slice->num_long_term_pics; i++) {
595 if (i < slice->num_long_term_sps) {
596 if (sps->num_long_term_ref_pics_sps > 1)
597 radeon_bs_code_fixed_bits(&bs, slice->lt_idx_sps[i], util_logbase2_ceil(sps->num_long_term_ref_pics_sps));
598 } else {
599 radeon_bs_code_fixed_bits(&bs, slice->poc_lsb_lt[i], sps->log2_max_pic_order_cnt_lsb_minus4 + 4);
600 radeon_bs_code_fixed_bits(&bs, slice->used_by_curr_pic_lt_flag[i], 1);
601 if (slice->used_by_curr_pic_lt_flag[i])
602 num_pic_total_curr++;
603 }
604 radeon_bs_code_fixed_bits(&bs, slice->delta_poc_msb_present_flag[i], 1);
605 if (slice->delta_poc_msb_present_flag[i])
606 radeon_bs_code_ue(&bs, slice->delta_poc_msb_cycle_lt[i]);
607 }
608 }
609 }
610
611 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) {
612 radeon_bs_code_fixed_bits(&bs, slice->num_ref_idx_active_override_flag, 1);
613 if (slice->num_ref_idx_active_override_flag)
614 radeon_bs_code_ue(&bs, slice->num_ref_idx_l0_active_minus1);
615 if (pps->lists_modification_present_flag && num_pic_total_curr > 1) {
616 unsigned num_bits = util_logbase2_ceil(num_pic_total_curr);
617 unsigned num_ref_l0_minus1 = slice->num_ref_idx_active_override_flag ?
618 slice->num_ref_idx_l0_active_minus1 : pps->num_ref_idx_l0_default_active_minus1;
619 radeon_bs_code_fixed_bits(&bs, slice->ref_pic_lists_modification.ref_pic_list_modification_flag_l0, 1);
620 for (unsigned i = 0; i <= num_ref_l0_minus1; i++)
621 radeon_bs_code_fixed_bits(&bs, slice->ref_pic_lists_modification.list_entry_l0[i], num_bits);
622 }
623 radeon_bs_code_fixed_bits(&bs, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
624 radeon_bs_code_ue(&bs, 5 - slice->max_num_merge_cand);
625 }
626
627 radeon_bs_flush_headers(&bs);
628 instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_COPY;
629 num_bits[inst_index] = bs.bits_output - bits_copied;
630 bits_copied = bs.bits_output;
631 inst_index++;
632
633 instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_SLICE_QP_DELTA;
634 inst_index++;
635
636 if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
637 (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)) {
638 radeon_bs_code_fixed_bits(&bs, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
639 radeon_bs_flush_headers(&bs);
640 instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_COPY;
641 num_bits[inst_index] = bs.bits_output - bits_copied;
642 bits_copied = bs.bits_output;
643 inst_index++;
644 }
645
646 instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_END;
647
648 cdw_filled = enc->cs.current.cdw - cdw_start;
649 for (int i = 0; i < RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
650 RADEON_ENC_CS(0x00000000);
651
652 for (int j = 0; j < RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
653 RADEON_ENC_CS(instruction[j]);
654 RADEON_ENC_CS(num_bits[j]);
655 }
656
657 RADEON_ENC_END();
658 }
659
radeon_uvd_enc_ctx(struct radeon_uvd_encoder * enc)660 static void radeon_uvd_enc_ctx(struct radeon_uvd_encoder *enc)
661 {
662 struct si_screen *sscreen = (struct si_screen *)enc->screen;
663
664 enc->enc_pic.ctx_buf.swizzle_mode = 0;
665 if (sscreen->info.gfx_level < GFX9) {
666 enc->enc_pic.ctx_buf.rec_luma_pitch = (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe);
667 enc->enc_pic.ctx_buf.rec_chroma_pitch =
668 (enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe);
669 } else {
670 enc->enc_pic.ctx_buf.rec_luma_pitch = enc->luma->u.gfx9.surf_pitch * enc->luma->bpe;
671 enc->enc_pic.ctx_buf.rec_chroma_pitch = enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe;
672 }
673
674 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_ENCODE_CONTEXT_BUFFER);
675 RADEON_ENC_READWRITE(enc->dpb.res->buf, enc->dpb.res->domains, 0);
676 RADEON_ENC_CS(0x00000000); // reserved
677 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
678 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
679 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
680 RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
681 for (uint32_t i = 0; i < RENC_UVD_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
682 RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset);
683 RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset);
684 }
685 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_picture_luma_pitch);
686 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_picture_chroma_pitch);
687 for (uint32_t i = 0; i < RENC_UVD_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
688 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_reconstructed_pictures[i].luma_offset);
689 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_reconstructed_pictures[i].chroma_offset);
690 }
691 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.luma_offset);
692 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.chroma_offset);
693 RADEON_ENC_END();
694 }
695
radeon_uvd_enc_bitstream(struct radeon_uvd_encoder * enc)696 static void radeon_uvd_enc_bitstream(struct radeon_uvd_encoder *enc)
697 {
698 enc->enc_pic.bit_buf.mode = RENC_UVD_SWIZZLE_MODE_LINEAR;
699 enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size;
700 enc->enc_pic.bit_buf.video_bitstream_data_offset = enc->bs_offset;
701
702 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_VIDEO_BITSTREAM_BUFFER);
703 RADEON_ENC_CS(enc->enc_pic.bit_buf.mode);
704 RADEON_ENC_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0);
705 RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_buffer_size);
706 RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_data_offset);
707 RADEON_ENC_END();
708 }
709
radeon_uvd_enc_feedback(struct radeon_uvd_encoder * enc)710 static void radeon_uvd_enc_feedback(struct radeon_uvd_encoder *enc)
711 {
712 enc->enc_pic.fb_buf.mode = RENC_UVD_FEEDBACK_BUFFER_MODE_LINEAR;
713 enc->enc_pic.fb_buf.feedback_buffer_size = 16;
714 enc->enc_pic.fb_buf.feedback_data_size = 40;
715
716 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_FEEDBACK_BUFFER);
717 RADEON_ENC_CS(enc->enc_pic.fb_buf.mode);
718 RADEON_ENC_WRITE(enc->fb->res->buf, enc->fb->res->domains, 0x0);
719 RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_buffer_size);
720 RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_data_size);
721 RADEON_ENC_END();
722 }
723
radeon_uvd_enc_intra_refresh(struct radeon_uvd_encoder * enc)724 static void radeon_uvd_enc_intra_refresh(struct radeon_uvd_encoder *enc)
725 {
726 switch (enc->enc_pic.desc->intra_refresh.mode) {
727 case INTRA_REFRESH_MODE_UNIT_ROWS:
728 enc->enc_pic.intra_ref.intra_refresh_mode = RENC_UVD_INTRA_REFRESH_MODE_CTB_MB_ROWS;
729 break;
730 case INTRA_REFRESH_MODE_UNIT_COLUMNS:
731 enc->enc_pic.intra_ref.intra_refresh_mode = RENC_UVD_INTRA_REFRESH_MODE_CTB_MB_COLUMNS;
732 break;
733 default:
734 enc->enc_pic.intra_ref.intra_refresh_mode = RENC_UVD_INTRA_REFRESH_MODE_NONE;
735 break;
736 };
737
738 enc->enc_pic.intra_ref.offset = enc->enc_pic.desc->intra_refresh.offset;
739 enc->enc_pic.intra_ref.region_size = enc->enc_pic.desc->intra_refresh.region_size;
740
741 if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)
742 enc->enc_pic.intra_ref.region_size++;
743
744 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INTRA_REFRESH);
745 RADEON_ENC_CS(enc->enc_pic.intra_ref.intra_refresh_mode);
746 RADEON_ENC_CS(enc->enc_pic.intra_ref.offset);
747 RADEON_ENC_CS(enc->enc_pic.intra_ref.region_size);
748 RADEON_ENC_END();
749 }
750
radeon_uvd_enc_rc_per_pic(struct radeon_uvd_encoder * enc)751 static void radeon_uvd_enc_rc_per_pic(struct radeon_uvd_encoder *enc)
752 {
753 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_RATE_CONTROL_PER_PICTURE);
754 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp);
755 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_app);
756 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_app);
757 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size);
758 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data);
759 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable);
760 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd);
761 RADEON_ENC_END();
762 }
763
radeon_uvd_enc_encode_params_hevc(struct radeon_uvd_encoder * enc)764 static void radeon_uvd_enc_encode_params_hevc(struct radeon_uvd_encoder *enc)
765 {
766 struct si_screen *sscreen = (struct si_screen *)enc->screen;
767 switch (enc->enc_pic.picture_type) {
768 case PIPE_H2645_ENC_PICTURE_TYPE_I:
769 case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
770 enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_I;
771 break;
772 case PIPE_H2645_ENC_PICTURE_TYPE_P:
773 enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_P;
774 break;
775 case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
776 enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_P_SKIP;
777 break;
778 case PIPE_H2645_ENC_PICTURE_TYPE_B:
779 enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_B;
780 break;
781 default:
782 enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_I;
783 }
784
785 enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size - enc->bs_offset;
786 if (sscreen->info.gfx_level < GFX9) {
787 enc->enc_pic.enc_params.input_pic_luma_pitch =
788 (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe);
789 enc->enc_pic.enc_params.input_pic_chroma_pitch =
790 (enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe);
791 } else {
792 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch * enc->luma->bpe;
793 enc->enc_pic.enc_params.input_pic_chroma_pitch =
794 enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe;
795 enc->enc_pic.enc_params.input_pic_swizzle_mode = enc->luma->u.gfx9.swizzle_mode;
796 }
797
798 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_ENCODE_PARAMS);
799 RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
800 RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
801
802 if (sscreen->info.gfx_level < GFX9) {
803 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256);
804 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256);
805 } else {
806 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
807 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
808 }
809 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
810 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
811 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_addr_mode);
812 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
813 RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
814 RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
815 RADEON_ENC_END();
816 }
817
radeon_uvd_enc_op_init(struct radeon_uvd_encoder * enc)818 static void radeon_uvd_enc_op_init(struct radeon_uvd_encoder *enc)
819 {
820 RADEON_ENC_BEGIN(RENC_UVD_IB_OP_INITIALIZE);
821 RADEON_ENC_END();
822 }
823
radeon_uvd_enc_op_close(struct radeon_uvd_encoder * enc)824 static void radeon_uvd_enc_op_close(struct radeon_uvd_encoder *enc)
825 {
826 RADEON_ENC_BEGIN(RENC_UVD_IB_OP_CLOSE_SESSION);
827 RADEON_ENC_END();
828 }
829
radeon_uvd_enc_op_enc(struct radeon_uvd_encoder * enc)830 static void radeon_uvd_enc_op_enc(struct radeon_uvd_encoder *enc)
831 {
832 RADEON_ENC_BEGIN(RENC_UVD_IB_OP_ENCODE);
833 RADEON_ENC_END();
834 }
835
radeon_uvd_enc_op_init_rc(struct radeon_uvd_encoder * enc)836 static void radeon_uvd_enc_op_init_rc(struct radeon_uvd_encoder *enc)
837 {
838 RADEON_ENC_BEGIN(RENC_UVD_IB_OP_INIT_RC);
839 RADEON_ENC_END();
840 }
841
radeon_uvd_enc_op_init_rc_vbv(struct radeon_uvd_encoder * enc)842 static void radeon_uvd_enc_op_init_rc_vbv(struct radeon_uvd_encoder *enc)
843 {
844 RADEON_ENC_BEGIN(RENC_UVD_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
845 RADEON_ENC_END();
846 }
847
radeon_uvd_enc_op_preset(struct radeon_uvd_encoder * enc)848 static void radeon_uvd_enc_op_preset(struct radeon_uvd_encoder *enc)
849 {
850 uint32_t preset_mode;
851
852 switch (enc->enc_pic.desc->quality_modes.preset_mode) {
853 case 0: /* SPEED */
854 preset_mode = RENC_UVD_IB_OP_SET_SPEED_ENCODING_MODE;
855 break;
856 case 1: /* BALANCED */
857 preset_mode = RENC_UVD_IB_OP_SET_BALANCE_ENCODING_MODE;
858 break;
859 case 2: /* QUALITY */
860 default:
861 preset_mode = RENC_UVD_IB_OP_SET_QUALITY_ENCODING_MODE;
862 break;
863 }
864
865 RADEON_ENC_BEGIN(preset_mode);
866 RADEON_ENC_END();
867 }
868
begin(struct radeon_uvd_encoder * enc,struct pipe_picture_desc * pic)869 static void begin(struct radeon_uvd_encoder *enc, struct pipe_picture_desc *pic)
870 {
871 radeon_uvd_enc_session_info(enc);
872 enc->total_task_size = 0;
873 radeon_uvd_enc_task_info(enc, enc->need_feedback);
874 radeon_uvd_enc_op_init(enc);
875
876 radeon_uvd_enc_session_init_hevc(enc);
877 radeon_uvd_enc_slice_control_hevc(enc, pic);
878 radeon_uvd_enc_spec_misc_hevc(enc, pic);
879 radeon_uvd_enc_deblocking_filter_hevc(enc, pic);
880
881 radeon_uvd_enc_layer_control(enc);
882 radeon_uvd_enc_rc_session_init(enc, pic);
883 radeon_uvd_enc_quality_params(enc);
884
885 for (uint32_t i = 0; i < enc->enc_pic.layer_ctrl.num_temporal_layers; i++) {
886 enc->enc_pic.layer_sel.temporal_layer_index = i;
887 radeon_uvd_enc_layer_select(enc);
888 radeon_uvd_enc_rc_layer_init(enc);
889 radeon_uvd_enc_layer_select(enc);
890 radeon_uvd_enc_rc_per_pic(enc);
891 }
892
893 radeon_uvd_enc_op_init_rc(enc);
894 radeon_uvd_enc_op_init_rc_vbv(enc);
895 *enc->p_task_size = (enc->total_task_size);
896 }
897
encode(struct radeon_uvd_encoder * enc)898 static void encode(struct radeon_uvd_encoder *enc)
899 {
900 radeon_uvd_enc_session_info(enc);
901 enc->total_task_size = 0;
902 radeon_uvd_enc_task_info(enc, enc->need_feedback);
903
904 if (enc->need_rate_control || enc->need_rc_per_pic) {
905 for (uint32_t i = 0; i < enc->enc_pic.layer_ctrl.num_temporal_layers; i++) {
906 enc->enc_pic.layer_sel.temporal_layer_index = i;
907 radeon_uvd_enc_layer_select(enc);
908 if (enc->need_rate_control)
909 radeon_uvd_enc_rc_layer_init(enc);
910 if (enc->need_rc_per_pic)
911 radeon_uvd_enc_rc_per_pic(enc);
912 }
913 }
914
915 enc->enc_pic.layer_sel.temporal_layer_index = enc->enc_pic.temporal_id;
916 radeon_uvd_enc_layer_select(enc);
917
918 radeon_uvd_enc_slice_header_hevc(enc);
919 radeon_uvd_enc_encode_params_hevc(enc);
920
921 radeon_uvd_enc_ctx(enc);
922 radeon_uvd_enc_bitstream(enc);
923 radeon_uvd_enc_feedback(enc);
924 radeon_uvd_enc_intra_refresh(enc);
925
926 radeon_uvd_enc_op_preset(enc);
927 radeon_uvd_enc_op_enc(enc);
928 *enc->p_task_size = (enc->total_task_size);
929 }
930
destroy(struct radeon_uvd_encoder * enc)931 static void destroy(struct radeon_uvd_encoder *enc)
932 {
933 radeon_uvd_enc_session_info(enc);
934 enc->total_task_size = 0;
935 radeon_uvd_enc_task_info(enc, enc->need_feedback);
936 radeon_uvd_enc_op_close(enc);
937 *enc->p_task_size = (enc->total_task_size);
938 }
939
radeon_uvd_enc_1_1_init(struct radeon_uvd_encoder * enc)940 void radeon_uvd_enc_1_1_init(struct radeon_uvd_encoder *enc)
941 {
942 enc->begin = begin;
943 enc->encode = encode;
944 enc->destroy = destroy;
945 }
946