1 /**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 **************************************************************************/
8
9 #include "radeon_vcn_enc.h"
10 #include "ac_vcn_enc_av1_default_cdf.h"
11 #include "ac_debug.h"
12
13 #include "pipe/p_video_codec.h"
14 #include "radeon_video.h"
15 #include "radeonsi/si_pipe.h"
16 #include "util/u_memory.h"
17 #include "util/u_video.h"
18 #include "vl/vl_video_buffer.h"
19
20 /* set quality modes from the input */
radeon_vcn_enc_quality_modes(struct radeon_encoder * enc,struct pipe_enc_quality_modes * in)21 static void radeon_vcn_enc_quality_modes(struct radeon_encoder *enc,
22 struct pipe_enc_quality_modes *in)
23 {
24 rvcn_enc_quality_modes_t *p = &enc->enc_pic.quality_modes;
25 struct si_screen *sscreen = (struct si_screen *)enc->screen;
26
27 p->preset_mode = in->preset_mode > RENCODE_PRESET_MODE_HIGH_QUALITY
28 ? RENCODE_PRESET_MODE_HIGH_QUALITY
29 : in->preset_mode;
30
31 if (u_reduce_video_profile(enc->base.profile) != PIPE_VIDEO_FORMAT_AV1 &&
32 p->preset_mode == RENCODE_PRESET_MODE_HIGH_QUALITY)
33 p->preset_mode = RENCODE_PRESET_MODE_QUALITY;
34
35 p->pre_encode_mode = in->pre_encode_mode ? RENCODE_PREENCODE_MODE_4X
36 : RENCODE_PREENCODE_MODE_NONE;
37
38 if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_QUALITY_VBR)
39 p->pre_encode_mode = RENCODE_PREENCODE_MODE_4X;
40
41 /* Disabling 2pass encoding for VCN 5.0
42 * This is a temporary limitation only for VCN 5.0 due to HW,
43 * once verified in future VCN 5.X versions, it will be enabled again.
44 */
45 if (sscreen->info.vcn_ip_version >= VCN_5_0_0)
46 p->pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
47
48 p->vbaq_mode = in->vbaq_mode ? RENCODE_VBAQ_AUTO : RENCODE_VBAQ_NONE;
49
50 if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE)
51 p->vbaq_mode = RENCODE_VBAQ_NONE;
52
53 enc->enc_pic.quality_params.vbaq_mode = p->vbaq_mode;
54 enc->enc_pic.quality_params.scene_change_sensitivity = 0;
55 enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
56 enc->enc_pic.quality_params.two_pass_search_center_map_mode =
57 (enc->enc_pic.quality_modes.pre_encode_mode &&
58 !enc->enc_pic.spec_misc.b_picture_enabled) ? 1 : 0;
59 enc->enc_pic.quality_params.vbaq_strength = 0;
60 }
61
62 /* to process invalid frame rate */
radeon_vcn_enc_invalid_frame_rate(uint32_t * den,uint32_t * num)63 static void radeon_vcn_enc_invalid_frame_rate(uint32_t *den, uint32_t *num)
64 {
65 if (*den == 0 || *num == 0) {
66 *den = 1;
67 *num = 30;
68 }
69 }
70
radeon_vcn_per_frame_integer(uint32_t bitrate,uint32_t den,uint32_t num)71 static uint32_t radeon_vcn_per_frame_integer(uint32_t bitrate, uint32_t den, uint32_t num)
72 {
73 uint64_t rate_den = (uint64_t)bitrate * (uint64_t)den;
74
75 return (uint32_t)(rate_den/num);
76 }
77
radeon_vcn_per_frame_frac(uint32_t bitrate,uint32_t den,uint32_t num)78 static uint32_t radeon_vcn_per_frame_frac(uint32_t bitrate, uint32_t den, uint32_t num)
79 {
80 uint64_t rate_den = (uint64_t)bitrate * (uint64_t)den;
81 uint64_t remainder = rate_den % num;
82
83 return (uint32_t)((remainder << 32) / num);
84 }
85
86 /* block length for av1 and hevc is the same, 64, for avc 16 */
radeon_vcn_enc_blocks_in_frame(struct radeon_encoder * enc,uint32_t * width_in_block,uint32_t * height_in_block)87 static uint32_t radeon_vcn_enc_blocks_in_frame(struct radeon_encoder *enc,
88 uint32_t *width_in_block,
89 uint32_t *height_in_block)
90 {
91 bool is_h264 = u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC;
92 uint32_t block_length = is_h264 ? PIPE_H264_MB_SIZE : PIPE_H265_ENC_CTB_SIZE;
93
94 *width_in_block = PIPE_ALIGN_IN_BLOCK_SIZE(enc->base.width, block_length);
95 *height_in_block = PIPE_ALIGN_IN_BLOCK_SIZE(enc->base.height, block_length);
96
97 return block_length;
98 }
99
radeon_vcn_enc_get_intra_refresh_param(struct radeon_encoder * enc,bool need_filter_overlap,struct pipe_enc_intra_refresh * intra_refresh)100 static void radeon_vcn_enc_get_intra_refresh_param(struct radeon_encoder *enc,
101 bool need_filter_overlap,
102 struct pipe_enc_intra_refresh *intra_refresh)
103 {
104 uint32_t width_in_block, height_in_block;
105
106 enc->enc_pic.intra_refresh.intra_refresh_mode = RENCODE_INTRA_REFRESH_MODE_NONE;
107 /* some exceptions where intra-refresh is disabled:
108 * 1. if B frame is enabled
109 * 2. if SVC (number of temproal layers is larger than 1) is enabled
110 */
111 if (enc->enc_pic.spec_misc.b_picture_enabled || enc->enc_pic.num_temporal_layers > 1) {
112 enc->enc_pic.intra_refresh.region_size = 0;
113 enc->enc_pic.intra_refresh.offset = 0;
114 return;
115 }
116
117 radeon_vcn_enc_blocks_in_frame(enc, &width_in_block, &height_in_block);
118
119 switch(intra_refresh->mode) {
120 case INTRA_REFRESH_MODE_UNIT_ROWS:
121 if (intra_refresh->offset < height_in_block)
122 enc->enc_pic.intra_refresh.intra_refresh_mode
123 = RENCODE_INTRA_REFRESH_MODE_CTB_MB_ROWS;
124 break;
125 case INTRA_REFRESH_MODE_UNIT_COLUMNS:
126 if (intra_refresh->offset < width_in_block)
127 enc->enc_pic.intra_refresh.intra_refresh_mode
128 = RENCODE_INTRA_REFRESH_MODE_CTB_MB_COLUMNS;
129 break;
130 case INTRA_REFRESH_MODE_NONE:
131 default:
132 break;
133 };
134
135 /* with loop filters (avc/hevc/av1) enabled the region_size has to increase 1 to
136 * get overlapped (av1 is enabling it all the time). The region_size and offset
137 * require to be in unit of MB or CTB or SB according to different codecs.
138 */
139 if (enc->enc_pic.intra_refresh.intra_refresh_mode != RENCODE_INTRA_REFRESH_MODE_NONE) {
140 enc->enc_pic.intra_refresh.region_size = (need_filter_overlap) ?
141 intra_refresh->region_size + 1 :
142 intra_refresh->region_size;
143 enc->enc_pic.intra_refresh.offset = intra_refresh->offset;
144 } else {
145 enc->enc_pic.intra_refresh.region_size = 0;
146 enc->enc_pic.intra_refresh.offset = 0;
147 }
148 }
149
radeon_vcn_enc_get_roi_param(struct radeon_encoder * enc,struct pipe_enc_roi * roi)150 static void radeon_vcn_enc_get_roi_param(struct radeon_encoder *enc,
151 struct pipe_enc_roi *roi)
152 {
153 struct si_screen *sscreen = (struct si_screen *)enc->screen;
154 bool is_av1 = u_reduce_video_profile(enc->base.profile)
155 == PIPE_VIDEO_FORMAT_AV1;
156 rvcn_enc_qp_map_t *qp_map = &enc->enc_pic.enc_qp_map;
157
158 if (!roi->num)
159 enc->enc_pic.enc_qp_map.qp_map_type = RENCODE_QP_MAP_TYPE_NONE;
160 else {
161 uint32_t width_in_block, height_in_block;
162 uint32_t block_length;
163 int32_t i, j, pa_format = 0;
164
165 qp_map->version = sscreen->info.vcn_ip_version >= VCN_5_0_0
166 ? RENCODE_QP_MAP_VCN5 : RENCODE_QP_MAP_LEGACY;
167
168 /* rate control is using a different qp map type, in case of below
169 * vcn_5_0_0 */
170 if (enc->enc_pic.rc_session_init.rate_control_method &&
171 (qp_map->version == RENCODE_QP_MAP_LEGACY)) {
172 enc->enc_pic.enc_qp_map.qp_map_type = RENCODE_QP_MAP_TYPE_MAP_PA;
173 pa_format = 1;
174 }
175 else
176 enc->enc_pic.enc_qp_map.qp_map_type = RENCODE_QP_MAP_TYPE_DELTA;
177
178 block_length = radeon_vcn_enc_blocks_in_frame(enc, &width_in_block, &height_in_block);
179
180 qp_map->width_in_block = width_in_block;
181 qp_map->height_in_block = height_in_block;
182
183 for (i = RENCODE_QP_MAP_MAX_REGIONS - 1; i >= roi->num; i--)
184 enc->enc_pic.enc_qp_map.map[i].is_valid = false;
185
186 /* reverse the map sequence */
187 for (j = 0; i >= 0; i--, j++) {
188 struct rvcn_enc_qp_map_region *map = &enc->enc_pic.enc_qp_map.map[j];
189 struct pipe_enc_region_in_roi *region = &roi->region[i];
190
191 map->is_valid = region->valid;
192 if (region->valid) {
193 int32_t av1_qi_value;
194 /* mapped av1 qi into the legacy qp range by dividing by 5 and
195 * rounding up in any rate control mode.
196 */
197 if (is_av1 && (pa_format || (qp_map->version == RENCODE_QP_MAP_VCN5))) {
198 if (region->qp_value > 0)
199 av1_qi_value = (region->qp_value + 2) / 5;
200 else if (region->qp_value < 0)
201 av1_qi_value = (region->qp_value - 2) / 5;
202 else
203 av1_qi_value = region->qp_value;
204 map->qp_delta = av1_qi_value;
205 } else
206 map->qp_delta = region->qp_value;
207
208 map->x_in_unit = CLAMP((region->x / block_length), 0, width_in_block - 1);
209 map->y_in_unit = CLAMP((region->y / block_length), 0, height_in_block - 1);
210 map->width_in_unit = CLAMP((region->width / block_length), 0, width_in_block);
211 map->height_in_unit = CLAMP((region->height / block_length), 0, width_in_block);
212 }
213 }
214 }
215 }
216
radeon_vcn_enc_get_latency_param(struct radeon_encoder * enc)217 static void radeon_vcn_enc_get_latency_param(struct radeon_encoder *enc)
218 {
219 struct si_screen *sscreen = (struct si_screen *)enc->screen;
220
221 enc->enc_pic.enc_latency.encode_latency =
222 sscreen->debug_flags & DBG(LOW_LATENCY_ENCODE) ? 1000 : 0;
223 }
224
radeon_vcn_enc_h264_get_session_param(struct radeon_encoder * enc,struct pipe_h264_enc_picture_desc * pic)225 static void radeon_vcn_enc_h264_get_session_param(struct radeon_encoder *enc,
226 struct pipe_h264_enc_picture_desc *pic)
227 {
228 if (enc->enc_pic.session_init.aligned_picture_width)
229 return;
230
231 uint32_t align_width = PIPE_H264_MB_SIZE;
232 uint32_t align_height = PIPE_H264_MB_SIZE;
233
234 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264;
235 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, align_width);
236 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, align_height);
237
238 uint32_t padding_width = 0;
239 uint32_t padding_height = 0;
240 uint32_t max_padding_width = align_width - 2;
241 uint32_t max_padding_height = align_height - 2;
242
243 if (enc->enc_pic.session_init.aligned_picture_width > enc->source->width)
244 padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->source->width;
245 if (enc->enc_pic.session_init.aligned_picture_height > enc->source->height)
246 padding_height = enc->enc_pic.session_init.aligned_picture_height - enc->source->height;
247
248 /* Input surface can be smaller if the difference is within padding bounds. */
249 if (padding_width > max_padding_width || padding_height > max_padding_height)
250 RADEON_ENC_ERR("Input surface size doesn't match aligned size\n");
251
252 if (pic->seq.enc_frame_cropping_flag) {
253 uint32_t pad_w =
254 (pic->seq.enc_frame_crop_left_offset + pic->seq.enc_frame_crop_right_offset) * 2;
255 uint32_t pad_h =
256 (pic->seq.enc_frame_crop_top_offset + pic->seq.enc_frame_crop_bottom_offset) * 2;
257 padding_width = CLAMP(pad_w, padding_width, max_padding_width);
258 padding_height = CLAMP(pad_h, padding_height, max_padding_height);
259 }
260
261 enc->enc_pic.session_init.padding_width = padding_width;
262 enc->enc_pic.session_init.padding_height = padding_height;
263 }
264
radeon_vcn_enc_h264_get_dbk_param(struct radeon_encoder * enc,struct pipe_h264_enc_picture_desc * pic)265 static void radeon_vcn_enc_h264_get_dbk_param(struct radeon_encoder *enc,
266 struct pipe_h264_enc_picture_desc *pic)
267 {
268 enc->enc_pic.h264_deblock.disable_deblocking_filter_idc =
269 CLAMP(pic->dbk.disable_deblocking_filter_idc, 0, 2);
270 enc->enc_pic.h264_deblock.alpha_c0_offset_div2 = pic->dbk.alpha_c0_offset_div2;
271 enc->enc_pic.h264_deblock.beta_offset_div2 = pic->dbk.beta_offset_div2;
272 enc->enc_pic.h264_deblock.cb_qp_offset = pic->pic_ctrl.chroma_qp_index_offset;
273 enc->enc_pic.h264_deblock.cr_qp_offset = pic->pic_ctrl.second_chroma_qp_index_offset;
274 }
275
radeon_vcn_enc_h264_get_spec_misc_param(struct radeon_encoder * enc,struct pipe_h264_enc_picture_desc * pic)276 static void radeon_vcn_enc_h264_get_spec_misc_param(struct radeon_encoder *enc,
277 struct pipe_h264_enc_picture_desc *pic)
278 {
279 struct si_screen *sscreen = (struct si_screen *)enc->screen;
280
281 enc->enc_pic.spec_misc.profile_idc = u_get_h264_profile_idc(enc->base.profile);
282 if (enc->enc_pic.spec_misc.profile_idc >= PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN &&
283 enc->enc_pic.spec_misc.profile_idc != PIPE_VIDEO_PROFILE_MPEG4_AVC_EXTENDED)
284 enc->enc_pic.spec_misc.cabac_enable = pic->pic_ctrl.enc_cabac_enable;
285 else
286 enc->enc_pic.spec_misc.cabac_enable = false;
287
288 enc->enc_pic.spec_misc.cabac_init_idc = enc->enc_pic.spec_misc.cabac_enable ?
289 pic->pic_ctrl.enc_cabac_init_idc : 0;
290 enc->enc_pic.spec_misc.deblocking_filter_control_present_flag =
291 pic->pic_ctrl.deblocking_filter_control_present_flag;
292 enc->enc_pic.spec_misc.redundant_pic_cnt_present_flag =
293 pic->pic_ctrl.redundant_pic_cnt_present_flag;
294 enc->enc_pic.spec_misc.b_picture_enabled = !!pic->seq.max_num_reorder_frames;
295 enc->enc_pic.spec_misc.constrained_intra_pred_flag =
296 pic->pic_ctrl.constrained_intra_pred_flag;
297 enc->enc_pic.spec_misc.half_pel_enabled = 1;
298 enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
299 enc->enc_pic.spec_misc.weighted_bipred_idc = 0;
300 enc->enc_pic.spec_misc.transform_8x8_mode =
301 sscreen->info.vcn_ip_version >= VCN_5_0_0 &&
302 pic->pic_ctrl.transform_8x8_mode_flag;
303 enc->enc_pic.spec_misc.level_idc = pic->seq.level_idc;
304 }
305
radeon_vcn_enc_h264_get_rc_param(struct radeon_encoder * enc,struct pipe_h264_enc_picture_desc * pic)306 static void radeon_vcn_enc_h264_get_rc_param(struct radeon_encoder *enc,
307 struct pipe_h264_enc_picture_desc *pic)
308 {
309 uint32_t frame_rate_den, frame_rate_num, max_qp;
310
311 enc->enc_pic.num_temporal_layers = pic->seq.num_temporal_layers ? pic->seq.num_temporal_layers : 1;
312 enc->enc_pic.temporal_id = MIN2(pic->pic_ctrl.temporal_id, enc->enc_pic.num_temporal_layers - 1);
313
314 for (int i = 0; i < enc->enc_pic.num_temporal_layers; i++) {
315 enc->enc_pic.rc_layer_init[i].target_bit_rate = pic->rate_ctrl[i].target_bitrate;
316 enc->enc_pic.rc_layer_init[i].peak_bit_rate = pic->rate_ctrl[i].peak_bitrate;
317 frame_rate_den = pic->rate_ctrl[i].frame_rate_den;
318 frame_rate_num = pic->rate_ctrl[i].frame_rate_num;
319 radeon_vcn_enc_invalid_frame_rate(&frame_rate_den, &frame_rate_num);
320 enc->enc_pic.rc_layer_init[i].frame_rate_den = frame_rate_den;
321 enc->enc_pic.rc_layer_init[i].frame_rate_num = frame_rate_num;
322 enc->enc_pic.rc_layer_init[i].vbv_buffer_size = pic->rate_ctrl[i].vbv_buffer_size;
323 enc->enc_pic.rc_layer_init[i].avg_target_bits_per_picture =
324 radeon_vcn_per_frame_integer(pic->rate_ctrl[i].target_bitrate,
325 frame_rate_den,
326 frame_rate_num);
327 enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_integer =
328 radeon_vcn_per_frame_integer(pic->rate_ctrl[i].peak_bitrate,
329 frame_rate_den,
330 frame_rate_num);
331 enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_fractional =
332 radeon_vcn_per_frame_frac(pic->rate_ctrl[i].peak_bitrate,
333 frame_rate_den,
334 frame_rate_num);
335 }
336 enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rate_ctrl[0].vbv_buf_lv;
337 enc->enc_pic.rc_per_pic.qp_obs = pic->quant_i_frames;
338 enc->enc_pic.rc_per_pic.min_qp_app_obs = pic->rate_ctrl[0].min_qp;
339 enc->enc_pic.rc_per_pic.max_qp_app_obs = pic->rate_ctrl[0].max_qp ?
340 pic->rate_ctrl[0].max_qp : 51;
341 enc->enc_pic.rc_per_pic.qp_i = pic->quant_i_frames;
342 enc->enc_pic.rc_per_pic.qp_p = pic->quant_p_frames;
343 enc->enc_pic.rc_per_pic.qp_b = pic->quant_b_frames;
344 enc->enc_pic.rc_per_pic.min_qp_i = pic->rate_ctrl[0].min_qp;
345 enc->enc_pic.rc_per_pic.min_qp_p = pic->rate_ctrl[0].min_qp;
346 enc->enc_pic.rc_per_pic.min_qp_b = pic->rate_ctrl[0].min_qp;
347 max_qp = pic->rate_ctrl[0].max_qp ? pic->rate_ctrl[0].max_qp : 51;
348 enc->enc_pic.rc_per_pic.max_qp_i = max_qp;
349 enc->enc_pic.rc_per_pic.max_qp_p = max_qp;
350 enc->enc_pic.rc_per_pic.max_qp_b = max_qp;
351 enc->enc_pic.rc_per_pic.enabled_filler_data = 0;
352 enc->enc_pic.rc_per_pic.skip_frame_enable = pic->rate_ctrl[0].skip_frame_enable;
353 enc->enc_pic.rc_per_pic.enforce_hrd = pic->rate_ctrl[0].enforce_hrd;
354 enc->enc_pic.rc_per_pic.qvbr_quality_level = pic->rate_ctrl[0].vbr_quality_factor;
355
356 switch (pic->rate_ctrl[0].rate_ctrl_method) {
357 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_DISABLE:
358 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
359 break;
360 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
361 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT:
362 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR;
363 enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rate_ctrl[0].fill_data_enable;
364 break;
365 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
366 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE:
367 enc->enc_pic.rc_session_init.rate_control_method =
368 RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
369 break;
370 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_QUALITY_VARIABLE:
371 enc->enc_pic.rc_session_init.rate_control_method =
372 RENCODE_RATE_CONTROL_METHOD_QUALITY_VBR;
373 break;
374 default:
375 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
376 }
377 enc->enc_pic.rc_per_pic.max_au_size_obs = pic->rate_ctrl[0].max_au_size;
378 enc->enc_pic.rc_per_pic.max_au_size_i = pic->rate_ctrl[0].max_au_size;
379 enc->enc_pic.rc_per_pic.max_au_size_p = pic->rate_ctrl[0].max_au_size;
380 enc->enc_pic.rc_per_pic.max_au_size_b = pic->rate_ctrl[0].max_au_size;
381 }
382
radeon_vcn_enc_h264_get_slice_ctrl_param(struct radeon_encoder * enc,struct pipe_h264_enc_picture_desc * pic)383 static void radeon_vcn_enc_h264_get_slice_ctrl_param(struct radeon_encoder *enc,
384 struct pipe_h264_enc_picture_desc *pic)
385 {
386 uint32_t num_mbs_total, num_mbs_in_slice;
387
388 num_mbs_total =
389 PIPE_ALIGN_IN_BLOCK_SIZE(enc->base.width, PIPE_H264_MB_SIZE) *
390 PIPE_ALIGN_IN_BLOCK_SIZE(enc->base.height, PIPE_H264_MB_SIZE);
391
392 if (pic->num_slice_descriptors <= 1) {
393 num_mbs_in_slice = num_mbs_total;
394 } else {
395 bool use_app_config = true;
396 num_mbs_in_slice = pic->slices_descriptors[0].num_macroblocks;
397
398 /* All slices must have equal size */
399 for (unsigned i = 1; i < pic->num_slice_descriptors - 1; i++) {
400 if (num_mbs_in_slice != pic->slices_descriptors[i].num_macroblocks)
401 use_app_config = false;
402 }
403 /* Except last one can be smaller */
404 if (pic->slices_descriptors[pic->num_slice_descriptors - 1].num_macroblocks > num_mbs_in_slice)
405 use_app_config = false;
406
407 if (!use_app_config) {
408 assert(num_mbs_total >= pic->num_slice_descriptors);
409 num_mbs_in_slice =
410 (num_mbs_total + pic->num_slice_descriptors - 1) / pic->num_slice_descriptors;
411 }
412 }
413
414 num_mbs_in_slice = MAX2(4, num_mbs_in_slice);
415
416 enc->enc_pic.slice_ctrl.slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS;
417 enc->enc_pic.slice_ctrl.num_mbs_per_slice = num_mbs_in_slice;
418 }
419
radeon_vcn_enc_get_output_format_param(struct radeon_encoder * enc,bool full_range)420 static void radeon_vcn_enc_get_output_format_param(struct radeon_encoder *enc, bool full_range)
421 {
422 switch (enc->enc_pic.bit_depth_luma_minus8) {
423 case 2: /* 10 bits */
424 enc->enc_pic.enc_output_format.output_color_volume = RENCODE_COLOR_VOLUME_G22_BT709;
425 enc->enc_pic.enc_output_format.output_color_range = full_range ?
426 RENCODE_COLOR_RANGE_FULL : RENCODE_COLOR_RANGE_STUDIO;
427 enc->enc_pic.enc_output_format.output_chroma_location = RENCODE_CHROMA_LOCATION_INTERSTITIAL;
428 enc->enc_pic.enc_output_format.output_color_bit_depth = RENCODE_COLOR_BIT_DEPTH_10_BIT;
429 break;
430 default: /* 8 bits */
431 enc->enc_pic.enc_output_format.output_color_volume = RENCODE_COLOR_VOLUME_G22_BT709;
432 enc->enc_pic.enc_output_format.output_color_range = full_range ?
433 RENCODE_COLOR_RANGE_FULL : RENCODE_COLOR_RANGE_STUDIO;
434 enc->enc_pic.enc_output_format.output_chroma_location = RENCODE_CHROMA_LOCATION_INTERSTITIAL;
435 enc->enc_pic.enc_output_format.output_color_bit_depth = RENCODE_COLOR_BIT_DEPTH_8_BIT;
436 break;
437 }
438 }
439
radeon_vcn_enc_get_input_format_param(struct radeon_encoder * enc,struct pipe_picture_desc * pic_base)440 static void radeon_vcn_enc_get_input_format_param(struct radeon_encoder *enc,
441 struct pipe_picture_desc *pic_base)
442 {
443 switch (pic_base->input_format) {
444 case PIPE_FORMAT_P010:
445 enc->enc_pic.enc_input_format.input_color_bit_depth = RENCODE_COLOR_BIT_DEPTH_10_BIT;
446 enc->enc_pic.enc_input_format.input_color_packing_format = RENCODE_COLOR_PACKING_FORMAT_P010;
447 enc->enc_pic.enc_input_format.input_chroma_subsampling = RENCODE_CHROMA_SUBSAMPLING_4_2_0;
448 enc->enc_pic.enc_input_format.input_color_space = RENCODE_COLOR_SPACE_YUV;
449 break;
450 case PIPE_FORMAT_B8G8R8A8_UNORM:
451 case PIPE_FORMAT_B8G8R8X8_UNORM:
452 enc->enc_pic.enc_input_format.input_color_bit_depth = RENCODE_COLOR_BIT_DEPTH_8_BIT;
453 enc->enc_pic.enc_input_format.input_chroma_subsampling = RENCODE_CHROMA_SUBSAMPLING_4_4_4;
454 enc->enc_pic.enc_input_format.input_color_packing_format = RENCODE_COLOR_PACKING_FORMAT_A8R8G8B8;
455 enc->enc_pic.enc_input_format.input_color_space = RENCODE_COLOR_SPACE_RGB;
456 break;
457 case PIPE_FORMAT_R8G8B8A8_UNORM:
458 case PIPE_FORMAT_R8G8B8X8_UNORM:
459 enc->enc_pic.enc_input_format.input_color_bit_depth = RENCODE_COLOR_BIT_DEPTH_8_BIT;
460 enc->enc_pic.enc_input_format.input_chroma_subsampling = RENCODE_CHROMA_SUBSAMPLING_4_4_4;
461 enc->enc_pic.enc_input_format.input_color_packing_format = RENCODE_COLOR_PACKING_FORMAT_A8B8G8R8;
462 enc->enc_pic.enc_input_format.input_color_space = RENCODE_COLOR_SPACE_RGB;
463 break;
464 case PIPE_FORMAT_B10G10R10A2_UNORM:
465 case PIPE_FORMAT_B10G10R10X2_UNORM:
466 enc->enc_pic.enc_input_format.input_color_bit_depth = RENCODE_COLOR_BIT_DEPTH_10_BIT;
467 enc->enc_pic.enc_input_format.input_chroma_subsampling = RENCODE_CHROMA_SUBSAMPLING_4_4_4;
468 enc->enc_pic.enc_input_format.input_color_packing_format = RENCODE_COLOR_PACKING_FORMAT_A2R10G10B10;
469 enc->enc_pic.enc_input_format.input_color_space = RENCODE_COLOR_SPACE_RGB;
470 break;
471 case PIPE_FORMAT_R10G10B10A2_UNORM:
472 case PIPE_FORMAT_R10G10B10X2_UNORM:
473 enc->enc_pic.enc_input_format.input_color_bit_depth = RENCODE_COLOR_BIT_DEPTH_10_BIT;
474 enc->enc_pic.enc_input_format.input_chroma_subsampling = RENCODE_CHROMA_SUBSAMPLING_4_4_4;
475 enc->enc_pic.enc_input_format.input_color_packing_format = RENCODE_COLOR_PACKING_FORMAT_A2B10G10R10;
476 enc->enc_pic.enc_input_format.input_color_space = RENCODE_COLOR_SPACE_RGB;
477 break;
478 case PIPE_FORMAT_NV12: /* FALL THROUGH */
479 default:
480 enc->enc_pic.enc_input_format.input_color_bit_depth = RENCODE_COLOR_BIT_DEPTH_8_BIT;
481 enc->enc_pic.enc_input_format.input_color_packing_format = RENCODE_COLOR_PACKING_FORMAT_NV12;
482 enc->enc_pic.enc_input_format.input_chroma_subsampling = RENCODE_CHROMA_SUBSAMPLING_4_2_0;
483 enc->enc_pic.enc_input_format.input_color_space = RENCODE_COLOR_SPACE_YUV;
484 break;
485 }
486
487 enc->enc_pic.enc_input_format.input_color_volume = RENCODE_COLOR_VOLUME_G22_BT709;
488 enc->enc_pic.enc_input_format.input_color_range = pic_base->input_full_range ?
489 RENCODE_COLOR_RANGE_FULL : RENCODE_COLOR_RANGE_STUDIO;
490 enc->enc_pic.enc_input_format.input_chroma_location = RENCODE_CHROMA_LOCATION_INTERSTITIAL;
491 }
492
radeon_vcn_enc_h264_get_param(struct radeon_encoder * enc,struct pipe_h264_enc_picture_desc * pic)493 static void radeon_vcn_enc_h264_get_param(struct radeon_encoder *enc,
494 struct pipe_h264_enc_picture_desc *pic)
495 {
496 bool use_filter;
497
498 enc->enc_pic.h264.desc = pic;
499 enc->enc_pic.picture_type = pic->picture_type;
500 enc->enc_pic.bit_depth_luma_minus8 = 0;
501 enc->enc_pic.bit_depth_chroma_minus8 = 0;
502 enc->enc_pic.enc_params.reference_picture_index =
503 pic->ref_list0[0] == PIPE_H2645_LIST_REF_INVALID_ENTRY ? 0xffffffff : pic->ref_list0[0];
504 enc->enc_pic.h264_enc_params.l1_reference_picture0_index =
505 pic->ref_list1[0] == PIPE_H2645_LIST_REF_INVALID_ENTRY ? 0xffffffff : pic->ref_list1[0];
506 enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
507 enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE;
508 enc->enc_pic.h264_enc_params.l0_reference_picture1_index = 0xffffffff;
509 enc->enc_pic.enc_params.reconstructed_picture_index = pic->dpb_curr_pic;
510 enc->enc_pic.h264_enc_params.is_reference = !pic->not_referenced;
511 enc->enc_pic.h264_enc_params.is_long_term = pic->is_ltr;
512 enc->enc_pic.not_referenced = pic->not_referenced;
513
514 if ((pic->ref_list0[0] != PIPE_H2645_LIST_REF_INVALID_ENTRY &&
515 pic->dpb[pic->ref_list0[0]].picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B) ||
516 (pic->ref_list1[0] != PIPE_H2645_LIST_REF_INVALID_ENTRY &&
517 pic->dpb[pic->ref_list1[0]].picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B))
518 RADEON_ENC_ERR("B-frame references not supported\n");
519
520 if (enc->dpb_type == DPB_TIER_2) {
521 for (uint32_t i = 0; i < ARRAY_SIZE(pic->dpb); i++) {
522 struct pipe_video_buffer *buf = pic->dpb[i].buffer;
523 enc->enc_pic.dpb_bufs[i] =
524 buf ? vl_video_buffer_get_associated_data(buf, &enc->base) : NULL;
525 assert(!buf || enc->enc_pic.dpb_bufs[i]);
526 }
527 }
528
529 radeon_vcn_enc_h264_get_session_param(enc, pic);
530 radeon_vcn_enc_h264_get_dbk_param(enc, pic);
531 radeon_vcn_enc_h264_get_rc_param(enc, pic);
532 radeon_vcn_enc_h264_get_spec_misc_param(enc, pic);
533 radeon_vcn_enc_h264_get_slice_ctrl_param(enc, pic);
534 radeon_vcn_enc_get_input_format_param(enc, &pic->base);
535 radeon_vcn_enc_get_output_format_param(enc, pic->seq.video_full_range_flag);
536
537 use_filter = enc->enc_pic.h264_deblock.disable_deblocking_filter_idc != 1;
538 radeon_vcn_enc_get_intra_refresh_param(enc, use_filter, &pic->intra_refresh);
539 radeon_vcn_enc_get_roi_param(enc, &pic->roi);
540 radeon_vcn_enc_get_latency_param(enc);
541 radeon_vcn_enc_quality_modes(enc, &pic->quality_modes);
542 }
543
radeon_vcn_enc_hevc_get_session_param(struct radeon_encoder * enc,struct pipe_h265_enc_picture_desc * pic)544 static void radeon_vcn_enc_hevc_get_session_param(struct radeon_encoder *enc,
545 struct pipe_h265_enc_picture_desc *pic)
546 {
547 if (enc->enc_pic.session_init.aligned_picture_width)
548 return;
549
550 uint32_t align_width = PIPE_H265_ENC_CTB_SIZE;
551 uint32_t align_height = 16;
552
553 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC;
554 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, align_width);
555 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, align_height);
556
557 uint32_t padding_width = 0;
558 uint32_t padding_height = 0;
559 uint32_t max_padding_width = align_width - 2;
560 uint32_t max_padding_height = align_height - 2;
561
562 if (enc->enc_pic.session_init.aligned_picture_width > enc->source->width)
563 padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->source->width;
564 if (enc->enc_pic.session_init.aligned_picture_height > enc->source->height)
565 padding_height = enc->enc_pic.session_init.aligned_picture_height - enc->source->height;
566
567 /* Input surface can be smaller if the difference is within padding bounds. */
568 if (padding_width > max_padding_width || padding_height > max_padding_height)
569 RADEON_ENC_ERR("Input surface size doesn't match aligned size\n");
570
571 if (pic->seq.conformance_window_flag) {
572 uint32_t pad_w =
573 (pic->seq.conf_win_left_offset + pic->seq.conf_win_right_offset) * 2;
574 uint32_t pad_h =
575 (pic->seq.conf_win_top_offset + pic->seq.conf_win_bottom_offset) * 2;
576 padding_width = CLAMP(pad_w, padding_width, max_padding_width);
577 padding_height = CLAMP(pad_h, padding_height, max_padding_height);
578 }
579
580 enc->enc_pic.session_init.padding_width = padding_width;
581 enc->enc_pic.session_init.padding_height = padding_height;
582 }
583
radeon_vcn_enc_hevc_get_dbk_param(struct radeon_encoder * enc,struct pipe_h265_enc_picture_desc * pic)584 static void radeon_vcn_enc_hevc_get_dbk_param(struct radeon_encoder *enc,
585 struct pipe_h265_enc_picture_desc *pic)
586 {
587 struct si_screen *sscreen = (struct si_screen *)enc->screen;
588
589 enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled =
590 pic->pic.pps_loop_filter_across_slices_enabled_flag;
591 enc->enc_pic.hevc_deblock.deblocking_filter_disabled =
592 pic->slice.slice_deblocking_filter_disabled_flag;
593 enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2;
594 enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2;
595 enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset;
596 enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset;
597 enc->enc_pic.hevc_deblock.disable_sao =
598 sscreen->info.vcn_ip_version < VCN_2_0_0 ||
599 !pic->seq.sample_adaptive_offset_enabled_flag;
600 }
601
radeon_vcn_enc_hevc_get_spec_misc_param(struct radeon_encoder * enc,struct pipe_h265_enc_picture_desc * pic)602 static void radeon_vcn_enc_hevc_get_spec_misc_param(struct radeon_encoder *enc,
603 struct pipe_h265_enc_picture_desc *pic)
604 {
605 struct si_screen *sscreen = (struct si_screen *)enc->screen;
606
607 enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 =
608 pic->seq.log2_min_luma_coding_block_size_minus3;
609 enc->enc_pic.hevc_spec_misc.amp_disabled = !pic->seq.amp_enabled_flag;
610 enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled =
611 pic->seq.strong_intra_smoothing_enabled_flag;
612 enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag =
613 pic->pic.constrained_intra_pred_flag;
614 enc->enc_pic.hevc_spec_misc.cabac_init_flag = pic->slice.cabac_init_flag;
615 enc->enc_pic.hevc_spec_misc.half_pel_enabled = 1;
616 enc->enc_pic.hevc_spec_misc.quarter_pel_enabled = 1;
617 enc->enc_pic.hevc_spec_misc.transform_skip_disabled =
618 sscreen->info.vcn_ip_version < VCN_3_0_0 ||
619 !pic->pic.transform_skip_enabled_flag;
620 enc->enc_pic.hevc_spec_misc.cu_qp_delta_enabled_flag =
621 (sscreen->info.vcn_ip_version >= VCN_2_0_0 &&
622 pic->pic.cu_qp_delta_enabled_flag) ||
623 enc->enc_pic.enc_qp_map.qp_map_type ||
624 enc->enc_pic.rc_session_init.rate_control_method;
625 }
626
radeon_vcn_enc_hevc_get_rc_param(struct radeon_encoder * enc,struct pipe_h265_enc_picture_desc * pic)627 static void radeon_vcn_enc_hevc_get_rc_param(struct radeon_encoder *enc,
628 struct pipe_h265_enc_picture_desc *pic)
629 {
630 uint32_t frame_rate_den, frame_rate_num, max_qp;
631
632 enc->enc_pic.num_temporal_layers = pic->seq.num_temporal_layers ? pic->seq.num_temporal_layers : 1;
633 enc->enc_pic.temporal_id = MIN2(pic->pic.temporal_id, enc->enc_pic.num_temporal_layers - 1);
634
635 for (int i = 0; i < enc->enc_pic.num_temporal_layers; i++) {
636 enc->enc_pic.rc_layer_init[i].target_bit_rate = pic->rc[i].target_bitrate;
637 enc->enc_pic.rc_layer_init[i].peak_bit_rate = pic->rc[i].peak_bitrate;
638 frame_rate_den = pic->rc[i].frame_rate_den;
639 frame_rate_num = pic->rc[i].frame_rate_num;
640 radeon_vcn_enc_invalid_frame_rate(&frame_rate_den, &frame_rate_num);
641 enc->enc_pic.rc_layer_init[i].frame_rate_den = frame_rate_den;
642 enc->enc_pic.rc_layer_init[i].frame_rate_num = frame_rate_num;
643 enc->enc_pic.rc_layer_init[i].vbv_buffer_size = pic->rc[i].vbv_buffer_size;
644 enc->enc_pic.rc_layer_init[i].avg_target_bits_per_picture =
645 radeon_vcn_per_frame_integer(pic->rc[i].target_bitrate,
646 frame_rate_den,
647 frame_rate_num);
648 enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_integer =
649 radeon_vcn_per_frame_integer(pic->rc[i].peak_bitrate,
650 frame_rate_den,
651 frame_rate_num);
652 enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_fractional =
653 radeon_vcn_per_frame_frac(pic->rc[i].peak_bitrate,
654 frame_rate_den,
655 frame_rate_num);
656 }
657 enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rc[0].vbv_buf_lv;
658 enc->enc_pic.rc_per_pic.qp_obs = pic->rc[0].quant_i_frames;
659 enc->enc_pic.rc_per_pic.min_qp_app_obs = pic->rc[0].min_qp;
660 enc->enc_pic.rc_per_pic.max_qp_app_obs = pic->rc[0].max_qp ? pic->rc[0].max_qp : 51;
661 enc->enc_pic.rc_per_pic.qp_i = pic->rc[0].quant_i_frames;
662 enc->enc_pic.rc_per_pic.qp_p = pic->rc[0].quant_p_frames;
663 enc->enc_pic.rc_per_pic.min_qp_i = pic->rc[0].min_qp;
664 enc->enc_pic.rc_per_pic.min_qp_p = pic->rc[0].min_qp;
665 max_qp = pic->rc[0].max_qp ? pic->rc[0].max_qp : 51;
666 enc->enc_pic.rc_per_pic.max_qp_i = max_qp;
667 enc->enc_pic.rc_per_pic.max_qp_p = max_qp;
668 enc->enc_pic.rc_per_pic.enabled_filler_data = 0;
669 enc->enc_pic.rc_per_pic.skip_frame_enable = pic->rc[0].skip_frame_enable;
670 enc->enc_pic.rc_per_pic.enforce_hrd = pic->rc[0].enforce_hrd;
671 enc->enc_pic.rc_per_pic.qvbr_quality_level = pic->rc[0].vbr_quality_factor;
672 switch (pic->rc[0].rate_ctrl_method) {
673 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_DISABLE:
674 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
675 break;
676 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
677 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT:
678 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR;
679 enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rc[0].fill_data_enable;
680 break;
681 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
682 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE:
683 enc->enc_pic.rc_session_init.rate_control_method =
684 RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
685 break;
686 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_QUALITY_VARIABLE:
687 enc->enc_pic.rc_session_init.rate_control_method =
688 RENCODE_RATE_CONTROL_METHOD_QUALITY_VBR;
689 break;
690 default:
691 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
692 }
693 enc->enc_pic.rc_per_pic.max_au_size_obs = pic->rc[0].max_au_size;
694 enc->enc_pic.rc_per_pic.max_au_size_i = pic->rc[0].max_au_size;
695 enc->enc_pic.rc_per_pic.max_au_size_p = pic->rc[0].max_au_size;
696 }
697
radeon_vcn_enc_hevc_get_slice_ctrl_param(struct radeon_encoder * enc,struct pipe_h265_enc_picture_desc * pic)698 static void radeon_vcn_enc_hevc_get_slice_ctrl_param(struct radeon_encoder *enc,
699 struct pipe_h265_enc_picture_desc *pic)
700 {
701 uint32_t num_ctbs_total, num_ctbs_in_slice;
702
703 num_ctbs_total =
704 PIPE_ALIGN_IN_BLOCK_SIZE(pic->seq.pic_width_in_luma_samples, PIPE_H265_ENC_CTB_SIZE) *
705 PIPE_ALIGN_IN_BLOCK_SIZE(pic->seq.pic_height_in_luma_samples, PIPE_H265_ENC_CTB_SIZE);
706
707 if (pic->num_slice_descriptors <= 1) {
708 num_ctbs_in_slice = num_ctbs_total;
709 } else {
710 bool use_app_config = true;
711 num_ctbs_in_slice = pic->slices_descriptors[0].num_ctu_in_slice;
712
713 /* All slices must have equal size */
714 for (unsigned i = 1; i < pic->num_slice_descriptors - 1; i++) {
715 if (num_ctbs_in_slice != pic->slices_descriptors[i].num_ctu_in_slice)
716 use_app_config = false;
717 }
718 /* Except last one can be smaller */
719 if (pic->slices_descriptors[pic->num_slice_descriptors - 1].num_ctu_in_slice > num_ctbs_in_slice)
720 use_app_config = false;
721
722 if (!use_app_config) {
723 assert(num_ctbs_total >= pic->num_slice_descriptors);
724 num_ctbs_in_slice =
725 (num_ctbs_total + pic->num_slice_descriptors - 1) / pic->num_slice_descriptors;
726 }
727 }
728
729 num_ctbs_in_slice = MAX2(4, num_ctbs_in_slice);
730
731 enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS;
732 enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice =
733 num_ctbs_in_slice;
734 enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment =
735 num_ctbs_in_slice;
736 }
737
radeon_vcn_enc_hevc_get_param(struct radeon_encoder * enc,struct pipe_h265_enc_picture_desc * pic)738 static void radeon_vcn_enc_hevc_get_param(struct radeon_encoder *enc,
739 struct pipe_h265_enc_picture_desc *pic)
740 {
741 enc->enc_pic.hevc.desc = pic;
742 enc->enc_pic.picture_type = pic->picture_type;
743 enc->enc_pic.enc_params.reference_picture_index =
744 pic->ref_list0[0] == PIPE_H2645_LIST_REF_INVALID_ENTRY ? 0xffffffff : pic->ref_list0[0];
745 enc->enc_pic.enc_params.reconstructed_picture_index = pic->dpb_curr_pic;
746 enc->enc_pic.bit_depth_luma_minus8 = pic->seq.bit_depth_luma_minus8;
747 enc->enc_pic.bit_depth_chroma_minus8 = pic->seq.bit_depth_chroma_minus8;
748 enc->enc_pic.nal_unit_type = pic->pic.nal_unit_type;
749
750 if (enc->dpb_type == DPB_TIER_2) {
751 for (uint32_t i = 0; i < ARRAY_SIZE(pic->dpb); i++) {
752 struct pipe_video_buffer *buf = pic->dpb[i].buffer;
753 enc->enc_pic.dpb_bufs[i] =
754 buf ? vl_video_buffer_get_associated_data(buf, &enc->base) : NULL;
755 assert(!buf || enc->enc_pic.dpb_bufs[i]);
756 }
757 }
758
759 radeon_vcn_enc_hevc_get_session_param(enc, pic);
760 radeon_vcn_enc_hevc_get_dbk_param(enc, pic);
761 radeon_vcn_enc_hevc_get_rc_param(enc, pic);
762 radeon_vcn_enc_hevc_get_slice_ctrl_param(enc, pic);
763 radeon_vcn_enc_get_input_format_param(enc, &pic->base);
764 radeon_vcn_enc_get_output_format_param(enc, pic->seq.video_full_range_flag);
765 radeon_vcn_enc_get_intra_refresh_param(enc,
766 !(enc->enc_pic.hevc_deblock.deblocking_filter_disabled),
767 &pic->intra_refresh);
768 radeon_vcn_enc_get_roi_param(enc, &pic->roi);
769 radeon_vcn_enc_hevc_get_spec_misc_param(enc, pic);
770 radeon_vcn_enc_get_latency_param(enc);
771 radeon_vcn_enc_quality_modes(enc, &pic->quality_modes);
772 }
773
radeon_vcn_enc_av1_get_session_param(struct radeon_encoder * enc,struct pipe_av1_enc_picture_desc * pic)774 static void radeon_vcn_enc_av1_get_session_param(struct radeon_encoder *enc,
775 struct pipe_av1_enc_picture_desc *pic)
776 {
777 struct si_screen *sscreen = (struct si_screen *)enc->screen;
778
779 if (enc->enc_pic.session_init.aligned_picture_width)
780 return;
781
782 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_AV1;
783
784 uint32_t width = enc->enc_pic.pic_width_in_luma_samples;
785 uint32_t height = enc->enc_pic.pic_height_in_luma_samples;
786 uint32_t align_width, align_height;
787
788 if (sscreen->info.vcn_ip_version < VCN_5_0_0) {
789 align_width = PIPE_AV1_ENC_SB_SIZE;
790 align_height = 16;
791 enc->enc_pic.session_init.aligned_picture_width = align(width, align_width);
792 enc->enc_pic.session_init.aligned_picture_height = align(height, align_height);
793 if (!(height % 8) && (height % 16))
794 enc->enc_pic.session_init.aligned_picture_height = height + 2;
795 enc->enc_pic.av1.coded_width = enc->enc_pic.session_init.aligned_picture_width;
796 enc->enc_pic.av1.coded_height = enc->enc_pic.session_init.aligned_picture_height;
797 if (sscreen->info.vcn_ip_version == VCN_4_0_2 ||
798 sscreen->info.vcn_ip_version == VCN_4_0_5 ||
799 sscreen->info.vcn_ip_version == VCN_4_0_6)
800 enc->enc_pic.session_init.WA_flags = 1;
801 } else {
802 align_width = 8;
803 align_height = 2;
804 enc->enc_pic.session_init.aligned_picture_width = align(width, align_width);
805 enc->enc_pic.session_init.aligned_picture_height = align(height, align_height);
806 enc->enc_pic.av1.coded_width = width;
807 enc->enc_pic.av1.coded_height = height;
808 }
809
810 uint32_t padding_width = 0;
811 uint32_t padding_height = 0;
812 uint32_t max_padding_width = align_width - 2;
813 uint32_t max_padding_height = align_height - 2;
814
815 if (enc->enc_pic.session_init.aligned_picture_width > enc->source->width)
816 padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->source->width;
817 if (enc->enc_pic.session_init.aligned_picture_height > enc->source->height)
818 padding_height = enc->enc_pic.session_init.aligned_picture_height - enc->source->height;
819
820 /* Input surface can be smaller if the difference is within padding bounds. */
821 if (padding_width > max_padding_width || padding_height > max_padding_height)
822 RADEON_ENC_ERR("Input surface size doesn't match aligned size\n");
823
824 padding_width = MAX2(padding_width, enc->enc_pic.session_init.aligned_picture_width - width);
825 padding_height = MAX2(padding_height, enc->enc_pic.session_init.aligned_picture_height - height);
826
827 enc->enc_pic.session_init.padding_width = padding_width;
828 enc->enc_pic.session_init.padding_height = padding_height;
829 }
830
radeon_vcn_enc_av1_get_spec_misc_param(struct radeon_encoder * enc,struct pipe_av1_enc_picture_desc * pic)831 static void radeon_vcn_enc_av1_get_spec_misc_param(struct radeon_encoder *enc,
832 struct pipe_av1_enc_picture_desc *pic)
833 {
834 enc->enc_pic.av1_spec_misc.cdef_mode = pic->seq.seq_bits.enable_cdef;
835 enc->enc_pic.av1_spec_misc.disable_cdf_update = pic->disable_cdf_update;
836 enc->enc_pic.av1_spec_misc.disable_frame_end_update_cdf = pic->disable_frame_end_update_cdf;
837 enc->enc_pic.av1_spec_misc.palette_mode_enable = pic->palette_mode_enable;
838 enc->enc_pic.av1_spec_misc.cdef_bits = pic->cdef.cdef_bits;
839 enc->enc_pic.av1_spec_misc.cdef_damping_minus3 = pic->cdef.cdef_damping_minus_3;
840 for (int i = 0; i < (pic->cdef.cdef_bits << 1); i++ ){
841 enc->enc_pic.av1_spec_misc.cdef_y_pri_strength[i] = (pic->cdef.cdef_y_strengths[i] >> 2);
842 enc->enc_pic.av1_spec_misc.cdef_y_sec_strength[i] = (pic->cdef.cdef_y_strengths[i] & 0x3);
843 enc->enc_pic.av1_spec_misc.cdef_uv_pri_strength[i] = (pic->cdef.cdef_uv_strengths[i] >> 2);
844 enc->enc_pic.av1_spec_misc.cdef_uv_sec_strength[i] = (pic->cdef.cdef_uv_strengths[i] & 0x3);
845 }
846
847 enc->enc_pic.av1_spec_misc.delta_q_y_dc = pic->quantization.y_dc_delta_q;
848 enc->enc_pic.av1_spec_misc.delta_q_u_dc = pic->quantization.u_dc_delta_q;
849 enc->enc_pic.av1_spec_misc.delta_q_u_ac = pic->quantization.u_ac_delta_q;
850 enc->enc_pic.av1_spec_misc.delta_q_v_dc = pic->quantization.v_dc_delta_q;
851 enc->enc_pic.av1_spec_misc.delta_q_v_ac = pic->quantization.v_ac_delta_q;
852
853 if (enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY)
854 enc->enc_pic.av1_spec_misc.separate_delta_q =
855 (pic->quantization.u_dc_delta_q != pic->quantization.v_dc_delta_q) ||
856 (pic->quantization.u_ac_delta_q != pic->quantization.v_ac_delta_q);
857
858 if (enc->enc_pic.disable_screen_content_tools) {
859 enc->enc_pic.force_integer_mv = 0;
860 enc->enc_pic.av1_spec_misc.palette_mode_enable = 0;
861 }
862
863 if (enc->enc_pic.force_integer_mv)
864 enc->enc_pic.av1_spec_misc.mv_precision = RENCODE_AV1_MV_PRECISION_FORCE_INTEGER_MV;
865 else
866 enc->enc_pic.av1_spec_misc.mv_precision = RENCODE_AV1_MV_PRECISION_ALLOW_HIGH_PRECISION;
867 }
868
radeon_vcn_enc_av1_get_rc_param(struct radeon_encoder * enc,struct pipe_av1_enc_picture_desc * pic)869 static void radeon_vcn_enc_av1_get_rc_param(struct radeon_encoder *enc,
870 struct pipe_av1_enc_picture_desc *pic)
871 {
872 uint32_t frame_rate_den, frame_rate_num, min_qp, max_qp;
873
874 enc->enc_pic.num_temporal_layers = pic->seq.num_temporal_layers ? pic->seq.num_temporal_layers : 1;
875 enc->enc_pic.temporal_id = MIN2(pic->temporal_id, enc->enc_pic.num_temporal_layers - 1);
876
877 for (int i = 0; i < ARRAY_SIZE(enc->enc_pic.rc_layer_init); i++) {
878 enc->enc_pic.rc_layer_init[i].target_bit_rate = pic->rc[i].target_bitrate;
879 enc->enc_pic.rc_layer_init[i].peak_bit_rate = pic->rc[i].peak_bitrate;
880 frame_rate_den = pic->rc[i].frame_rate_den;
881 frame_rate_num = pic->rc[i].frame_rate_num;
882 radeon_vcn_enc_invalid_frame_rate(&frame_rate_den, &frame_rate_num);
883 enc->enc_pic.rc_layer_init[i].frame_rate_den = frame_rate_den;
884 enc->enc_pic.rc_layer_init[i].frame_rate_num = frame_rate_num;
885 enc->enc_pic.rc_layer_init[i].vbv_buffer_size = pic->rc[i].vbv_buffer_size;
886 enc->enc_pic.rc_layer_init[i].avg_target_bits_per_picture =
887 radeon_vcn_per_frame_integer(pic->rc[i].target_bitrate,
888 frame_rate_den,
889 frame_rate_num);
890 enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_integer =
891 radeon_vcn_per_frame_integer(pic->rc[i].peak_bitrate,
892 frame_rate_den,
893 frame_rate_num);
894 enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_fractional =
895 radeon_vcn_per_frame_frac(pic->rc[i].peak_bitrate,
896 frame_rate_den,
897 frame_rate_num);
898 }
899 enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rc[0].vbv_buf_lv;
900 enc->enc_pic.rc_per_pic.qp_obs = pic->rc[0].qp;
901 enc->enc_pic.rc_per_pic.min_qp_app_obs = pic->rc[0].min_qp ? pic->rc[0].min_qp : 1;
902 enc->enc_pic.rc_per_pic.max_qp_app_obs = pic->rc[0].max_qp ? pic->rc[0].max_qp : 255;
903 enc->enc_pic.rc_per_pic.qp_i = pic->rc[0].qp;
904 enc->enc_pic.rc_per_pic.qp_p = pic->rc[0].qp_inter;
905 enc->enc_pic.rc_per_pic.qp_b = pic->rc[0].qp_inter;
906 min_qp = pic->rc[0].min_qp ? pic->rc[0].min_qp : 1;
907 enc->enc_pic.rc_per_pic.min_qp_i = min_qp;
908 enc->enc_pic.rc_per_pic.min_qp_p = min_qp;
909 enc->enc_pic.rc_per_pic.min_qp_b = min_qp;
910 max_qp = pic->rc[0].max_qp ? pic->rc[0].max_qp : 255;
911 enc->enc_pic.rc_per_pic.max_qp_i = max_qp;
912 enc->enc_pic.rc_per_pic.max_qp_p = max_qp;
913 enc->enc_pic.rc_per_pic.max_qp_b = max_qp;
914 enc->enc_pic.rc_per_pic.enabled_filler_data = 0;
915 enc->enc_pic.rc_per_pic.skip_frame_enable = pic->rc[0].skip_frame_enable;
916 enc->enc_pic.rc_per_pic.enforce_hrd = pic->rc[0].enforce_hrd;
917 enc->enc_pic.rc_per_pic.qvbr_quality_level = (pic->rc[0].vbr_quality_factor + 2) / 5;
918 switch (pic->rc[0].rate_ctrl_method) {
919 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_DISABLE:
920 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
921 break;
922 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
923 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT:
924 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR;
925 enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rc[0].fill_data_enable;
926 break;
927 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
928 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE:
929 enc->enc_pic.rc_session_init.rate_control_method =
930 RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
931 break;
932 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_QUALITY_VARIABLE:
933 enc->enc_pic.rc_session_init.rate_control_method =
934 RENCODE_RATE_CONTROL_METHOD_QUALITY_VBR;
935 break;
936 default:
937 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
938 }
939 enc->enc_pic.rc_per_pic.max_au_size_obs = pic->rc[0].max_au_size;
940 enc->enc_pic.rc_per_pic.max_au_size_i = pic->rc[0].max_au_size;
941 enc->enc_pic.rc_per_pic.max_au_size_p = pic->rc[0].max_au_size;
942 enc->enc_pic.rc_per_pic.max_au_size_b = pic->rc[0].max_au_size;
943 }
944
radeon_vcn_enc_av1_get_tile_config(struct radeon_encoder * enc,struct pipe_av1_enc_picture_desc * pic)945 static void radeon_vcn_enc_av1_get_tile_config(struct radeon_encoder *enc,
946 struct pipe_av1_enc_picture_desc *pic)
947 {
948 uint32_t num_tile_cols, num_tile_rows;
949
950 num_tile_cols = MIN2(RENCODE_AV1_TILE_CONFIG_MAX_NUM_COLS, pic->tile_cols);
951 num_tile_rows = MIN2(RENCODE_AV1_TILE_CONFIG_MAX_NUM_ROWS, pic->tile_rows);
952
953 enc->enc_pic.av1_tile_config.uniform_tile_spacing = !!(pic->uniform_tile_spacing);
954 enc->enc_pic.av1_tile_config.num_tile_cols = pic->tile_cols;
955 enc->enc_pic.av1_tile_config.num_tile_rows = pic->tile_rows;
956 enc->enc_pic.av1_tile_config.num_tile_groups = pic->num_tile_groups;
957 for (int i = 0; i < num_tile_cols; i++ )
958 enc->enc_pic.av1_tile_config.tile_widths[i] = pic->width_in_sbs_minus_1[i] + 1;
959 for (int i = 0; i < num_tile_rows; i++ )
960 enc->enc_pic.av1_tile_config.tile_height[i] = pic->height_in_sbs_minus_1[i] + 1;
961 for (int i = 0; i < num_tile_cols * num_tile_rows; i++ ) {
962 enc->enc_pic.av1_tile_config.tile_groups[i].start =
963 (uint32_t)pic->tile_groups[i].tile_group_start;
964 enc->enc_pic.av1_tile_config.tile_groups[i].end =
965 (uint32_t)pic->tile_groups[i].tile_group_end;
966 }
967 enc->enc_pic.av1_tile_config.context_update_tile_id = pic->context_update_tile_id;
968 }
969
radeon_vcn_enc_av1_get_param(struct radeon_encoder * enc,struct pipe_av1_enc_picture_desc * pic)970 static void radeon_vcn_enc_av1_get_param(struct radeon_encoder *enc,
971 struct pipe_av1_enc_picture_desc *pic)
972 {
973 struct si_screen *sscreen = (struct si_screen *)enc->screen;
974 struct radeon_enc_pic *enc_pic = &enc->enc_pic;
975
976 enc_pic->av1.desc = pic;
977 enc_pic->frame_type = pic->frame_type;
978 enc_pic->bit_depth_luma_minus8 = enc_pic->bit_depth_chroma_minus8 =
979 pic->seq.bit_depth_minus8;
980 enc_pic->pic_width_in_luma_samples = pic->seq.pic_width_in_luma_samples;
981 enc_pic->pic_height_in_luma_samples = pic->seq.pic_height_in_luma_samples;
982 enc_pic->enable_error_resilient_mode = pic->error_resilient_mode;
983 enc_pic->force_integer_mv = pic->force_integer_mv;
984 enc_pic->disable_screen_content_tools = !pic->allow_screen_content_tools;
985 enc_pic->is_obu_frame = pic->enable_frame_obu;
986
987 enc_pic->enc_params.reference_picture_index =
988 pic->ref_list0[0] == PIPE_H2645_LIST_REF_INVALID_ENTRY ?
989 0xffffffff : pic->dpb_ref_frame_idx[pic->ref_list0[0]];
990 enc_pic->enc_params.reconstructed_picture_index = pic->dpb_curr_pic;
991
992 if (sscreen->info.vcn_ip_version >= VCN_5_0_0) {
993 for (uint32_t i = 0; i < RENCODE_AV1_REFS_PER_FRAME; i++)
994 enc_pic->av1_enc_params.ref_frames[i] = pic->dpb_ref_frame_idx[i];
995
996 enc_pic->av1_enc_params.lsm_reference_frame_index[0] =
997 pic->ref_list0[0] == PIPE_H2645_LIST_REF_INVALID_ENTRY ? 0xffffffff : pic->ref_list0[0];
998 enc_pic->av1_enc_params.lsm_reference_frame_index[1] = 0xffffffff;
999 enc_pic->av1.compound = false;
1000
1001 if (pic->ref_list1[0] != PIPE_H2645_LIST_REF_INVALID_ENTRY) {
1002 enc_pic->av1.compound = true; /* BIDIR_COMP */
1003 enc_pic->av1_enc_params.lsm_reference_frame_index[1] = pic->ref_list1[0];
1004 } else if (pic->ref_list0[1] != PIPE_H2645_LIST_REF_INVALID_ENTRY) {
1005 enc_pic->av1.compound = true; /* UNIDIR_COMP */
1006 enc_pic->av1_enc_params.lsm_reference_frame_index[1] = pic->ref_list0[1];
1007 }
1008
1009 uint32_t skip_frames[2];
1010 enc_pic->av1.skip_mode_allowed = radeon_enc_av1_skip_mode_allowed(enc, skip_frames);
1011
1012 if (enc_pic->av1.compound) {
1013 bool disallow_skip_mode = enc_pic->av1_spec_misc.disallow_skip_mode;
1014 enc_pic->av1_spec_misc.disallow_skip_mode = !enc_pic->av1.skip_mode_allowed;
1015 /* Skip mode frames must match reference frames */
1016 if (enc_pic->av1.skip_mode_allowed) {
1017 enc_pic->av1_spec_misc.disallow_skip_mode =
1018 skip_frames[0] != enc_pic->av1_enc_params.lsm_reference_frame_index[0] ||
1019 skip_frames[1] != enc_pic->av1_enc_params.lsm_reference_frame_index[1];
1020 }
1021 enc->need_spec_misc = disallow_skip_mode != enc_pic->av1_spec_misc.disallow_skip_mode;
1022 } else {
1023 enc->need_spec_misc = false;
1024 }
1025 }
1026
1027 if (enc->dpb_type == DPB_TIER_2) {
1028 for (uint32_t i = 0; i < ARRAY_SIZE(pic->dpb); i++) {
1029 struct pipe_video_buffer *buf = pic->dpb[i].buffer;
1030 enc->enc_pic.dpb_bufs[i] =
1031 buf ? vl_video_buffer_get_associated_data(buf, &enc->base) : NULL;
1032 assert(!buf || enc->enc_pic.dpb_bufs[i]);
1033 }
1034 }
1035
1036 radeon_vcn_enc_av1_get_session_param(enc, pic);
1037 radeon_vcn_enc_av1_get_spec_misc_param(enc, pic);
1038 radeon_vcn_enc_av1_get_rc_param(enc, pic);
1039 radeon_vcn_enc_av1_get_tile_config(enc, pic);
1040 radeon_vcn_enc_get_input_format_param(enc, &pic->base);
1041 radeon_vcn_enc_get_output_format_param(enc, pic->seq.color_config.color_range);
1042 /* loop filter enabled all the time */
1043 radeon_vcn_enc_get_intra_refresh_param(enc,
1044 true,
1045 &pic->intra_refresh);
1046 radeon_vcn_enc_get_roi_param(enc, &pic->roi);
1047 radeon_vcn_enc_get_latency_param(enc);
1048 radeon_vcn_enc_quality_modes(enc, &pic->quality_modes);
1049 }
1050
radeon_vcn_enc_get_param(struct radeon_encoder * enc,struct pipe_picture_desc * picture)1051 static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
1052 {
1053 enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size - enc->bs_offset;
1054
1055 if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC)
1056 radeon_vcn_enc_h264_get_param(enc, (struct pipe_h264_enc_picture_desc *)picture);
1057 else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC)
1058 radeon_vcn_enc_hevc_get_param(enc, (struct pipe_h265_enc_picture_desc *)picture);
1059 else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_AV1)
1060 radeon_vcn_enc_av1_get_param(enc, (struct pipe_av1_enc_picture_desc *)picture);
1061 }
1062
flush(struct radeon_encoder * enc,unsigned flags,struct pipe_fence_handle ** fence)1063 static int flush(struct radeon_encoder *enc, unsigned flags, struct pipe_fence_handle **fence)
1064 {
1065 struct si_screen *sscreen = (struct si_screen *)enc->screen;
1066
1067 if (sscreen->debug_flags & DBG(IB)) {
1068 struct ac_ib_parser ib_parser = {
1069 .f = stderr,
1070 .ib = enc->cs.current.buf,
1071 .num_dw = enc->cs.current.cdw,
1072 .gfx_level = sscreen->info.gfx_level,
1073 .vcn_version = sscreen->info.vcn_ip_version,
1074 .family = sscreen->info.family,
1075 .ip_type = AMD_IP_VCN_ENC,
1076 };
1077 ac_parse_ib(&ib_parser, "IB");
1078 }
1079
1080 return enc->ws->cs_flush(&enc->cs, flags, fence);
1081 }
1082
radeon_enc_flush(struct pipe_video_codec * encoder)1083 static void radeon_enc_flush(struct pipe_video_codec *encoder)
1084 {
1085 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
1086 flush(enc, PIPE_FLUSH_ASYNC, NULL);
1087 }
1088
radeon_enc_cs_flush(void * ctx,unsigned flags,struct pipe_fence_handle ** fence)1089 static void radeon_enc_cs_flush(void *ctx, unsigned flags, struct pipe_fence_handle **fence)
1090 {
1091 // just ignored
1092 }
1093
1094 /* configure reconstructed picture offset */
radeon_enc_rec_offset(rvcn_enc_reconstructed_picture_t * recon,uint32_t * offset,uint32_t luma_size,uint32_t chroma_size,bool is_av1)1095 static void radeon_enc_rec_offset(rvcn_enc_reconstructed_picture_t *recon,
1096 uint32_t *offset,
1097 uint32_t luma_size,
1098 uint32_t chroma_size,
1099 bool is_av1)
1100 {
1101 if (offset) {
1102 recon->luma_offset = *offset;
1103 *offset += luma_size;
1104 recon->chroma_offset = *offset;
1105 *offset += chroma_size;
1106 if (is_av1) {
1107 recon->av1.av1_cdf_frame_context_offset = *offset;
1108 *offset += RENCODE_AV1_FRAME_CONTEXT_CDF_TABLE_SIZE;
1109 recon->av1.av1_cdef_algorithm_context_offset = *offset;
1110 *offset += RENCODE_AV1_CDEF_ALGORITHM_FRAME_CONTEXT_SIZE;
1111 }
1112 } else {
1113 recon->luma_offset = 0;
1114 recon->chroma_offset = 0;
1115 recon->av1.av1_cdf_frame_context_offset = 0;
1116 recon->av1.av1_cdef_algorithm_context_offset = 0;
1117 }
1118 recon->chroma_v_offset = 0;
1119 }
1120
1121 /* configure reconstructed picture offset */
radeon_enc_rec_meta_offset(rvcn_enc_reconstructed_picture_t * recon,uint32_t * offset,uint32_t total_coloc_size,uint32_t alignment,bool has_b,bool is_h264,bool is_av1)1122 static void radeon_enc_rec_meta_offset(rvcn_enc_reconstructed_picture_t *recon,
1123 uint32_t *offset,
1124 uint32_t total_coloc_size,
1125 uint32_t alignment,
1126 bool has_b,
1127 bool is_h264,
1128 bool is_av1)
1129 {
1130 uint32_t context_offset = 0;
1131
1132 if (offset) {
1133 recon->frame_context_buffer_offset = *offset;
1134 recon->encode_metadata_offset = context_offset;
1135 context_offset += RENCODE_MAX_METADATA_BUFFER_SIZE_PER_FRAME;
1136 if (is_h264) {
1137 if (has_b) {
1138 recon->h264.colloc_buffer_offset = context_offset;
1139 context_offset += total_coloc_size;
1140 } else
1141 recon->h264.colloc_buffer_offset = RENCODE_INVALID_COLOC_OFFSET;
1142 }
1143
1144 if (is_av1) {
1145 recon->av1.av1_cdf_frame_context_offset = context_offset;
1146 context_offset += RENCODE_AV1_FRAME_CONTEXT_CDF_TABLE_SIZE;
1147 recon->av1.av1_cdef_algorithm_context_offset = context_offset;
1148 context_offset += RENCODE_AV1_CDEF_ALGORITHM_FRAME_CONTEXT_SIZE;
1149 }
1150 context_offset = align(context_offset, alignment);
1151 *offset += context_offset;
1152 } else {
1153 recon->frame_context_buffer_offset = 0;
1154 recon->encode_metadata_offset = 0;
1155 recon->av1.av1_cdf_frame_context_offset = 0;
1156 recon->av1.av1_cdef_algorithm_context_offset = 0;
1157 }
1158 }
1159
setup_cdf(struct radeon_encoder * enc)1160 static int setup_cdf(struct radeon_encoder *enc)
1161 {
1162 unsigned char *p_cdf = NULL;
1163
1164 if (!enc->cdf ||
1165 !si_vid_create_buffer(enc->screen,
1166 enc->cdf,
1167 VCN_ENC_AV1_DEFAULT_CDF_SIZE,
1168 PIPE_USAGE_DYNAMIC)) {
1169 RADEON_ENC_ERR("Can't create CDF buffer.\n");
1170 goto error;
1171 }
1172
1173 p_cdf = enc->ws->buffer_map(enc->ws,
1174 enc->cdf->res->buf,
1175 &enc->cs,
1176 PIPE_MAP_READ_WRITE | RADEON_MAP_TEMPORARY);
1177 if (!p_cdf)
1178 goto error;
1179
1180 memcpy(p_cdf, rvcn_av1_cdf_default_table, VCN_ENC_AV1_DEFAULT_CDF_SIZE);
1181 enc->ws->buffer_unmap(enc->ws, enc->cdf->res->buf);
1182
1183 return 0;
1184
1185 error:
1186 return -1;
1187 }
1188
pre_encode_size(struct radeon_encoder * enc,uint32_t * offset)1189 static void pre_encode_size(struct radeon_encoder *enc,
1190 uint32_t *offset)
1191 {
1192 bool is_h264 = u_reduce_video_profile(enc->base.profile)
1193 == PIPE_VIDEO_FORMAT_MPEG4_AVC;
1194 uint32_t rec_alignment = is_h264 ? 16 : 64;
1195 uint32_t aligned_width = align(enc->base.width, rec_alignment);
1196 uint32_t aligned_height = align(enc->base.height, rec_alignment);
1197 struct radeon_enc_pic *enc_pic = &enc->enc_pic;
1198 bool has_b = enc_pic->spec_misc.b_picture_enabled; /* for h264 only */
1199 uint32_t pre_size = DIV_ROUND_UP((aligned_width >> 2), rec_alignment) *
1200 DIV_ROUND_UP((aligned_height >> 2), rec_alignment);
1201 uint32_t full_size = DIV_ROUND_UP(aligned_width, rec_alignment) *
1202 DIV_ROUND_UP(aligned_height, rec_alignment);
1203
1204 enc_pic->ctx_buf.two_pass_search_center_map_offset = *offset;
1205 if (is_h264 && !has_b)
1206 *offset += align((pre_size * 4 + full_size) * sizeof(uint32_t), enc->alignment);
1207 else if (!is_h264)
1208 *offset += align((pre_size * 52 + full_size) * sizeof(uint32_t), enc->alignment);
1209 }
1210
setup_dpb(struct radeon_encoder * enc,uint32_t num_reconstructed_pictures)1211 static int setup_dpb(struct radeon_encoder *enc, uint32_t num_reconstructed_pictures)
1212 {
1213 struct si_screen *sscreen = (struct si_screen *)enc->screen;
1214 bool is_h264 = u_reduce_video_profile(enc->base.profile)
1215 == PIPE_VIDEO_FORMAT_MPEG4_AVC;
1216 bool is_av1 = u_reduce_video_profile(enc->base.profile)
1217 == PIPE_VIDEO_FORMAT_AV1;
1218 uint32_t rec_alignment = is_h264 ? 16 : 64;
1219 uint32_t aligned_width = align(enc->base.width, rec_alignment);
1220 uint32_t aligned_height = align(enc->base.height, rec_alignment);
1221 uint32_t pitch = align(aligned_width, enc->alignment);
1222 uint32_t luma_size, chroma_size, offset;
1223 struct radeon_enc_pic *enc_pic = &enc->enc_pic;
1224 int i;
1225 bool has_b = enc_pic->spec_misc.b_picture_enabled; /* for h264 only */
1226 uint32_t aligned_dpb_height = MAX2(256, aligned_height);
1227 uint32_t total_coloc_bytes = (align((aligned_width / 16), 64) / 2)
1228 * (aligned_height / 16);
1229
1230 luma_size = align(pitch * aligned_dpb_height , enc->alignment);
1231 chroma_size = align(luma_size / 2 , enc->alignment);
1232 if (enc_pic->bit_depth_luma_minus8 || enc_pic->bit_depth_chroma_minus8) {
1233 luma_size *= 2;
1234 chroma_size *= 2;
1235 }
1236
1237 assert(num_reconstructed_pictures <= RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES);
1238
1239 enc_pic->ctx_buf.rec_luma_pitch = pitch;
1240 enc_pic->ctx_buf.pre_encode_picture_luma_pitch = pitch;
1241 enc_pic->ctx_buf.num_reconstructed_pictures = num_reconstructed_pictures;
1242 enc_pic->total_coloc_bytes = total_coloc_bytes;
1243
1244 offset = 0;
1245 enc->metadata_size = 0;
1246 if (sscreen->info.vcn_ip_version < VCN_5_0_0) {
1247 enc_pic->ctx_buf.rec_chroma_pitch = pitch;
1248 enc_pic->ctx_buf.pre_encode_picture_chroma_pitch = pitch;
1249 if (has_b) {
1250 enc_pic->ctx_buf.colloc_buffer_offset = offset;
1251 offset += total_coloc_bytes;
1252 } else
1253 enc_pic->ctx_buf.colloc_buffer_offset = 0;
1254
1255 if (enc_pic->quality_modes.pre_encode_mode)
1256 pre_encode_size(enc, &offset);
1257 else
1258 enc_pic->ctx_buf.two_pass_search_center_map_offset = 0;
1259
1260 if (enc_pic->quality_modes.pre_encode_mode) {
1261 enc_pic->ctx_buf.pre_encode_input_picture.rgb.red_offset = offset;
1262 offset += luma_size;
1263 enc_pic->ctx_buf.pre_encode_input_picture.rgb.green_offset = offset;
1264 offset += luma_size;
1265 enc_pic->ctx_buf.pre_encode_input_picture.rgb.blue_offset = offset;
1266 offset += luma_size;
1267 }
1268
1269 if (is_av1) {
1270 enc_pic->ctx_buf.av1.av1_sdb_intermediate_context_offset = offset;
1271 offset += RENCODE_AV1_SDB_FRAME_CONTEXT_SIZE;
1272 }
1273
1274 for (i = 0; i < num_reconstructed_pictures; i++) {
1275 radeon_enc_rec_offset(&enc_pic->ctx_buf.reconstructed_pictures[i],
1276 &offset, luma_size, chroma_size, is_av1);
1277
1278 if (enc_pic->quality_modes.pre_encode_mode)
1279 radeon_enc_rec_offset(&enc_pic->ctx_buf.pre_encode_reconstructed_pictures[i],
1280 &offset, luma_size, chroma_size, is_av1);
1281 }
1282
1283 for (; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
1284 radeon_enc_rec_offset(&enc_pic->ctx_buf.reconstructed_pictures[i],
1285 NULL, 0, 0, false);
1286 if (enc_pic->quality_modes.pre_encode_mode)
1287 radeon_enc_rec_offset(&enc_pic->ctx_buf.pre_encode_reconstructed_pictures[i],
1288 NULL, 0, 0, false);
1289 }
1290
1291 enc->dpb_size = offset;
1292 } else { /* vcn 5.0 */
1293 enc_pic->ctx_buf.rec_chroma_pitch = pitch / 2;
1294 enc_pic->ctx_buf.pre_encode_picture_chroma_pitch = pitch / 2;
1295 /* dpb buffer */
1296 if (is_av1) {
1297 enc_pic->ctx_buf.av1.av1_sdb_intermediate_context_offset = offset;
1298 offset += RENCODE_AV1_SDB_FRAME_CONTEXT_SIZE;
1299 } else
1300 enc_pic->ctx_buf.av1.av1_sdb_intermediate_context_offset = 0;
1301
1302 if (enc_pic->quality_modes.pre_encode_mode) {
1303 enc_pic->ctx_buf.pre_encode_input_picture.rgb.red_offset = offset;
1304 offset += luma_size;
1305 enc_pic->ctx_buf.pre_encode_input_picture.rgb.green_offset = offset;
1306 offset += luma_size;
1307 enc_pic->ctx_buf.pre_encode_input_picture.rgb.blue_offset = offset;
1308 offset += luma_size;
1309 }
1310
1311 for (i = 0; i < num_reconstructed_pictures; i++) {
1312 radeon_enc_rec_offset(&enc_pic->ctx_buf.reconstructed_pictures[i],
1313 &offset, luma_size, chroma_size, false);
1314
1315 if (enc_pic->quality_modes.pre_encode_mode)
1316 radeon_enc_rec_offset(&enc_pic->ctx_buf.pre_encode_reconstructed_pictures[i],
1317 &offset, luma_size, chroma_size, false);
1318 }
1319
1320 for (; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
1321 radeon_enc_rec_offset(&enc_pic->ctx_buf.reconstructed_pictures[i],
1322 NULL, 0, 0, false);
1323 if (enc_pic->quality_modes.pre_encode_mode)
1324 radeon_enc_rec_offset(&enc_pic->ctx_buf.pre_encode_reconstructed_pictures[i],
1325 NULL, 0, 0, false);
1326 }
1327
1328 enc->dpb_size = offset;
1329
1330 /* meta buffer*/
1331 offset = 0;
1332 if (enc_pic->quality_modes.pre_encode_mode)
1333 pre_encode_size(enc, &offset);
1334 else
1335 enc_pic->ctx_buf.two_pass_search_center_map_offset = 0;
1336
1337 for (i = 0; i < num_reconstructed_pictures; i++) {
1338 radeon_enc_rec_meta_offset(&enc_pic->ctx_buf.reconstructed_pictures[i],
1339 &offset, total_coloc_bytes, enc->alignment, has_b, is_h264, is_av1);
1340 if (enc_pic->quality_modes.pre_encode_mode)
1341 radeon_enc_rec_meta_offset(&enc_pic->ctx_buf.pre_encode_reconstructed_pictures[i],
1342 &offset, total_coloc_bytes, enc->alignment, has_b, is_h264, is_av1);
1343 }
1344 for (; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
1345 radeon_enc_rec_meta_offset(&enc_pic->ctx_buf.reconstructed_pictures[i],
1346 NULL, 0, 0, false, false, false);
1347 if (enc_pic->quality_modes.pre_encode_mode)
1348 radeon_enc_rec_meta_offset(&enc_pic->ctx_buf.pre_encode_reconstructed_pictures[i],
1349 NULL, 0, 0, false, false, false);
1350 }
1351 enc->metadata_size = offset;
1352 }
1353
1354 enc->dpb_slots = num_reconstructed_pictures;
1355
1356 return enc->dpb_size;
1357 }
1358
1359 /* each block (MB/CTB/SB) has one QP/QI value */
roi_buffer_size(struct radeon_encoder * enc)1360 static uint32_t roi_buffer_size(struct radeon_encoder *enc)
1361 {
1362 uint32_t pitch_size_in_dword = 0;
1363 rvcn_enc_qp_map_t *qp_map = &enc->enc_pic.enc_qp_map;
1364
1365 if ( qp_map->version == RENCODE_QP_MAP_LEGACY){
1366 pitch_size_in_dword = qp_map->width_in_block;
1367 qp_map->qp_map_pitch = qp_map->width_in_block;
1368 } else {
1369 /* two units merge into 1 dword */
1370 pitch_size_in_dword = DIV_ROUND_UP(qp_map->width_in_block, 2);
1371 qp_map->qp_map_pitch = pitch_size_in_dword * 2;
1372 }
1373
1374 return pitch_size_in_dword * qp_map->height_in_block * sizeof(uint32_t);
1375 }
1376
arrange_qp_map(void * start,struct rvcn_enc_qp_map_region * regin,rvcn_enc_qp_map_t * map)1377 static void arrange_qp_map(void *start,
1378 struct rvcn_enc_qp_map_region *regin,
1379 rvcn_enc_qp_map_t *map)
1380 {
1381 uint32_t i, j;
1382 uint32_t offset;
1383 uint32_t num_in_x = MIN2(regin->x_in_unit + regin->width_in_unit, map->width_in_block)
1384 - regin->x_in_unit;
1385 uint32_t num_in_y = MIN2(regin->y_in_unit + regin->height_in_unit, map->height_in_block)
1386 - regin->y_in_unit;;
1387
1388 for (j = 0; j < num_in_y; j++) {
1389 for (i = 0; i < num_in_x; i++) {
1390 offset = regin->x_in_unit + i + (regin->y_in_unit + j) * map->qp_map_pitch;
1391 if (map->version == RENCODE_QP_MAP_LEGACY)
1392 *((uint32_t *)start + offset) = (int32_t)regin->qp_delta;
1393 else
1394 *((int16_t *)start + offset) =
1395 (int16_t)(regin->qp_delta << RENCODE_QP_MAP_UNIFIED_QP_BITS_SHIFT);
1396 }
1397 }
1398 }
1399
1400 /* Arrange roi map values according to the input regions.
1401 * The arrangment will consider the lower sequence region
1402 * higher priority and that could overlap the higher sequence
1403 * map region. */
generate_roi_map(struct radeon_encoder * enc)1404 static int generate_roi_map(struct radeon_encoder *enc)
1405 {
1406 uint32_t width_in_block, height_in_block;
1407 uint32_t i;
1408 void *p_roi = NULL;
1409
1410 radeon_vcn_enc_blocks_in_frame(enc, &width_in_block, &height_in_block);
1411
1412 p_roi = enc->ws->buffer_map(enc->ws,
1413 enc->roi->res->buf,
1414 &enc->cs,
1415 PIPE_MAP_READ_WRITE | RADEON_MAP_TEMPORARY);
1416 if (!p_roi)
1417 goto error;
1418
1419 memset(p_roi, 0, enc->roi_size);
1420
1421 for (i = 0; i < ARRAY_SIZE(enc->enc_pic.enc_qp_map.map); i++) {
1422 struct rvcn_enc_qp_map_region *region = &enc->enc_pic.enc_qp_map.map[i];
1423 if (region->is_valid)
1424 arrange_qp_map(p_roi, region, &enc->enc_pic.enc_qp_map);
1425 }
1426
1427 enc->ws->buffer_unmap(enc->ws, enc->roi->res->buf);
1428 return 0;
1429 error:
1430 return -1;
1431 }
1432
radeon_enc_begin_frame(struct pipe_video_codec * encoder,struct pipe_video_buffer * source,struct pipe_picture_desc * picture)1433 static void radeon_enc_begin_frame(struct pipe_video_codec *encoder,
1434 struct pipe_video_buffer *source,
1435 struct pipe_picture_desc *picture)
1436 {
1437 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
1438 struct si_screen *sscreen = (struct si_screen *)enc->screen;
1439 struct vl_video_buffer *vid_buf = (struct vl_video_buffer *)source;
1440 unsigned dpb_slots = 0;
1441
1442 enc->source = source;
1443 enc->need_rate_control = false;
1444 enc->need_rc_per_pic = false;
1445
1446 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
1447 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
1448 dpb_slots = MAX2(pic->seq.max_num_ref_frames + 1, pic->dpb_size);
1449 enc->need_rate_control =
1450 (enc->enc_pic.rc_layer_init[0].target_bit_rate != pic->rate_ctrl[0].target_bitrate) ||
1451 (enc->enc_pic.rc_layer_init[0].frame_rate_num != pic->rate_ctrl[0].frame_rate_num) ||
1452 (enc->enc_pic.rc_layer_init[0].frame_rate_den != pic->rate_ctrl[0].frame_rate_den);
1453
1454 enc->need_rc_per_pic =
1455 (enc->enc_pic.rc_per_pic.qp_i != pic->quant_i_frames) ||
1456 (enc->enc_pic.rc_per_pic.qp_p != pic->quant_p_frames) ||
1457 (enc->enc_pic.rc_per_pic.qp_b != pic->quant_b_frames) ||
1458 (enc->enc_pic.rc_per_pic.max_au_size_i != pic->rate_ctrl[0].max_au_size) ||
1459 (enc->enc_pic.rc_per_pic.qvbr_quality_level != pic->rate_ctrl[0].vbr_quality_factor);
1460 } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
1461 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
1462 dpb_slots = MAX2(pic->seq.sps_max_dec_pic_buffering_minus1[0] + 1, pic->dpb_size);
1463 enc->need_rate_control =
1464 (enc->enc_pic.rc_layer_init[0].target_bit_rate != pic->rc[0].target_bitrate) ||
1465 (enc->enc_pic.rc_layer_init[0].frame_rate_num != pic->rc[0].frame_rate_num) ||
1466 (enc->enc_pic.rc_layer_init[0].frame_rate_den != pic->rc[0].frame_rate_den);
1467
1468 enc->need_rc_per_pic =
1469 (enc->enc_pic.rc_per_pic.qp_i != pic->rc[0].quant_i_frames) ||
1470 (enc->enc_pic.rc_per_pic.qp_p != pic->rc[0].quant_p_frames) ||
1471 (enc->enc_pic.rc_per_pic.max_au_size_i != pic->rc[0].max_au_size) ||
1472 (enc->enc_pic.rc_per_pic.qvbr_quality_level != pic->rc[0].vbr_quality_factor);
1473 } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_AV1) {
1474 struct pipe_av1_enc_picture_desc *pic = (struct pipe_av1_enc_picture_desc *)picture;
1475 dpb_slots = pic->dpb_size;
1476 enc->need_rate_control =
1477 (enc->enc_pic.rc_layer_init[0].target_bit_rate != pic->rc[0].target_bitrate) ||
1478 (enc->enc_pic.rc_layer_init[0].frame_rate_num != pic->rc[0].frame_rate_num) ||
1479 (enc->enc_pic.rc_layer_init[0].frame_rate_den != pic->rc[0].frame_rate_den);
1480
1481 enc->need_rc_per_pic =
1482 (enc->enc_pic.rc_per_pic.qp_i != pic->rc[0].qp) ||
1483 (enc->enc_pic.rc_per_pic.qp_p != pic->rc[0].qp_inter) ||
1484 (enc->enc_pic.rc_per_pic.qp_b != pic->rc[0].qp_inter) ||
1485 (enc->enc_pic.rc_per_pic.max_au_size_i != pic->rc[0].max_au_size) ||
1486 (enc->enc_pic.rc_per_pic.qvbr_quality_level != pic->rc[0].vbr_quality_factor);
1487
1488 if (!enc->cdf) {
1489 enc->cdf = CALLOC_STRUCT(rvid_buffer);
1490 if (setup_cdf(enc)) {
1491 RADEON_ENC_ERR("Can't create cdf buffer.\n");
1492 goto error;
1493 }
1494 }
1495 }
1496
1497 if (enc->dpb_type == DPB_TIER_2)
1498 dpb_slots = 0;
1499
1500 radeon_vcn_enc_get_param(enc, picture);
1501 if (!enc->dpb) {
1502 enc->dpb = CALLOC_STRUCT(rvid_buffer);
1503 if (setup_dpb(enc, dpb_slots)) {
1504 if (!enc->dpb ||
1505 !si_vid_create_buffer(enc->screen, enc->dpb, enc->dpb_size, PIPE_USAGE_DEFAULT)) {
1506 RADEON_ENC_ERR("Can't create DPB buffer.\n");
1507 goto error;
1508 }
1509 }
1510 }
1511
1512 if ((sscreen->info.vcn_ip_version >= VCN_5_0_0) && enc->metadata_size && !enc->meta) {
1513 enc->meta = CALLOC_STRUCT(rvid_buffer);
1514 if (!enc->meta ||
1515 !si_vid_create_buffer(enc->screen, enc->meta, enc->metadata_size, PIPE_USAGE_DEFAULT)) {
1516 RADEON_ENC_ERR("Can't create meta buffer.\n");
1517 goto error;
1518 }
1519 }
1520
1521 if (dpb_slots > enc->dpb_slots) {
1522 setup_dpb(enc, dpb_slots);
1523 if (!si_vid_resize_buffer(enc->base.context, &enc->cs, enc->dpb, enc->dpb_size, NULL)) {
1524 RADEON_ENC_ERR("Can't resize DPB buffer.\n");
1525 goto error;
1526 }
1527 if (sscreen->info.vcn_ip_version >= VCN_5_0_0 && enc->metadata_size &&
1528 !si_vid_resize_buffer(enc->base.context, &enc->cs, enc->meta, enc->metadata_size, NULL)) {
1529 RADEON_ENC_ERR("Can't resize meta buffer.\n");
1530 goto error;
1531 }
1532 }
1533
1534 /* qp map buffer could be created here, and release at the end */
1535 if (enc->enc_pic.enc_qp_map.qp_map_type != RENCODE_QP_MAP_TYPE_NONE) {
1536 if (!enc->roi) {
1537 enc->roi = CALLOC_STRUCT(rvid_buffer);
1538 enc->roi_size = roi_buffer_size(enc);
1539 if (!enc->roi || !enc->roi_size ||
1540 !si_vid_create_buffer(enc->screen, enc->roi, enc->roi_size, PIPE_USAGE_DYNAMIC)) {
1541 RADEON_ENC_ERR("Can't create ROI buffer.\n");
1542 goto error;
1543 }
1544 }
1545 if(generate_roi_map(enc)) {
1546 RADEON_ENC_ERR("Can't form roi map.\n");
1547 goto error;
1548 }
1549 }
1550
1551 if (source->buffer_format == PIPE_FORMAT_NV12 ||
1552 source->buffer_format == PIPE_FORMAT_P010 ||
1553 source->buffer_format == PIPE_FORMAT_P016) {
1554 enc->get_buffer(vid_buf->resources[0], &enc->handle, &enc->luma);
1555 enc->get_buffer(vid_buf->resources[1], NULL, &enc->chroma);
1556 }
1557 else {
1558 enc->get_buffer(vid_buf->resources[0], &enc->handle, &enc->luma);
1559 enc->chroma = NULL;
1560 }
1561
1562 enc->need_feedback = false;
1563
1564 if (!enc->stream_handle) {
1565 struct rvid_buffer fb;
1566 enc->stream_handle = si_vid_alloc_stream_handle();
1567 enc->si = CALLOC_STRUCT(rvid_buffer);
1568 if (!enc->si ||
1569 !enc->stream_handle ||
1570 !si_vid_create_buffer(enc->screen, enc->si, 128 * 1024, PIPE_USAGE_DEFAULT)) {
1571 RADEON_ENC_ERR("Can't create session buffer.\n");
1572 goto error;
1573 }
1574 si_vid_create_buffer(enc->screen, &fb, 4096, PIPE_USAGE_STAGING);
1575 enc->fb = &fb;
1576 enc->begin(enc);
1577 flush(enc, PIPE_FLUSH_ASYNC, NULL);
1578 si_vid_destroy_buffer(&fb);
1579 enc->need_rate_control = false;
1580 enc->need_rc_per_pic = false;
1581 }
1582
1583 return;
1584
1585 error:
1586 RADEON_ENC_DESTROY_VIDEO_BUFFER(enc->dpb);
1587 RADEON_ENC_DESTROY_VIDEO_BUFFER(enc->si);
1588 RADEON_ENC_DESTROY_VIDEO_BUFFER(enc->cdf);
1589 RADEON_ENC_DESTROY_VIDEO_BUFFER(enc->roi);
1590 RADEON_ENC_DESTROY_VIDEO_BUFFER(enc->meta);
1591 }
1592
radeon_vcn_enc_encode_h264_header(struct radeon_encoder * enc,struct pipe_enc_raw_header * header,uint8_t * out)1593 static uint32_t radeon_vcn_enc_encode_h264_header(struct radeon_encoder *enc,
1594 struct pipe_enc_raw_header *header,
1595 uint8_t *out)
1596 {
1597 /* Startcode may be 3 or 4 bytes. */
1598 const uint8_t nal_byte = header->buffer[header->buffer[2] == 0x1 ? 3 : 4];
1599
1600 switch (header->type) {
1601 case PIPE_H264_NAL_SPS:
1602 return radeon_enc_write_sps(enc, nal_byte, out);
1603 case PIPE_H264_NAL_PPS:
1604 return radeon_enc_write_pps(enc, nal_byte, out);
1605 default:
1606 assert(header->buffer);
1607 memcpy(out, header->buffer, header->size);
1608 return header->size;
1609 }
1610 }
1611
radeon_vcn_enc_encode_hevc_header(struct radeon_encoder * enc,struct pipe_enc_raw_header * header,uint8_t * out)1612 static uint32_t radeon_vcn_enc_encode_hevc_header(struct radeon_encoder *enc,
1613 struct pipe_enc_raw_header *header,
1614 uint8_t *out)
1615 {
1616 switch (header->type) {
1617 case PIPE_H265_NAL_VPS:
1618 return radeon_enc_write_vps(enc, out);
1619 case PIPE_H265_NAL_SPS:
1620 return radeon_enc_write_sps_hevc(enc, out);
1621 case PIPE_H265_NAL_PPS:
1622 return radeon_enc_write_pps_hevc(enc, out);
1623 default:
1624 assert(header->buffer);
1625 memcpy(out, header->buffer, header->size);
1626 return header->size;
1627 }
1628 }
1629
radeon_vcn_enc_encode_av1_header(struct radeon_encoder * enc,struct pipe_enc_raw_header * header,uint8_t * out)1630 static uint32_t radeon_vcn_enc_encode_av1_header(struct radeon_encoder *enc,
1631 struct pipe_enc_raw_header *header,
1632 uint8_t *out)
1633 {
1634 switch (header->type) {
1635 case 1: /* SEQUENCE_HEADER */
1636 return radeon_enc_write_sequence_header(enc, header->buffer, out);
1637 default:
1638 assert(header->buffer);
1639 memcpy(out, header->buffer, header->size);
1640 return header->size;
1641 }
1642 }
1643
radeon_vcn_enc_encode_headers(struct radeon_encoder * enc)1644 static void *radeon_vcn_enc_encode_headers(struct radeon_encoder *enc)
1645 {
1646 const bool is_h264 = u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC;
1647 const bool is_hevc = u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC;
1648 const bool is_av1 = u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_AV1;
1649 struct util_dynarray *headers;
1650 unsigned num_slices = 0, num_headers = 0;
1651
1652 if (is_h264)
1653 headers = &enc->enc_pic.h264.desc->raw_headers;
1654 else if (is_hevc)
1655 headers = &enc->enc_pic.hevc.desc->raw_headers;
1656 else if (is_av1)
1657 headers = &enc->enc_pic.av1.desc->raw_headers;
1658 else
1659 return NULL;
1660
1661 util_dynarray_foreach(headers, struct pipe_enc_raw_header, header) {
1662 if (header->is_slice)
1663 num_slices++;
1664 num_headers++;
1665 }
1666
1667 if (!num_headers || !num_slices || num_headers == num_slices)
1668 return NULL;
1669
1670 size_t segments_size =
1671 sizeof(struct rvcn_enc_output_unit_segment) * (num_headers - num_slices + 1);
1672 struct rvcn_enc_feedback_data *data =
1673 CALLOC_VARIANT_LENGTH_STRUCT(rvcn_enc_feedback_data, segments_size);
1674 if (!data)
1675 return NULL;
1676
1677 uint8_t *ptr = enc->ws->buffer_map(enc->ws, enc->bs_handle, &enc->cs,
1678 PIPE_MAP_WRITE | RADEON_MAP_TEMPORARY);
1679 if (!ptr) {
1680 RADEON_ENC_ERR("Can't map bs buffer.\n");
1681 FREE(data);
1682 return NULL;
1683 }
1684
1685 unsigned offset = 0;
1686 struct rvcn_enc_output_unit_segment *slice_segment = NULL;
1687
1688 util_dynarray_foreach(headers, struct pipe_enc_raw_header, header) {
1689 if (header->is_slice) {
1690 if (slice_segment)
1691 continue;
1692 slice_segment = &data->segments[data->num_segments];
1693 slice_segment->is_slice = true;
1694 } else {
1695 unsigned size = 0;
1696 if (is_h264)
1697 size = radeon_vcn_enc_encode_h264_header(enc, header, ptr + offset);
1698 else if (is_hevc)
1699 size = radeon_vcn_enc_encode_hevc_header(enc, header, ptr + offset);
1700 else if (is_av1)
1701 size = radeon_vcn_enc_encode_av1_header(enc, header, ptr + offset);
1702 data->segments[data->num_segments].size = size;
1703 data->segments[data->num_segments].offset = offset;
1704 offset += size;
1705 }
1706 data->num_segments++;
1707 }
1708
1709 enc->bs_offset = align(offset, 16);
1710 assert(enc->bs_offset < enc->bs_size);
1711
1712 assert(slice_segment);
1713 slice_segment->offset = enc->bs_offset;
1714
1715 enc->ws->buffer_unmap(enc->ws, enc->bs_handle);
1716
1717 return data;
1718 }
1719
radeon_enc_encode_bitstream(struct pipe_video_codec * encoder,struct pipe_video_buffer * source,struct pipe_resource * destination,void ** fb)1720 static void radeon_enc_encode_bitstream(struct pipe_video_codec *encoder,
1721 struct pipe_video_buffer *source,
1722 struct pipe_resource *destination, void **fb)
1723 {
1724 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
1725 struct vl_video_buffer *vid_buf = (struct vl_video_buffer *)source;
1726
1727 if (enc->error)
1728 return;
1729
1730 enc->get_buffer(destination, &enc->bs_handle, NULL);
1731 enc->bs_size = destination->width0;
1732 enc->bs_offset = 0;
1733
1734 *fb = enc->fb = CALLOC_STRUCT(rvid_buffer);
1735
1736 if (!si_vid_create_buffer(enc->screen, enc->fb, 4096, PIPE_USAGE_STAGING)) {
1737 RADEON_ENC_ERR("Can't create feedback buffer.\n");
1738 return;
1739 }
1740
1741 enc->fb->user_data = radeon_vcn_enc_encode_headers(enc);
1742
1743 if (vid_buf->base.statistics_data) {
1744 enc->get_buffer(vid_buf->base.statistics_data, &enc->stats, NULL);
1745 if (enc->stats->size < sizeof(rvcn_encode_stats_type_0_t)) {
1746 RADEON_ENC_ERR("Encoder statistics output buffer is too small.\n");
1747 enc->stats = NULL;
1748 }
1749 vid_buf->base.statistics_data = NULL;
1750 }
1751 else
1752 enc->stats = NULL;
1753
1754 enc->need_feedback = true;
1755 enc->encode(enc);
1756 }
1757
radeon_enc_end_frame(struct pipe_video_codec * encoder,struct pipe_video_buffer * source,struct pipe_picture_desc * picture)1758 static int radeon_enc_end_frame(struct pipe_video_codec *encoder, struct pipe_video_buffer *source,
1759 struct pipe_picture_desc *picture)
1760 {
1761 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
1762
1763 if (enc->error)
1764 return -1;
1765
1766 return flush(enc, picture->flush_flags, picture->fence);
1767 }
1768
radeon_enc_destroy(struct pipe_video_codec * encoder)1769 static void radeon_enc_destroy(struct pipe_video_codec *encoder)
1770 {
1771 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
1772
1773 if (enc->stream_handle) {
1774 struct rvid_buffer fb;
1775 enc->need_feedback = false;
1776 si_vid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
1777 enc->fb = &fb;
1778 enc->destroy(enc);
1779 flush(enc, PIPE_FLUSH_ASYNC, NULL);
1780 RADEON_ENC_DESTROY_VIDEO_BUFFER(enc->si);
1781 si_vid_destroy_buffer(&fb);
1782 }
1783
1784 RADEON_ENC_DESTROY_VIDEO_BUFFER(enc->dpb);
1785 RADEON_ENC_DESTROY_VIDEO_BUFFER(enc->cdf);
1786 RADEON_ENC_DESTROY_VIDEO_BUFFER(enc->roi);
1787 RADEON_ENC_DESTROY_VIDEO_BUFFER(enc->meta);
1788 enc->ws->cs_destroy(&enc->cs);
1789 if (enc->ectx)
1790 enc->ectx->destroy(enc->ectx);
1791
1792 FREE(enc);
1793 }
1794
radeon_enc_get_feedback(struct pipe_video_codec * encoder,void * feedback,unsigned * size,struct pipe_enc_feedback_metadata * metadata)1795 static void radeon_enc_get_feedback(struct pipe_video_codec *encoder, void *feedback,
1796 unsigned *size, struct pipe_enc_feedback_metadata *metadata)
1797 {
1798 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
1799 struct rvid_buffer *fb = feedback;
1800
1801 uint32_t *ptr = enc->ws->buffer_map(enc->ws, fb->res->buf, &enc->cs,
1802 PIPE_MAP_READ_WRITE | RADEON_MAP_TEMPORARY);
1803 if (ptr[1])
1804 *size = ptr[6] - ptr[8];
1805 else
1806 *size = 0;
1807 enc->ws->buffer_unmap(enc->ws, fb->res->buf);
1808
1809 metadata->present_metadata = PIPE_VIDEO_FEEDBACK_METADATA_TYPE_CODEC_UNIT_LOCATION;
1810
1811 if (fb->user_data) {
1812 struct rvcn_enc_feedback_data *data = fb->user_data;
1813 metadata->codec_unit_metadata_count = data->num_segments;
1814 for (unsigned i = 0; i < data->num_segments; i++) {
1815 metadata->codec_unit_metadata[i].offset = data->segments[i].offset;
1816 if (data->segments[i].is_slice) {
1817 metadata->codec_unit_metadata[i].size = *size;
1818 metadata->codec_unit_metadata[i].flags = 0;
1819 } else {
1820 metadata->codec_unit_metadata[i].size = data->segments[i].size;
1821 metadata->codec_unit_metadata[i].flags = PIPE_VIDEO_CODEC_UNIT_LOCATION_FLAG_SINGLE_NALU;
1822 }
1823 }
1824 FREE(fb->user_data);
1825 fb->user_data = NULL;
1826 } else {
1827 metadata->codec_unit_metadata_count = 1;
1828 metadata->codec_unit_metadata[0].offset = 0;
1829 metadata->codec_unit_metadata[0].size = *size;
1830 metadata->codec_unit_metadata[0].flags = 0;
1831 }
1832
1833 RADEON_ENC_DESTROY_VIDEO_BUFFER(fb);
1834 }
1835
radeon_enc_fence_wait(struct pipe_video_codec * encoder,struct pipe_fence_handle * fence,uint64_t timeout)1836 static int radeon_enc_fence_wait(struct pipe_video_codec *encoder,
1837 struct pipe_fence_handle *fence,
1838 uint64_t timeout)
1839 {
1840 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
1841
1842 return enc->ws->fence_wait(enc->ws, fence, timeout);
1843 }
1844
radeon_enc_destroy_fence(struct pipe_video_codec * encoder,struct pipe_fence_handle * fence)1845 static void radeon_enc_destroy_fence(struct pipe_video_codec *encoder,
1846 struct pipe_fence_handle *fence)
1847 {
1848 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
1849
1850 enc->ws->fence_reference(enc->ws, &fence, NULL);
1851 }
1852
radeon_enc_frame_context_buffer_size(struct radeon_encoder * enc)1853 static unsigned int radeon_enc_frame_context_buffer_size(struct radeon_encoder *enc)
1854 {
1855 unsigned int size = 0;
1856 bool is_h264 = u_reduce_video_profile(enc->base.profile)
1857 == PIPE_VIDEO_FORMAT_MPEG4_AVC;
1858 bool is_av1 = u_reduce_video_profile(enc->base.profile)
1859 == PIPE_VIDEO_FORMAT_AV1;
1860 bool has_b = enc->enc_pic.spec_misc.b_picture_enabled; /* for h264 only */
1861
1862 size = RENCODE_MAX_METADATA_BUFFER_SIZE_PER_FRAME;
1863 if (is_h264) {
1864 if (has_b) {
1865 enc->enc_pic.fcb_offset.h264.colloc_buffer_offset = size;
1866 size += enc->enc_pic.total_coloc_bytes;
1867 } else
1868 enc->enc_pic.fcb_offset.h264.colloc_buffer_offset =
1869 RENCODE_INVALID_COLOC_OFFSET;
1870 }
1871
1872 if (is_av1) {
1873 enc->enc_pic.fcb_offset.av1.av1_cdf_frame_context_offset = size;
1874 size += RENCODE_AV1_FRAME_CONTEXT_CDF_TABLE_SIZE;
1875 enc->enc_pic.fcb_offset.av1.av1_cdef_algorithm_context_offset = size;
1876 size += RENCODE_AV1_CDEF_ALGORITHM_FRAME_CONTEXT_SIZE;
1877 }
1878
1879 size = align(size, enc->alignment);
1880 return size;
1881 }
1882
radeon_enc_create_dpb_aux_buffers(struct radeon_encoder * enc,struct radeon_enc_dpb_buffer * buf)1883 void radeon_enc_create_dpb_aux_buffers(struct radeon_encoder *enc, struct radeon_enc_dpb_buffer *buf)
1884 {
1885 if (buf->fcb)
1886 return;
1887
1888 uint32_t fcb_size = radeon_enc_frame_context_buffer_size(enc);
1889
1890 buf->fcb = CALLOC_STRUCT(rvid_buffer);
1891 if (!buf->fcb || !si_vid_create_buffer(enc->screen, buf->fcb, fcb_size, PIPE_USAGE_DEFAULT)) {
1892 RADEON_ENC_ERR("Can't create fcb buffer!\n");
1893 return;
1894 }
1895
1896 if (enc->enc_pic.quality_modes.pre_encode_mode) {
1897 buf->pre = enc->base.context->create_video_buffer(enc->base.context, &buf->templ);
1898 if (!buf->pre) {
1899 RADEON_ENC_ERR("Can't create preenc buffer!\n");
1900 return;
1901 }
1902 buf->pre_luma = (struct si_texture *)((struct vl_video_buffer *)buf->pre)->resources[0];
1903 buf->pre_chroma = (struct si_texture *)((struct vl_video_buffer *)buf->pre)->resources[1];
1904
1905 buf->pre_fcb = CALLOC_STRUCT(rvid_buffer);
1906 if (!buf->pre_fcb || !si_vid_create_buffer(enc->screen, buf->pre_fcb, fcb_size, PIPE_USAGE_DEFAULT)) {
1907 RADEON_ENC_ERR("Can't create preenc fcb buffer!\n");
1908 return;
1909 }
1910 }
1911 }
1912
radeon_enc_destroy_dpb_buffer(void * data)1913 static void radeon_enc_destroy_dpb_buffer(void *data)
1914 {
1915 struct radeon_enc_dpb_buffer *dpb = data;
1916
1917 if (dpb->pre)
1918 dpb->pre->destroy(dpb->pre);
1919
1920 RADEON_ENC_DESTROY_VIDEO_BUFFER(dpb->fcb);
1921 RADEON_ENC_DESTROY_VIDEO_BUFFER(dpb->pre_fcb);
1922 FREE(dpb);
1923 }
1924
radeon_enc_create_dpb_buffer(struct pipe_video_codec * encoder,struct pipe_picture_desc * picture,const struct pipe_video_buffer * templat)1925 static struct pipe_video_buffer *radeon_enc_create_dpb_buffer(struct pipe_video_codec *encoder,
1926 struct pipe_picture_desc *picture,
1927 const struct pipe_video_buffer *templat)
1928 {
1929 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
1930
1931 struct pipe_video_buffer templ = *templat;
1932 templ.bind |= PIPE_BIND_VIDEO_ENCODE_DPB;
1933 struct pipe_video_buffer *buf = enc->base.context->create_video_buffer(enc->base.context, &templ);
1934 if (!buf) {
1935 RADEON_ENC_ERR("Can't create dpb buffer!\n");
1936 return NULL;
1937 }
1938
1939 struct radeon_enc_dpb_buffer *dpb = CALLOC_STRUCT(radeon_enc_dpb_buffer);
1940 dpb->templ = templ;
1941 dpb->luma = (struct si_texture *)((struct vl_video_buffer *)buf)->resources[0];
1942 dpb->chroma = (struct si_texture *)((struct vl_video_buffer *)buf)->resources[1];
1943
1944 vl_video_buffer_set_associated_data(buf, &enc->base, dpb, &radeon_enc_destroy_dpb_buffer);
1945
1946 return buf;
1947 }
1948
radeon_create_encoder(struct pipe_context * context,const struct pipe_video_codec * templ,struct radeon_winsys * ws,radeon_enc_get_buffer get_buffer)1949 struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
1950 const struct pipe_video_codec *templ,
1951 struct radeon_winsys *ws,
1952 radeon_enc_get_buffer get_buffer)
1953 {
1954 struct si_screen *sscreen = (struct si_screen *)context->screen;
1955 struct si_context *sctx = (struct si_context *)context;
1956 struct radeon_encoder *enc;
1957
1958 enc = CALLOC_STRUCT(radeon_encoder);
1959
1960 if (!enc)
1961 return NULL;
1962
1963 if (sctx->vcn_has_ctx) {
1964 enc->ectx = context->screen->context_create(context->screen, NULL, PIPE_CONTEXT_COMPUTE_ONLY);
1965 if (!enc->ectx)
1966 sctx->vcn_has_ctx = false;
1967 }
1968
1969 enc->alignment = 256;
1970 enc->base = *templ;
1971 enc->base.context = (sctx->vcn_has_ctx)? enc->ectx : context;
1972 enc->base.destroy = radeon_enc_destroy;
1973 enc->base.begin_frame = radeon_enc_begin_frame;
1974 enc->base.encode_bitstream = radeon_enc_encode_bitstream;
1975 enc->base.end_frame = radeon_enc_end_frame;
1976 enc->base.flush = radeon_enc_flush;
1977 enc->base.get_feedback = radeon_enc_get_feedback;
1978 enc->base.fence_wait = radeon_enc_fence_wait;
1979 enc->base.destroy_fence = radeon_enc_destroy_fence;
1980 enc->get_buffer = get_buffer;
1981 enc->screen = context->screen;
1982 enc->ws = ws;
1983
1984 if (!ws->cs_create(&enc->cs,
1985 (sctx->vcn_has_ctx) ? ((struct si_context *)enc->ectx)->ctx : sctx->ctx,
1986 AMD_IP_VCN_ENC, radeon_enc_cs_flush, enc)) {
1987 RADEON_ENC_ERR("Can't get command submission context.\n");
1988 goto error;
1989 }
1990
1991 enc->enc_pic.use_rc_per_pic_ex = false;
1992
1993 ac_vcn_enc_init_cmds(&enc->cmd, sscreen->info.vcn_ip_version);
1994
1995 if (sscreen->info.vcn_ip_version >= VCN_5_0_0)
1996 enc->dpb_type = DPB_TIER_2;
1997
1998 if (enc->dpb_type == DPB_TIER_2)
1999 enc->base.create_dpb_buffer = radeon_enc_create_dpb_buffer;
2000
2001 if (sscreen->info.vcn_ip_version >= VCN_5_0_0) {
2002 radeon_enc_5_0_init(enc);
2003 if (sscreen->info.vcn_ip_version == VCN_5_0_0) {
2004 /* this limits tile splitting scheme to use legacy method */
2005 enc->enc_pic.av1_tile_splitting_legacy_flag = true;
2006 }
2007 }
2008 else if (sscreen->info.vcn_ip_version >= VCN_4_0_0) {
2009 if (sscreen->info.vcn_enc_minor_version >= 1)
2010 enc->enc_pic.use_rc_per_pic_ex = true;
2011 radeon_enc_4_0_init(enc);
2012 }
2013 else if (sscreen->info.vcn_ip_version >= VCN_3_0_0) {
2014 if (sscreen->info.vcn_enc_minor_version >= 29)
2015 enc->enc_pic.use_rc_per_pic_ex = true;
2016 radeon_enc_3_0_init(enc);
2017 }
2018 else if (sscreen->info.vcn_ip_version >= VCN_2_0_0) {
2019 if (sscreen->info.vcn_enc_minor_version >= 18)
2020 enc->enc_pic.use_rc_per_pic_ex = true;
2021 radeon_enc_2_0_init(enc);
2022 }
2023 else {
2024 if (sscreen->info.vcn_enc_minor_version >= 15)
2025 enc->enc_pic.use_rc_per_pic_ex = true;
2026 radeon_enc_1_2_init(enc);
2027 }
2028
2029 return &enc->base;
2030
2031 error:
2032 enc->ws->cs_destroy(&enc->cs);
2033 FREE(enc);
2034 return NULL;
2035 }
2036
radeon_enc_add_buffer(struct radeon_encoder * enc,struct pb_buffer_lean * buf,unsigned usage,enum radeon_bo_domain domain,signed offset)2037 void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer_lean *buf,
2038 unsigned usage, enum radeon_bo_domain domain, signed offset)
2039 {
2040 enc->ws->cs_add_buffer(&enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
2041 uint64_t addr;
2042 addr = enc->ws->buffer_get_virtual_address(buf);
2043 addr = addr + offset;
2044 RADEON_ENC_CS(addr >> 32);
2045 RADEON_ENC_CS(addr);
2046 }
2047
radeon_enc_code_leb128(uint8_t * buf,uint32_t value,uint32_t num_bytes)2048 void radeon_enc_code_leb128(uint8_t *buf, uint32_t value,
2049 uint32_t num_bytes)
2050 {
2051 uint8_t leb128_byte = 0;
2052 uint32_t i = 0;
2053
2054 do {
2055 leb128_byte = (value & 0x7f);
2056 value >>= 7;
2057 if (num_bytes > 1)
2058 leb128_byte |= 0x80;
2059
2060 *(buf + i) = leb128_byte;
2061 num_bytes--;
2062 i++;
2063 } while((leb128_byte & 0x80));
2064 }
2065
radeon_enc_av1_tile_log2(unsigned int blk_size,unsigned int max)2066 unsigned int radeon_enc_av1_tile_log2(unsigned int blk_size, unsigned int max)
2067 {
2068 unsigned int k;
2069
2070 assert(blk_size);
2071 for (k = 0; (blk_size << k) < max; k++) {}
2072
2073 return k;
2074 }
2075
2076 /* dummy function for re-using the same pipeline */
radeon_enc_dummy(struct radeon_encoder * enc)2077 void radeon_enc_dummy(struct radeon_encoder *enc) {}
2078
2079 /* this function has to be in pair with AV1 header copy instruction type at the end */
radeon_enc_av1_bs_copy_end(struct radeon_encoder * enc,uint32_t bits)2080 static void radeon_enc_av1_bs_copy_end(struct radeon_encoder *enc, uint32_t bits)
2081 {
2082 assert(bits > 0);
2083 /* it must be dword aligned at the end */
2084 *enc->enc_pic.copy_start = DIV_ROUND_UP(bits, 32) * 4 + 12;
2085 *(enc->enc_pic.copy_start + 2) = bits;
2086 }
2087
2088 /* av1 bitstream instruction type */
radeon_enc_av1_bs_instruction_type(struct radeon_encoder * enc,struct radeon_bitstream * bs,uint32_t inst,uint32_t obu_type)2089 void radeon_enc_av1_bs_instruction_type(struct radeon_encoder *enc,
2090 struct radeon_bitstream *bs,
2091 uint32_t inst,
2092 uint32_t obu_type)
2093 {
2094 radeon_bs_flush_headers(bs);
2095
2096 if (bs->bits_output)
2097 radeon_enc_av1_bs_copy_end(enc, bs->bits_output);
2098
2099 enc->enc_pic.copy_start = &enc->cs.current.buf[enc->cs.current.cdw++];
2100 RADEON_ENC_CS(inst);
2101
2102 if (inst != RENCODE_HEADER_INSTRUCTION_COPY) {
2103 *enc->enc_pic.copy_start = 8;
2104 if (inst == RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_START) {
2105 *enc->enc_pic.copy_start += 4;
2106 RADEON_ENC_CS(obu_type);
2107 }
2108 } else
2109 RADEON_ENC_CS(0); /* allocate a dword for number of bits */
2110
2111 radeon_bs_reset(bs, NULL, &enc->cs);
2112 }
2113
radeon_enc_value_bits(uint32_t value)2114 uint32_t radeon_enc_value_bits(uint32_t value)
2115 {
2116 uint32_t i = 1;
2117
2118 while (value > 1) {
2119 i++;
2120 value >>= 1;
2121 }
2122
2123 return i;
2124 }
2125