1 /************************************************************************** 2 * 3 * Copyright 2017 Advanced Micro Devices, Inc. 4 * 5 * SPDX-License-Identifier: MIT 6 * 7 **************************************************************************/ 8 9 #ifndef _RADEON_VCN_ENC_H 10 #define _RADEON_VCN_ENC_H 11 12 #include "radeon_vcn.h" 13 #include "util/macros.h" 14 #include "radeon_bitstream.h" 15 16 #include "ac_vcn_enc.h" 17 18 #define PIPE_ALIGN_IN_BLOCK_SIZE(value, alignment) DIV_ROUND_UP(value, alignment) 19 20 #define RADEON_ENC_CS(value) (enc->cs.current.buf[enc->cs.current.cdw++] = (value)) 21 #define RADEON_ENC_BEGIN(cmd) \ 22 { \ 23 uint32_t *begin = &enc->cs.current.buf[enc->cs.current.cdw++]; \ 24 RADEON_ENC_CS(cmd) 25 #define RADEON_ENC_READ(buf, domain, off) \ 26 radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off)) 27 #define RADEON_ENC_WRITE(buf, domain, off) \ 28 radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off)) 29 #define RADEON_ENC_READWRITE(buf, domain, off) \ 30 radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off)) 31 #define RADEON_ENC_END() \ 32 *begin = (&enc->cs.current.buf[enc->cs.current.cdw] - begin) * 4; \ 33 enc->total_task_size += *begin; \ 34 } 35 #define RADEON_ENC_ADDR_SWAP() \ 36 do { \ 37 unsigned int *low = &enc->cs.current.buf[enc->cs.current.cdw - 2]; \ 38 unsigned int *high = &enc->cs.current.buf[enc->cs.current.cdw - 1]; \ 39 unsigned int temp = *low; \ 40 *low = *high; \ 41 *high = temp; \ 42 } while(0) 43 44 #define RADEON_ENC_DESTROY_VIDEO_BUFFER(buf) \ 45 do { \ 46 if (buf) { \ 47 si_vid_destroy_buffer(buf); \ 48 FREE(buf); \ 49 (buf) = NULL; \ 50 } \ 51 } while(0) 52 53 #define RADEON_ENC_ERR(fmt, args...) \ 54 do { \ 55 enc->error = true; \ 56 fprintf(stderr, "EE %s:%d %s VCN - " fmt, __FILE__, __LINE__, __func__, ##args); \ 57 } while(0) 58 59 typedef void (*radeon_enc_get_buffer)(struct pipe_resource *resource, struct pb_buffer_lean **handle, 60 struct radeon_surf **surface); 61 62 struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context, 63 const struct pipe_video_codec *templat, 64 struct radeon_winsys *ws, 65 radeon_enc_get_buffer get_buffer); 66 67 struct radeon_enc_dpb_buffer { 68 struct pipe_video_buffer templ, *pre; 69 70 struct si_texture *luma; /* recon luma */ 71 struct si_texture *chroma; /* recon chroma */ 72 struct rvid_buffer *fcb; /* frame context buffer*/ 73 struct si_texture *pre_luma; /* preenc recon luma */ 74 struct si_texture *pre_chroma;/* preenc recon chroma */ 75 struct rvid_buffer *pre_fcb; /* preenc frame context buffer */ 76 }; 77 78 struct radeon_enc_pic { 79 union { 80 enum pipe_h2645_enc_picture_type picture_type; 81 enum pipe_av1_enc_frame_type frame_type; 82 }; 83 84 union { 85 struct { 86 struct pipe_h264_enc_picture_desc *desc; 87 } h264; 88 struct { 89 struct pipe_h265_enc_picture_desc *desc; 90 } hevc; 91 struct { 92 struct pipe_av1_enc_picture_desc *desc; 93 uint32_t coded_width; 94 uint32_t coded_height; 95 bool compound; 96 bool skip_mode_allowed; 97 } av1; 98 }; 99 100 unsigned pic_width_in_luma_samples; 101 unsigned pic_height_in_luma_samples; 102 unsigned bit_depth_luma_minus8; 103 unsigned bit_depth_chroma_minus8; 104 unsigned nal_unit_type; 105 unsigned temporal_id; 106 unsigned num_temporal_layers; 107 unsigned total_coloc_bytes; 108 rvcn_enc_quality_modes_t quality_modes; 109 110 bool not_referenced; 111 bool use_rc_per_pic_ex; 112 bool av1_tile_splitting_legacy_flag; 113 114 struct { 115 union { 116 struct 117 { 118 uint32_t av1_cdf_frame_context_offset; 119 uint32_t av1_cdef_algorithm_context_offset; 120 } av1; 121 struct 122 { 123 uint32_t colloc_buffer_offset; 124 } h264; 125 }; 126 } fcb_offset; 127 128 struct radeon_enc_dpb_buffer *dpb_bufs[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES]; 129 130 struct { 131 struct { 132 struct { 133 uint32_t enable_error_resilient_mode:1; 134 uint32_t force_integer_mv:1; 135 uint32_t disable_screen_content_tools:1; 136 uint32_t is_obu_frame:1; 137 }; 138 uint32_t *copy_start; 139 }; 140 rvcn_enc_av1_spec_misc_t av1_spec_misc; 141 rvcn_enc_av1_cdf_default_table_t av1_cdf_default_table; 142 }; 143 144 rvcn_enc_session_info_t session_info; 145 rvcn_enc_task_info_t task_info; 146 rvcn_enc_session_init_t session_init; 147 rvcn_enc_layer_control_t layer_ctrl; 148 rvcn_enc_layer_select_t layer_sel; 149 rvcn_enc_h264_slice_control_t slice_ctrl; 150 rvcn_enc_hevc_slice_control_t hevc_slice_ctrl; 151 rvcn_enc_h264_spec_misc_t spec_misc; 152 rvcn_enc_hevc_spec_misc_t hevc_spec_misc; 153 rvcn_enc_rate_ctl_session_init_t rc_session_init; 154 rvcn_enc_rate_ctl_layer_init_t rc_layer_init[RENCODE_MAX_NUM_TEMPORAL_LAYERS]; 155 rvcn_enc_h264_encode_params_t h264_enc_params; 156 rvcn_enc_h264_deblocking_filter_t h264_deblock; 157 rvcn_enc_hevc_deblocking_filter_t hevc_deblock; 158 rvcn_enc_hevc_encode_params_t hevc_enc_params; 159 rvcn_enc_av1_encode_params_t av1_enc_params; 160 rvcn_enc_av1_tile_config_t av1_tile_config; 161 rvcn_enc_rate_ctl_per_picture_t rc_per_pic; 162 rvcn_enc_quality_params_t quality_params; 163 rvcn_enc_encode_context_buffer_t ctx_buf; 164 rvcn_enc_video_bitstream_buffer_t bit_buf; 165 rvcn_enc_feedback_buffer_t fb_buf; 166 rvcn_enc_intra_refresh_t intra_refresh; 167 rvcn_enc_encode_params_t enc_params; 168 rvcn_enc_stats_t enc_statistics; 169 rvcn_enc_input_format_t enc_input_format; 170 rvcn_enc_output_format_t enc_output_format; 171 rvcn_enc_qp_map_t enc_qp_map; 172 rvcn_enc_metadata_buffer_t metadata; 173 rvcn_enc_latency_t enc_latency; 174 }; 175 176 struct radeon_encoder { 177 struct pipe_video_codec base; 178 179 void (*begin)(struct radeon_encoder *enc); 180 void (*before_encode)(struct radeon_encoder *enc); 181 void (*encode)(struct radeon_encoder *enc); 182 void (*destroy)(struct radeon_encoder *enc); 183 void (*session_info)(struct radeon_encoder *enc); 184 void (*task_info)(struct radeon_encoder *enc, bool need_feedback); 185 void (*session_init)(struct radeon_encoder *enc); 186 void (*layer_control)(struct radeon_encoder *enc); 187 void (*layer_select)(struct radeon_encoder *enc); 188 void (*slice_control)(struct radeon_encoder *enc); 189 void (*spec_misc)(struct radeon_encoder *enc); 190 void (*rc_session_init)(struct radeon_encoder *enc); 191 void (*rc_layer_init)(struct radeon_encoder *enc); 192 void (*deblocking_filter)(struct radeon_encoder *enc); 193 void (*quality_params)(struct radeon_encoder *enc); 194 void (*slice_header)(struct radeon_encoder *enc); 195 void (*ctx)(struct radeon_encoder *enc); 196 void (*bitstream)(struct radeon_encoder *enc); 197 void (*feedback)(struct radeon_encoder *enc); 198 void (*intra_refresh)(struct radeon_encoder *enc); 199 void (*rc_per_pic)(struct radeon_encoder *enc); 200 void (*encode_params)(struct radeon_encoder *enc); 201 void (*encode_params_codec_spec)(struct radeon_encoder *enc); 202 void (*qp_map)(struct radeon_encoder *enc); 203 void (*op_init)(struct radeon_encoder *enc); 204 void (*op_close)(struct radeon_encoder *enc); 205 void (*op_enc)(struct radeon_encoder *enc); 206 void (*op_init_rc)(struct radeon_encoder *enc); 207 void (*op_init_rc_vbv)(struct radeon_encoder *enc); 208 void (*op_preset)(struct radeon_encoder *enc); 209 void (*encode_headers)(struct radeon_encoder *enc); 210 void (*input_format)(struct radeon_encoder *enc); 211 void (*output_format)(struct radeon_encoder *enc); 212 void (*encode_statistics)(struct radeon_encoder *enc); 213 void (*obu_instructions)(struct radeon_encoder *enc); 214 void (*cdf_default_table)(struct radeon_encoder *enc); 215 void (*ctx_override)(struct radeon_encoder *enc); 216 void (*metadata)(struct radeon_encoder *enc); 217 void (*tile_config)(struct radeon_encoder *enc); 218 void (*encode_latency)(struct radeon_encoder *enc); 219 /* mq is used for preversing multiple queue ibs */ 220 void (*mq_begin)(struct radeon_encoder *enc); 221 void (*mq_encode)(struct radeon_encoder *enc); 222 void (*mq_destroy)(struct radeon_encoder *enc); 223 224 unsigned stream_handle; 225 226 struct pipe_screen *screen; 227 struct radeon_winsys *ws; 228 struct radeon_cmdbuf cs; 229 230 radeon_enc_get_buffer get_buffer; 231 232 struct pb_buffer_lean *handle; 233 struct radeon_surf *luma; 234 struct radeon_surf *chroma; 235 struct pipe_video_buffer *source; 236 237 struct pb_buffer_lean *bs_handle; 238 unsigned bs_size; 239 unsigned bs_offset; 240 241 struct rvid_buffer *si; 242 struct rvid_buffer *fb; 243 struct rvid_buffer *dpb; 244 struct rvid_buffer *cdf; 245 struct rvid_buffer *roi; 246 struct rvid_buffer *meta; 247 struct radeon_enc_pic enc_pic; 248 struct pb_buffer_lean *stats; 249 rvcn_enc_cmd_t cmd; 250 251 unsigned alignment; 252 uint32_t total_task_size; 253 uint32_t *p_task_size; 254 struct rvcn_sq_var sq; 255 256 bool need_feedback; 257 bool need_rate_control; 258 bool need_rc_per_pic; 259 bool need_spec_misc; 260 unsigned dpb_size; 261 unsigned dpb_slots; 262 unsigned roi_size; 263 unsigned metadata_size; 264 265 bool error; 266 267 enum { 268 DPB_LEGACY = 0, 269 DPB_TIER_2 270 } dpb_type; 271 272 struct pipe_context *ectx; 273 }; 274 275 struct rvcn_enc_output_unit_segment { 276 bool is_slice; 277 unsigned size; 278 unsigned offset; 279 }; 280 281 struct rvcn_enc_feedback_data { 282 unsigned num_segments; 283 struct rvcn_enc_output_unit_segment segments[]; 284 }; 285 286 /* structure for determining av1 tile division scheme. 287 * In one direction, it is trying to split width/height into two parts, 288 * main and border, each of which has a length (number of sbs), 289 * Therefore, it has two possible tile sizes, even with multiple 290 * tiles, and in non-uniformed case, it is trying to make tile sizes 291 * as similar as possible. 292 */ 293 294 struct tile_1d_layout { 295 bool uniform_tile_flag; 296 uint32_t nb_main_sb; /* if non-uniform, it means the first part */ 297 uint32_t nb_border_sb; /* if non-uniform, it means the second part */ 298 uint32_t nb_main_tile; 299 uint32_t nb_border_tile; 300 }; 301 302 void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer_lean *buf, 303 unsigned usage, enum radeon_bo_domain domain, signed offset); 304 305 void radeon_enc_dummy(struct radeon_encoder *enc); 306 307 void radeon_enc_code_leb128(unsigned char *buf, unsigned int value, 308 unsigned int num_bytes); 309 310 void radeon_enc_1_2_init(struct radeon_encoder *enc); 311 312 void radeon_enc_2_0_init(struct radeon_encoder *enc); 313 314 void radeon_enc_3_0_init(struct radeon_encoder *enc); 315 316 void radeon_enc_4_0_init(struct radeon_encoder *enc); 317 318 void radeon_enc_5_0_init(struct radeon_encoder *enc); 319 320 unsigned int radeon_enc_write_sps(struct radeon_encoder *enc, uint8_t nal_byte, uint8_t *out); 321 322 unsigned int radeon_enc_write_pps(struct radeon_encoder *enc, uint8_t nal_byte, uint8_t *out); 323 324 unsigned int radeon_enc_write_vps(struct radeon_encoder *enc, uint8_t *out); 325 326 unsigned int radeon_enc_write_sps_hevc(struct radeon_encoder *enc, uint8_t *out); 327 328 unsigned int radeon_enc_write_pps_hevc(struct radeon_encoder *enc, uint8_t *out); 329 330 unsigned int radeon_enc_write_sequence_header(struct radeon_encoder *enc, uint8_t *obu_bytes, uint8_t *out); 331 332 void radeon_enc_av1_bs_instruction_type(struct radeon_encoder *enc, 333 struct radeon_bitstream *bs, 334 unsigned int inst, unsigned int obu_type); 335 336 void radeon_enc_av1_obu_header(struct radeon_encoder *enc, struct radeon_bitstream *bs, uint32_t obu_type); 337 338 void radeon_enc_av1_frame_header_common(struct radeon_encoder *enc, struct radeon_bitstream *bs, bool frame_header); 339 340 void radeon_enc_av1_tile_group(struct radeon_encoder *enc, struct radeon_bitstream *bs); 341 342 unsigned int radeon_enc_value_bits(unsigned int value); 343 344 unsigned int radeon_enc_av1_tile_log2(unsigned int blk_size, unsigned int max); 345 346 bool radeon_enc_is_av1_uniform_tile (uint32_t nb_sb, uint32_t nb_tiles, 347 uint32_t min_nb_sb, struct tile_1d_layout *p); 348 349 void radeon_enc_av1_tile_layout (uint32_t nb_sb, uint32_t nb_tiles, uint32_t min_nb_sb, 350 struct tile_1d_layout *p); 351 352 bool radeon_enc_av1_skip_mode_allowed(struct radeon_encoder *enc, uint32_t frames[2]); 353 354 void radeon_enc_create_dpb_aux_buffers(struct radeon_encoder *enc, 355 struct radeon_enc_dpb_buffer *buf); 356 357 #endif // _RADEON_VCN_ENC_H 358