1 /**************************************************************************
2 *
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 **************************************************************************/
8
9 #include "pipe/p_video_codec.h"
10
11 #include "util/u_video.h"
12
13 #include "si_pipe.h"
14 #include "radeon_vcn_enc.h"
15
16 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
17 #define RENCODE_FW_INTERFACE_MINOR_VERSION 15
18
radeon_enc_sq_begin(struct radeon_encoder * enc)19 static void radeon_enc_sq_begin(struct radeon_encoder *enc)
20 {
21 rvcn_sq_header(&enc->cs, &enc->sq, true);
22 enc->mq_begin(enc);
23 rvcn_sq_tail(&enc->cs, &enc->sq);
24 }
25
radeon_enc_sq_encode(struct radeon_encoder * enc)26 static void radeon_enc_sq_encode(struct radeon_encoder *enc)
27 {
28 rvcn_sq_header(&enc->cs, &enc->sq, true);
29 enc->mq_encode(enc);
30 rvcn_sq_tail(&enc->cs, &enc->sq);
31 }
32
radeon_enc_sq_destroy(struct radeon_encoder * enc)33 static void radeon_enc_sq_destroy(struct radeon_encoder *enc)
34 {
35 rvcn_sq_header(&enc->cs, &enc->sq, true);
36 enc->mq_destroy(enc);
37 rvcn_sq_tail(&enc->cs, &enc->sq);
38 }
39
radeon_enc_op_preset(struct radeon_encoder * enc)40 static void radeon_enc_op_preset(struct radeon_encoder *enc)
41 {
42 uint32_t preset_mode;
43
44 if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_SPEED &&
45 (!enc->enc_pic.hevc_deblock.disable_sao &&
46 (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC)))
47 preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE;
48 else if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_QUALITY)
49 preset_mode = RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE;
50 else if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_HIGH_QUALITY)
51 preset_mode = RENCODE_IB_OP_SET_HIGH_QUALITY_ENCODING_MODE;
52 else if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_BALANCE)
53 preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE;
54 else
55 preset_mode = RENCODE_IB_OP_SET_SPEED_ENCODING_MODE;
56
57 RADEON_ENC_BEGIN(preset_mode);
58 RADEON_ENC_END();
59 }
60
radeon_enc_session_init(struct radeon_encoder * enc)61 static void radeon_enc_session_init(struct radeon_encoder *enc)
62 {
63 enc->enc_pic.session_init.slice_output_enabled = 0;
64 enc->enc_pic.session_init.display_remote = 0;
65 enc->enc_pic.session_init.pre_encode_mode = enc->enc_pic.quality_modes.pre_encode_mode;
66 enc->enc_pic.session_init.pre_encode_chroma_enabled = !!(enc->enc_pic.quality_modes.pre_encode_mode);
67
68 RADEON_ENC_BEGIN(enc->cmd.session_init);
69 RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
70 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
71 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
72 RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
73 RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
74 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
75 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
76 RADEON_ENC_CS(enc->enc_pic.session_init.slice_output_enabled);
77 RADEON_ENC_CS(enc->enc_pic.session_init.display_remote);
78 RADEON_ENC_CS(enc->enc_pic.session_init.WA_flags);
79 RADEON_ENC_END();
80 }
81
radeon_enc_spec_misc_av1(struct radeon_encoder * enc)82 static void radeon_enc_spec_misc_av1(struct radeon_encoder *enc)
83 {
84 rvcn_enc_av1_tile_config_t *p_config = &enc->enc_pic.av1_tile_config;
85 struct tile_1d_layout tile_layout;
86 uint32_t num_of_tiles;
87 uint32_t frame_width_in_sb;
88 uint32_t frame_height_in_sb;
89 uint32_t num_tiles_cols;
90 uint32_t num_tiles_rows;
91 uint32_t max_tile_area_sb = RENCODE_AV1_MAX_TILE_AREA >> (2 * 6);
92 uint32_t max_tile_width_in_sb = RENCODE_AV1_MAX_TILE_WIDTH >> 6;
93 uint32_t max_tile_ares_in_sb = 0;
94 uint32_t max_tile_height_in_sb = 0;
95 uint32_t min_log2_tiles_width_in_sb;
96 uint32_t min_log2_tiles;
97
98 frame_width_in_sb = PIPE_ALIGN_IN_BLOCK_SIZE(enc->enc_pic.session_init.aligned_picture_width,
99 PIPE_AV1_ENC_SB_SIZE);
100 frame_height_in_sb = PIPE_ALIGN_IN_BLOCK_SIZE(enc->enc_pic.session_init.aligned_picture_height,
101 PIPE_AV1_ENC_SB_SIZE);
102 num_tiles_cols = (frame_width_in_sb > max_tile_width_in_sb) ? 2 : 1;
103 num_tiles_rows = CLAMP(p_config->num_tile_rows,
104 1, RENCODE_AV1_TILE_CONFIG_MAX_NUM_ROWS);
105 min_log2_tiles_width_in_sb = radeon_enc_av1_tile_log2(max_tile_width_in_sb, frame_width_in_sb);
106 min_log2_tiles = MAX2(min_log2_tiles_width_in_sb, radeon_enc_av1_tile_log2(max_tile_area_sb,
107 frame_width_in_sb * frame_height_in_sb));
108
109 max_tile_width_in_sb = (num_tiles_cols == 1) ? frame_width_in_sb : max_tile_width_in_sb;
110
111 if (min_log2_tiles)
112 max_tile_ares_in_sb = (frame_width_in_sb * frame_height_in_sb)
113 >> (min_log2_tiles + 1);
114 else
115 max_tile_ares_in_sb = frame_width_in_sb * frame_height_in_sb;
116
117 max_tile_height_in_sb = DIV_ROUND_UP(max_tile_ares_in_sb, max_tile_width_in_sb);
118 num_tiles_rows = MAX2(num_tiles_rows,
119 DIV_ROUND_UP(frame_height_in_sb, max_tile_height_in_sb));
120
121 radeon_enc_av1_tile_layout(frame_height_in_sb, num_tiles_rows, 1, &tile_layout);
122 num_tiles_rows = tile_layout.nb_main_tile + tile_layout.nb_border_tile;
123
124 num_of_tiles = num_tiles_cols * num_tiles_rows;
125
126 /* in case of multiple tiles, it should be an obu frame */
127 if (num_of_tiles > 1)
128 enc->enc_pic.is_obu_frame = 1;
129
130 RADEON_ENC_BEGIN(enc->cmd.spec_misc_av1);
131 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.palette_mode_enable);
132 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.mv_precision);
133 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.cdef_mode);
134 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.disable_cdf_update);
135 RADEON_ENC_CS(enc->enc_pic.av1_spec_misc.disable_frame_end_update_cdf);
136 RADEON_ENC_CS(num_of_tiles);
137 RADEON_ENC_CS(0);
138 RADEON_ENC_CS(0);
139 RADEON_ENC_CS(0xFFFFFFFF);
140 RADEON_ENC_CS(0xFFFFFFFF);
141 RADEON_ENC_END();
142 }
143
radeon_enc_cdf_default_table(struct radeon_encoder * enc)144 static void radeon_enc_cdf_default_table(struct radeon_encoder *enc)
145 {
146 bool use_cdf_default = enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY ||
147 enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY ||
148 enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SWITCH ||
149 (enc->enc_pic.enable_error_resilient_mode);
150
151 enc->enc_pic.av1_cdf_default_table.use_cdf_default = use_cdf_default ? 1 : 0;
152
153 RADEON_ENC_BEGIN(enc->cmd.cdf_default_table_av1);
154 RADEON_ENC_CS(enc->enc_pic.av1_cdf_default_table.use_cdf_default);
155 RADEON_ENC_READWRITE(enc->cdf->res->buf, enc->cdf->res->domains, 0);
156 RADEON_ENC_ADDR_SWAP();
157 RADEON_ENC_END();
158 }
159
radeon_enc_av1_obu_header(struct radeon_encoder * enc,struct radeon_bitstream * bs,uint32_t obu_type)160 void radeon_enc_av1_obu_header(struct radeon_encoder *enc, struct radeon_bitstream *bs, uint32_t obu_type)
161 {
162 /* obu header () */
163 /* obu_forbidden_bit */
164 radeon_bs_code_fixed_bits(bs, 0, 1);
165 /* obu_type */
166 radeon_bs_code_fixed_bits(bs, obu_type, 4);
167 /* obu_extension_flag */
168 radeon_bs_code_fixed_bits(bs, enc->enc_pic.av1.desc->obu_extension_flag ? 1 : 0, 1);
169 /* obu_has_size_field */
170 radeon_bs_code_fixed_bits(bs, 1, 1);
171 /* obu_reserved_1bit */
172 radeon_bs_code_fixed_bits(bs, 0, 1);
173
174 if (enc->enc_pic.av1.desc->obu_extension_flag) {
175 radeon_bs_code_fixed_bits(bs, enc->enc_pic.temporal_id, 3);
176 radeon_bs_code_fixed_bits(bs, 0, 2); /* spatial_id should always be zero */
177 radeon_bs_code_fixed_bits(bs, 0, 3); /* reserved 3 bits */
178 }
179 }
180
radeon_enc_write_sequence_header(struct radeon_encoder * enc,uint8_t * obu_bytes,uint8_t * out)181 unsigned int radeon_enc_write_sequence_header(struct radeon_encoder *enc, uint8_t *obu_bytes, uint8_t *out)
182 {
183 struct radeon_bitstream bs;
184 uint8_t *size_offset;
185 uint32_t obu_size;
186 uint32_t width_bits;
187 uint32_t height_bits;
188 struct pipe_av1_enc_seq_param *seq = &enc->enc_pic.av1.desc->seq;
189
190 radeon_bs_reset(&bs, out, NULL);
191 radeon_bs_code_fixed_bits(&bs, obu_bytes[0], 8);
192 if (obu_bytes[0] & 0x4) /* obu_extension_flag */
193 radeon_bs_code_fixed_bits(&bs, obu_bytes[1], 8);
194
195 /* obu_size, use one byte for header, the size will be written in afterwards */
196 size_offset = &out[bs.bits_output / 8];
197 radeon_bs_code_fixed_bits(&bs, 0, 8);
198
199 /* sequence_header_obu() */
200 /* seq_profile */
201 radeon_bs_code_fixed_bits(&bs, seq->profile, 3);
202 /* still_picture */
203 radeon_bs_code_fixed_bits(&bs, seq->seq_bits.still_picture, 1);
204 /* reduced_still_picture_header */
205 radeon_bs_code_fixed_bits(&bs, seq->seq_bits.reduced_still_picture_header, 1);
206
207 if (seq->seq_bits.reduced_still_picture_header) {
208 /* seq_level_idx[0] */
209 radeon_bs_code_fixed_bits(&bs, seq->seq_level_idx[0], 5);
210 } else {
211 /* timing_info_present_flag */
212 radeon_bs_code_fixed_bits(&bs, seq->seq_bits.timing_info_present_flag, 1);
213
214 if (seq->seq_bits.timing_info_present_flag) {
215 /* num_units_in_display_tick */
216 radeon_bs_code_fixed_bits(&bs, seq->num_units_in_display_tick, 32);
217 /* time_scale */
218 radeon_bs_code_fixed_bits(&bs, seq->time_scale, 32);
219 /* equal_picture_interval */
220 radeon_bs_code_fixed_bits(&bs, seq->seq_bits.equal_picture_interval, 1);
221 /* num_ticks_per_picture_minus_1 */
222 if (seq->seq_bits.equal_picture_interval)
223 radeon_bs_code_uvlc(&bs, seq->num_tick_per_picture_minus1);
224 /* decoder_model_info_present_flag */
225 radeon_bs_code_fixed_bits(&bs, seq->seq_bits.decoder_model_info_present_flag, 1);
226 if (seq->seq_bits.decoder_model_info_present_flag) {
227 /* buffer_delay_length_minus1 */
228 radeon_bs_code_fixed_bits(&bs, seq->decoder_model_info.buffer_delay_length_minus1, 5);
229 /* num_units_in_decoding_tick */
230 radeon_bs_code_fixed_bits(&bs, seq->decoder_model_info.num_units_in_decoding_tick, 32);
231 /* buffer_removal_time_length_minus1 */
232 radeon_bs_code_fixed_bits(&bs, seq->decoder_model_info.buffer_removal_time_length_minus1, 5);
233 /* frame_presentation_time_length_minus1 */
234 radeon_bs_code_fixed_bits(&bs, seq->decoder_model_info.frame_presentation_time_length_minus1, 5);
235 }
236 }
237
238 /* initial_display_delay_present_flag */
239 radeon_bs_code_fixed_bits(&bs, seq->seq_bits.initial_display_delay_present_flag, 1);
240 /* operating_points_cnt_minus_1 */
241 radeon_bs_code_fixed_bits(&bs, seq->num_temporal_layers - 1, 5);
242
243 for (uint32_t i = 0; i < seq->num_temporal_layers; i++) {
244 /* operating_point_idc[i] */
245 radeon_bs_code_fixed_bits(&bs, seq->operating_point_idc[i], 12);
246 /* seq_level_idx[i] */
247 radeon_bs_code_fixed_bits(&bs, seq->seq_level_idx[i], 5);
248 if (seq->seq_level_idx[i] > 7)
249 /* seq_tier[i] */
250 radeon_bs_code_fixed_bits(&bs, seq->seq_tier[i], 1);
251 if (seq->seq_bits.decoder_model_info_present_flag) {
252 /* decoder_model_present_for_this_op[i] */
253 radeon_bs_code_fixed_bits(&bs, seq->decoder_model_present_for_this_op[i], 1);
254 if (seq->decoder_model_present_for_this_op[i]) {
255 uint32_t length = seq->decoder_model_info.buffer_delay_length_minus1 + 1;
256 /* decoder_buffer_delay[i] */
257 radeon_bs_code_fixed_bits(&bs, seq->decoder_buffer_delay[i], length);
258 /* encoder_buffer_delay[i] */
259 radeon_bs_code_fixed_bits(&bs, seq->encoder_buffer_delay[i], length);
260 /* low_delay_mode_flag[i] */
261 radeon_bs_code_fixed_bits(&bs, seq->low_delay_mode_flag[i], 1);
262 }
263 }
264 if (seq->seq_bits.initial_display_delay_present_flag) {
265 /* initial_display_delay_present_for_this_op[i] */
266 radeon_bs_code_fixed_bits(&bs, seq->initial_display_delay_present_for_this_op[i], 1);
267 if (seq->initial_display_delay_present_for_this_op[i])
268 /* initial_display_delay_minus_1[i] */
269 radeon_bs_code_fixed_bits(&bs, seq->initial_display_delay_minus_1[i], 4);
270 }
271 }
272 }
273
274 /* frame_width_bits_minus_1 */
275 width_bits = radeon_enc_value_bits(enc->enc_pic.av1.coded_width);
276 radeon_bs_code_fixed_bits(&bs, width_bits - 1, 4);
277 /* frame_height_bits_minus_1 */
278 height_bits = radeon_enc_value_bits(enc->enc_pic.av1.coded_height);
279 radeon_bs_code_fixed_bits(&bs, height_bits - 1, 4);
280 /* max_frame_width_minus_1 */
281 radeon_bs_code_fixed_bits(&bs, enc->enc_pic.av1.coded_width - 1,
282 width_bits);
283 /* max_frame_height_minus_1 */
284 radeon_bs_code_fixed_bits(&bs, enc->enc_pic.av1.coded_height - 1,
285 height_bits);
286
287 if (!seq->seq_bits.reduced_still_picture_header)
288 /* frame_id_numbers_present_flag */
289 radeon_bs_code_fixed_bits(&bs, seq->seq_bits.frame_id_number_present_flag, 1);
290
291 if (seq->seq_bits.frame_id_number_present_flag) {
292 /* delta_frame_id_length_minus_2 */
293 radeon_bs_code_fixed_bits(&bs, seq->delta_frame_id_length - 2, 4);
294 /* additional_frame_id_length_minus_1 */
295 radeon_bs_code_fixed_bits(&bs, seq->additional_frame_id_length - 1, 3);
296 }
297
298 /* use_128x128_superblock */
299 radeon_bs_code_fixed_bits(&bs, 0, 1);
300 /* enable_filter_intra */
301 radeon_bs_code_fixed_bits(&bs, 0, 1);
302 /* enable_intra_edge_filter */
303 radeon_bs_code_fixed_bits(&bs, 0, 1);
304
305 if (!seq->seq_bits.reduced_still_picture_header) {
306 /* enable_interintra_compound */
307 radeon_bs_code_fixed_bits(&bs, 0, 1);
308 /* enable_masked_compound */
309 radeon_bs_code_fixed_bits(&bs, 0, 1);
310 /* enable_warped_motion */
311 radeon_bs_code_fixed_bits(&bs, 0, 1);
312 /* enable_dual_filter */
313 radeon_bs_code_fixed_bits(&bs, 0, 1);
314 /* enable_order_hint */
315 radeon_bs_code_fixed_bits(&bs, seq->seq_bits.enable_order_hint, 1);
316
317 if (seq->seq_bits.enable_order_hint) {
318 /* enable_jnt_comp */
319 radeon_bs_code_fixed_bits(&bs, 0, 1);
320 /* enable_ref_frame_mvs */
321 radeon_bs_code_fixed_bits(&bs, 0, 1);
322 }
323
324 /* seq_choose_screen_content_tools */
325 radeon_bs_code_fixed_bits(&bs, enc->enc_pic.disable_screen_content_tools ? 0 : 1, 1);
326 if (enc->enc_pic.disable_screen_content_tools)
327 /* seq_force_screen_content_tools */
328 radeon_bs_code_fixed_bits(&bs, 0, 1);
329 else
330 /* seq_choose_integer_mv */
331 radeon_bs_code_fixed_bits(&bs, 1, 1);
332
333 if (seq->seq_bits.enable_order_hint)
334 /* order_hint_bits_minus_1 */
335 radeon_bs_code_fixed_bits(&bs, seq->order_hint_bits - 1, 3);
336 }
337
338 /* enable_superres */
339 radeon_bs_code_fixed_bits(&bs, 0, 1);
340 /* enable_cdef */
341 radeon_bs_code_fixed_bits(&bs, enc->enc_pic.av1_spec_misc.cdef_mode ? 1 : 0, 1);
342 /* enable_restoration */
343 radeon_bs_code_fixed_bits(&bs, 0, 1);
344 /* high_bitdepth */
345 radeon_bs_code_fixed_bits(&bs, enc->enc_pic.enc_output_format.output_color_bit_depth, 1);
346 /* mono_chrome */
347 radeon_bs_code_fixed_bits(&bs, 0, 1);
348 /* color_description_present_flag */
349 radeon_bs_code_fixed_bits(&bs, seq->seq_bits.color_description_present_flag, 1);
350
351 if (seq->seq_bits.color_description_present_flag) {
352 /* color_primaries */
353 radeon_bs_code_fixed_bits(&bs, seq->color_config.color_primaries, 8);
354 /* transfer_characteristics */
355 radeon_bs_code_fixed_bits(&bs, seq->color_config.transfer_characteristics, 8);
356 /* matrix_coefficients */
357 radeon_bs_code_fixed_bits(&bs, seq->color_config.matrix_coefficients, 8);
358 }
359 /* color_range */
360 radeon_bs_code_fixed_bits(&bs, seq->color_config.color_range, 1);
361 /* chroma_sample_position */
362 radeon_bs_code_fixed_bits(&bs, seq->color_config.chroma_sample_position, 2);
363 /* separate_uv_delta_q */
364 bool separate_delta_q = false;
365 radeon_bs_code_fixed_bits(&bs, !!(separate_delta_q), 1);
366 /* film_grain_params_present */
367 radeon_bs_code_fixed_bits(&bs, 0, 1);
368
369 /* trailing_one_bit */
370 radeon_bs_code_fixed_bits(&bs, 1, 1);
371 radeon_bs_byte_align(&bs);
372
373 obu_size = (uint32_t)(&out[bs.bits_output / 8] - size_offset - 1);
374 radeon_enc_code_leb128(size_offset, obu_size, 1);
375
376 return bs.bits_output / 8;
377 }
378
radeon_enc_av1_frame_header_common(struct radeon_encoder * enc,struct radeon_bitstream * bs,bool frame_header)379 void radeon_enc_av1_frame_header_common(struct radeon_encoder *enc, struct radeon_bitstream *bs, bool frame_header)
380 {
381 uint32_t i;
382 bool frame_is_intra = enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY ||
383 enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY;
384 uint32_t obu_type = frame_header ? RENCODE_OBU_TYPE_FRAME_HEADER
385 : RENCODE_OBU_TYPE_FRAME;
386 bool error_resilient_mode = false;
387 struct pipe_av1_enc_picture_desc *av1 = enc->enc_pic.av1.desc;
388
389 radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
390
391 radeon_enc_av1_obu_header(enc, bs, obu_type);
392
393 radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_SIZE, 0);
394
395 /* uncompressed_header() */
396 radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
397
398 if (!av1->seq.seq_bits.reduced_still_picture_header) {
399 radeon_bs_code_fixed_bits(bs, 0, 1); /* show_existing_frame */
400 /* frame_type */
401 radeon_bs_code_fixed_bits(bs, enc->enc_pic.frame_type, 2);
402 /* show_frame */
403 radeon_bs_code_fixed_bits(bs, av1->show_frame, 1);
404 if (!av1->show_frame)
405 /* showable_frame */
406 radeon_bs_code_fixed_bits(bs, av1->showable_frame, 1);
407
408 if ((enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SWITCH) ||
409 (enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY && av1->show_frame))
410 error_resilient_mode = true;
411 else {
412 /* error_resilient_mode */
413 radeon_bs_code_fixed_bits(bs, enc->enc_pic.enable_error_resilient_mode ? 1 : 0, 1);
414 error_resilient_mode = enc->enc_pic.enable_error_resilient_mode;
415 }
416 }
417
418 /* disable_cdf_update */
419 radeon_bs_code_fixed_bits(bs, enc->enc_pic.av1_spec_misc.disable_cdf_update ? 1 : 0, 1);
420
421 bool allow_screen_content_tools = false;
422 if (av1->seq.seq_bits.reduced_still_picture_header || !enc->enc_pic.disable_screen_content_tools) {
423 /* allow_screen_content_tools */
424 allow_screen_content_tools = enc->enc_pic.av1_spec_misc.palette_mode_enable ||
425 enc->enc_pic.force_integer_mv;
426 radeon_bs_code_fixed_bits(bs, allow_screen_content_tools ? 1 : 0, 1);
427 }
428
429 if (allow_screen_content_tools)
430 /* force_integer_mv */
431 radeon_bs_code_fixed_bits(bs, enc->enc_pic.force_integer_mv ? 1 : 0, 1);
432
433 if (av1->seq.seq_bits.frame_id_number_present_flag)
434 /* current_frame_id */
435 radeon_bs_code_fixed_bits(bs, av1->current_frame_id,
436 av1->seq.delta_frame_id_length + av1->seq.additional_frame_id_length);
437
438 bool frame_size_override = false;
439 if (enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_SWITCH)
440 frame_size_override = true;
441 else if (!av1->seq.seq_bits.reduced_still_picture_header) {
442 /* frame_size_override_flag */
443 frame_size_override = false;
444 radeon_bs_code_fixed_bits(bs, 0, 1);
445 }
446
447 if (av1->seq.seq_bits.enable_order_hint)
448 /* order_hint */
449 radeon_bs_code_fixed_bits(bs, av1->order_hint, av1->seq.order_hint_bits);
450
451 if (!frame_is_intra && !error_resilient_mode)
452 /* primary_ref_frame */
453 radeon_bs_code_fixed_bits(bs, av1->primary_ref_frame, 3);
454
455 if ((enc->enc_pic.frame_type != PIPE_AV1_ENC_FRAME_TYPE_SWITCH) &&
456 (enc->enc_pic.frame_type != PIPE_AV1_ENC_FRAME_TYPE_KEY || !av1->show_frame))
457 /* refresh_frame_flags */
458 radeon_bs_code_fixed_bits(bs, av1->refresh_frame_flags, 8);
459
460 if ((!frame_is_intra || av1->refresh_frame_flags != 0xff) &&
461 error_resilient_mode && av1->seq.seq_bits.enable_order_hint)
462 for (i = 0; i < RENCODE_AV1_NUM_REF_FRAMES; i++)
463 /* ref_order_hint */
464 radeon_bs_code_fixed_bits(bs, av1->ref_order_hint[i], av1->seq.order_hint_bits);
465
466 if (frame_is_intra) {
467 /* render_and_frame_size_different */
468 radeon_bs_code_fixed_bits(bs, av1->enable_render_size ? 1 : 0, 1);
469 if (av1->enable_render_size) {
470 /* render_width_minus_1 */
471 radeon_bs_code_fixed_bits(bs, av1->render_width_minus_1, 16);
472 /* render_height_minus_1 */
473 radeon_bs_code_fixed_bits(bs, av1->render_height_minus_1, 16);
474 }
475 if (!enc->enc_pic.disable_screen_content_tools &&
476 (enc->enc_pic.av1_spec_misc.palette_mode_enable || enc->enc_pic.force_integer_mv))
477 /* allow_intrabc */
478 radeon_bs_code_fixed_bits(bs, 0, 1);
479 } else {
480 if (av1->seq.seq_bits.enable_order_hint)
481 /* frame_refs_short_signaling */
482 radeon_bs_code_fixed_bits(bs, av1->frame_refs_short_signaling, 1);
483 if (av1->frame_refs_short_signaling) {
484 radeon_bs_code_fixed_bits(bs, av1->last_frame_idx, 3);
485 radeon_bs_code_fixed_bits(bs, av1->gold_frame_idx, 3);
486 }
487 for (i = 0; i < RENCODE_AV1_REFS_PER_FRAME; i++) {
488 /* ref_frame_idx[i] */
489 radeon_bs_code_fixed_bits(bs, av1->ref_frame_idx[i], 3);
490 if (av1->seq.seq_bits.frame_id_number_present_flag)
491 /* delta_frame_id_minus_1[i] */
492 radeon_bs_code_fixed_bits(bs, av1->delta_frame_id_minus_1[i], av1->seq.delta_frame_id_length);
493 }
494
495 if (frame_size_override && !error_resilient_mode)
496 /* found_ref */
497 radeon_bs_code_fixed_bits(bs, 1, 1);
498 else {
499 if(frame_size_override) {
500 /* frame_width_minus_1 */
501 uint32_t used_bits =
502 radeon_enc_value_bits(enc->enc_pic.av1.coded_width - 1);
503 radeon_bs_code_fixed_bits(bs, enc->enc_pic.av1.coded_width - 1,
504 used_bits);
505 /* frame_height_minus_1 */
506 used_bits = radeon_enc_value_bits(enc->enc_pic.av1.coded_height - 1);
507 radeon_bs_code_fixed_bits(bs, enc->enc_pic.av1.coded_height - 1,
508 used_bits);
509 }
510 /* render_and_frame_size_different */
511 radeon_bs_code_fixed_bits(bs, av1->enable_render_size ? 1 : 0, 1);
512 if (av1->enable_render_size) {
513 /* render_width_minus_1 */
514 radeon_bs_code_fixed_bits(bs, av1->render_width_minus_1, 16);
515 /* render_height_minus_1 */
516 radeon_bs_code_fixed_bits(bs, av1->render_height_minus_1, 16);
517 }
518 }
519
520 if (enc->enc_pic.disable_screen_content_tools || !enc->enc_pic.force_integer_mv)
521 /* allow_high_precision_mv */
522 radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_ALLOW_HIGH_PRECISION_MV, 0);
523
524 /* read_interpolation_filter */
525 radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_INTERPOLATION_FILTER, 0);
526
527 radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
528 /* is_motion_mode_switchable */
529 radeon_bs_code_fixed_bits(bs, 0, 1);
530 }
531
532 if (!av1->seq.seq_bits.reduced_still_picture_header && !enc->enc_pic.av1_spec_misc.disable_cdf_update)
533 /* disable_frame_end_update_cdf */
534 radeon_bs_code_fixed_bits(bs, enc->enc_pic.av1_spec_misc.disable_frame_end_update_cdf ? 1 : 0, 1);
535 }
536
radeon_enc_av1_frame_header(struct radeon_encoder * enc,struct radeon_bitstream * bs,bool frame_header)537 static void radeon_enc_av1_frame_header(struct radeon_encoder *enc, struct radeon_bitstream *bs, bool frame_header)
538 {
539 bool frame_is_intra = enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_KEY ||
540 enc->enc_pic.frame_type == PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY;
541
542 radeon_enc_av1_frame_header_common(enc, bs, frame_header);
543
544 /* tile_info */
545 radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_V4_AV1_BITSTREAM_INSTRUCTION_TILE_INFO, 0);
546 /* quantization_params */
547 radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_V4_AV1_BITSTREAM_INSTRUCTION_QUANTIZATION_PARAMS, 0);
548 /* segmentation_enable */
549 radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
550 radeon_bs_code_fixed_bits(bs, 0, 1);
551 /* delta_q_params */
552 radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_Q_PARAMS, 0);
553 /* delta_lf_params */
554 radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_DELTA_LF_PARAMS, 0);
555 /* loop_filter_params */
556 radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_LOOP_FILTER_PARAMS, 0);
557 /* cdef_params */
558 radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_CDEF_PARAMS, 0);
559 /* lr_params */
560 /* read_tx_mode */
561 radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_READ_TX_MODE, 0);
562
563 radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
564
565 if (!frame_is_intra)
566 /* reference_select */
567 radeon_bs_code_fixed_bits(bs, 0, 1);
568
569 /* reduced_tx_set */
570 radeon_bs_code_fixed_bits(bs, 0, 1);
571
572 if (!frame_is_intra)
573 for (uint32_t ref = 1 /*LAST_FRAME*/; ref <= 7 /*ALTREF_FRAME*/; ref++)
574 /* is_global */
575 radeon_bs_code_fixed_bits(bs, 0, 1);
576 /* film_grain_params() */
577 }
578
radeon_enc_av1_tile_group(struct radeon_encoder * enc,struct radeon_bitstream * bs)579 void radeon_enc_av1_tile_group(struct radeon_encoder *enc, struct radeon_bitstream *bs)
580 {
581 radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_START,
582 RENCODE_OBU_START_TYPE_TILE_GROUP);
583 radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_COPY, 0);
584
585 radeon_enc_av1_obu_header(enc, bs, RENCODE_OBU_TYPE_TILE_GROUP);
586
587 radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_SIZE, 0);
588 radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU, 0);
589 radeon_enc_av1_bs_instruction_type(enc, bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_END, 0);
590 }
591
radeon_enc_obu_instruction(struct radeon_encoder * enc)592 static void radeon_enc_obu_instruction(struct radeon_encoder *enc)
593 {
594 struct radeon_bitstream bs;
595 bool frame_header = !enc->enc_pic.is_obu_frame;
596
597 radeon_bs_reset(&bs, NULL, &enc->cs);
598
599 RADEON_ENC_BEGIN(enc->cmd.bitstream_instruction_av1);
600
601 radeon_enc_av1_bs_instruction_type(enc, &bs,
602 RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_START,
603 frame_header ? RENCODE_OBU_START_TYPE_FRAME_HEADER
604 : RENCODE_OBU_START_TYPE_FRAME);
605
606 radeon_enc_av1_frame_header(enc, &bs, frame_header);
607
608 if (!frame_header)
609 radeon_enc_av1_bs_instruction_type(enc, &bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_TILE_GROUP_OBU, 0);
610
611 radeon_enc_av1_bs_instruction_type(enc, &bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_OBU_END, 0);
612
613 if (frame_header)
614 radeon_enc_av1_tile_group(enc, &bs);
615
616 radeon_enc_av1_bs_instruction_type(enc, &bs, RENCODE_AV1_BITSTREAM_INSTRUCTION_END, 0);
617 RADEON_ENC_END();
618 }
619
620 /* av1 encode params */
radeon_enc_av1_encode_params(struct radeon_encoder * enc)621 static void radeon_enc_av1_encode_params(struct radeon_encoder *enc)
622 {
623 switch (enc->enc_pic.frame_type) {
624 case PIPE_AV1_ENC_FRAME_TYPE_KEY:
625 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
626 break;
627 case PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY:
628 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
629 break;
630 case PIPE_AV1_ENC_FRAME_TYPE_INTER:
631 case PIPE_AV1_ENC_FRAME_TYPE_SWITCH:
632 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
633 break;
634 default:
635 assert(0); /* never come to this condition */
636 }
637
638 if (enc->luma->meta_offset)
639 RADEON_ENC_ERR("DCC surfaces not supported.\n");
640
641 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
642 enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma ?
643 enc->chroma->u.gfx9.surf_pitch : enc->luma->u.gfx9.surf_pitch;
644 enc->enc_pic.enc_params.input_pic_swizzle_mode = enc->luma->u.gfx9.swizzle_mode;
645
646 RADEON_ENC_BEGIN(enc->cmd.enc_params);
647 RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
648 RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
649 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
650 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma ?
651 enc->chroma->u.gfx9.surf_offset : enc->luma->u.gfx9.surf_pitch);
652 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
653 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
654 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
655 RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
656 RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
657 RADEON_ENC_END();
658 }
659
radeon_enc_ref_swizzle_mode(struct radeon_encoder * enc)660 static uint32_t radeon_enc_ref_swizzle_mode(struct radeon_encoder *enc)
661 {
662 /* return RENCODE_REC_SWIZZLE_MODE_LINEAR; for debugging purpose */
663 if (enc->enc_pic.bit_depth_luma_minus8 != 0)
664 return RENCODE_REC_SWIZZLE_MODE_8x8_1D_THIN_12_24BPP;
665 else
666 return RENCODE_REC_SWIZZLE_MODE_256B_D;
667 }
668
radeon_enc_ctx(struct radeon_encoder * enc)669 static void radeon_enc_ctx(struct radeon_encoder *enc)
670 {
671
672 bool is_av1 = u_reduce_video_profile(enc->base.profile)
673 == PIPE_VIDEO_FORMAT_AV1;
674 enc->enc_pic.ctx_buf.swizzle_mode = radeon_enc_ref_swizzle_mode(enc);
675 enc->enc_pic.ctx_buf.two_pass_search_center_map_offset = 0;
676
677 RADEON_ENC_BEGIN(enc->cmd.ctx);
678 RADEON_ENC_READWRITE(enc->dpb->res->buf, enc->dpb->res->domains, 0);
679 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
680 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
681 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
682 RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
683
684 for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
685 rvcn_enc_reconstructed_picture_t *pic =
686 &enc->enc_pic.ctx_buf.reconstructed_pictures[i];
687 RADEON_ENC_CS(pic->luma_offset);
688 RADEON_ENC_CS(pic->chroma_offset);
689 if (is_av1) {
690 RADEON_ENC_CS(pic->av1.av1_cdf_frame_context_offset);
691 RADEON_ENC_CS(pic->av1.av1_cdef_algorithm_context_offset);
692 } else {
693 RADEON_ENC_CS(0x00000000); /* unused offset 1 */
694 RADEON_ENC_CS(0x00000000); /* unused offset 2 */
695 }
696 }
697
698 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_picture_luma_pitch);
699 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_picture_chroma_pitch);
700
701 for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
702 rvcn_enc_reconstructed_picture_t *pic =
703 &enc->enc_pic.ctx_buf.pre_encode_reconstructed_pictures[i];
704 RADEON_ENC_CS(pic->luma_offset);
705 RADEON_ENC_CS(pic->chroma_offset);
706 if (is_av1) {
707 RADEON_ENC_CS(pic->av1.av1_cdf_frame_context_offset);
708 RADEON_ENC_CS(pic->av1.av1_cdef_algorithm_context_offset);
709 } else {
710 RADEON_ENC_CS(0x00000000); /* unused offset 1 */
711 RADEON_ENC_CS(0x00000000); /* unused offset 2 */
712 }
713 }
714
715 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.red_offset);
716 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.green_offset);
717 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.blue_offset);
718
719 RADEON_ENC_CS(enc->enc_pic.ctx_buf.two_pass_search_center_map_offset);
720 if (is_av1)
721 RADEON_ENC_CS(enc->enc_pic.ctx_buf.av1.av1_sdb_intermediate_context_offset);
722 else
723 RADEON_ENC_CS(enc->enc_pic.ctx_buf.colloc_buffer_offset);
724 RADEON_ENC_END();
725 }
726
radeon_enc_header_av1(struct radeon_encoder * enc)727 static void radeon_enc_header_av1(struct radeon_encoder *enc)
728 {
729 enc->tile_config(enc);
730 enc->obu_instructions(enc);
731 enc->encode_params(enc);
732 enc->encode_params_codec_spec(enc);
733 enc->cdf_default_table(enc);
734 }
735
radeon_enc_4_0_init(struct radeon_encoder * enc)736 void radeon_enc_4_0_init(struct radeon_encoder *enc)
737 {
738 radeon_enc_3_0_init(enc);
739
740 enc->session_init = radeon_enc_session_init;
741 enc->ctx = radeon_enc_ctx;
742 enc->mq_begin = enc->begin;
743 enc->mq_encode = enc->encode;
744 enc->mq_destroy = enc->destroy;
745 enc->begin = radeon_enc_sq_begin;
746 enc->encode = radeon_enc_sq_encode;
747 enc->destroy = radeon_enc_sq_destroy;
748 enc->op_preset = radeon_enc_op_preset;
749
750 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_AV1) {
751 /* begin function need to set these functions to dummy */
752 enc->slice_control = radeon_enc_dummy;
753 enc->deblocking_filter = radeon_enc_dummy;
754 enc->tile_config = radeon_enc_dummy;
755 enc->encode_params_codec_spec = radeon_enc_dummy;
756 enc->spec_misc = radeon_enc_spec_misc_av1;
757 enc->encode_headers = radeon_enc_header_av1;
758 enc->obu_instructions = radeon_enc_obu_instruction;
759 enc->cdf_default_table = radeon_enc_cdf_default_table;
760 enc->encode_params = radeon_enc_av1_encode_params;
761 }
762
763 enc->enc_pic.session_info.interface_version =
764 ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
765 (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
766 }
767