1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * SPDX-License-Identifier: MIT
9 */
10
11 #ifndef RADV_PIPELINE_GRAPHICS_H
12 #define RADV_PIPELINE_GRAPHICS_H
13
14 #include "sid.h"
15
16 #include "radv_descriptor_set.h"
17 #include "radv_pipeline.h"
18 #include "radv_shader.h"
19
20 #include "vk_graphics_state.h"
21 #include "vk_meta.h"
22
23 #define VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO_RADV (VkStructureType)2000290001
24
25 #define VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO_RADV_cast VkGraphicsPipelineCreateInfoRADV
26
27 typedef struct VkGraphicsPipelineCreateInfoRADV {
28 VkStructureType sType;
29 const void *pNext;
30 VkBool32 db_depth_clear;
31 VkBool32 db_stencil_clear;
32 VkBool32 depth_compress_disable;
33 VkBool32 stencil_compress_disable;
34 uint32_t custom_blend_mode;
35 } VkGraphicsPipelineCreateInfoRADV;
36
37 struct radv_sample_locations_state {
38 VkSampleCountFlagBits per_pixel;
39 VkExtent2D grid_size;
40 uint32_t count;
41 VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
42 };
43
44 struct radv_dynamic_state {
45 struct vk_dynamic_graphics_state vk;
46
47 /**
48 * Bitmask of (1ull << VK_DYNAMIC_STATE_*).
49 * Defines the set of saved dynamic state.
50 */
51 uint64_t mask;
52
53 struct {
54 struct {
55 float scale[3];
56 float translate[3];
57 } xform[MAX_VIEWPORTS];
58 } hw_vp;
59
60 struct radv_sample_locations_state sample_location;
61
62 VkImageAspectFlags feedback_loop_aspects;
63 };
64
65 struct radv_multisample_state {
66 bool sample_shading_enable;
67 float min_sample_shading;
68 };
69
70 struct radv_ia_multi_vgt_param_helpers {
71 uint32_t base;
72 bool partial_es_wave;
73 bool ia_switch_on_eoi;
74 bool partial_vs_wave;
75 };
76
77 struct radv_sqtt_shaders_reloc {
78 struct radeon_winsys_bo *bo;
79 union radv_shader_arena_block *alloc;
80 uint64_t va[MESA_VULKAN_SHADER_STAGES];
81 };
82
83 struct radv_graphics_pipeline {
84 struct radv_pipeline base;
85
86 bool uses_drawid;
87 bool uses_baseinstance;
88
89 /* Whether the pipeline forces per-vertex VRS (GFX10.3+). */
90 bool force_vrs_per_vertex;
91
92 /* Whether the pipeline uses NGG (GFX10+). */
93 bool is_ngg;
94 bool has_ngg_culling;
95
96 uint8_t vtx_emit_num;
97
98 uint32_t vtx_base_sgpr;
99 uint64_t dynamic_states;
100 uint64_t needed_dynamic_state;
101
102 VkShaderStageFlags active_stages;
103
104 struct radv_dynamic_state dynamic_state;
105
106 struct radv_vertex_input_state vertex_input;
107
108 struct radv_multisample_state ms;
109 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
110 uint32_t binding_stride[MAX_VBS];
111 uint32_t db_render_control;
112
113 /* Last pre-PS API stage */
114 gl_shader_stage last_vgt_api_stage;
115
116 unsigned rast_prim;
117
118
119 /* Custom blend mode for internal operations. */
120 unsigned custom_blend_mode;
121
122 /* Whether the pipeline uses out-of-order rasterization. */
123 bool uses_out_of_order_rast;
124
125 /* Whether the pipeline uses VRS. */
126 bool uses_vrs;
127
128 /* Whether the pipeline uses a VRS attachment. */
129 bool uses_vrs_attachment;
130
131 /* Whether the pipeline uses VRS coarse shading internally. */
132 bool uses_vrs_coarse_shading;
133
134 /* For relocation of shaders with RGP. */
135 struct radv_sqtt_shaders_reloc *sqtt_shaders_reloc;
136
137 /* Whether the pipeline imported binaries. */
138 bool has_pipeline_binaries;
139 };
140
141 RADV_DECL_PIPELINE_DOWNCAST(graphics, RADV_PIPELINE_GRAPHICS)
142
143 struct radv_retained_shaders {
144 struct {
145 void *serialized_nir;
146 size_t serialized_nir_size;
147 unsigned char shader_sha1[SHA1_DIGEST_LENGTH];
148 struct radv_shader_stage_key key;
149 } stages[MESA_VULKAN_SHADER_STAGES];
150 };
151
152 struct radv_graphics_lib_pipeline {
153 struct radv_graphics_pipeline base;
154
155 struct vk_graphics_pipeline_state graphics_state;
156
157 /* For vk_graphics_pipeline_state */
158 void *state_data;
159
160 struct radv_pipeline_layout layout;
161
162 VkGraphicsPipelineLibraryFlagsEXT lib_flags;
163
164 struct radv_retained_shaders retained_shaders;
165
166 void *mem_ctx;
167
168 unsigned stage_count;
169 VkPipelineShaderStageCreateInfo *stages;
170 struct radv_shader_stage_key stage_keys[MESA_VULKAN_SHADER_STAGES];
171 };
172
RADV_DECL_PIPELINE_DOWNCAST(graphics_lib,RADV_PIPELINE_GRAPHICS_LIB)173 RADV_DECL_PIPELINE_DOWNCAST(graphics_lib, RADV_PIPELINE_GRAPHICS_LIB)
174
175 static inline bool
176 radv_pipeline_has_stage(const struct radv_graphics_pipeline *pipeline, gl_shader_stage stage)
177 {
178 return pipeline->base.shaders[stage];
179 }
180
181 static inline uint32_t
radv_conv_prim_to_gs_out(uint32_t topology,bool is_ngg)182 radv_conv_prim_to_gs_out(uint32_t topology, bool is_ngg)
183 {
184 switch (topology) {
185 case V_008958_DI_PT_POINTLIST:
186 case V_008958_DI_PT_PATCH:
187 return V_028A6C_POINTLIST;
188 case V_008958_DI_PT_LINELIST:
189 case V_008958_DI_PT_LINESTRIP:
190 case V_008958_DI_PT_LINELIST_ADJ:
191 case V_008958_DI_PT_LINESTRIP_ADJ:
192 return V_028A6C_LINESTRIP;
193 case V_008958_DI_PT_TRILIST:
194 case V_008958_DI_PT_TRISTRIP:
195 case V_008958_DI_PT_TRIFAN:
196 case V_008958_DI_PT_TRILIST_ADJ:
197 case V_008958_DI_PT_TRISTRIP_ADJ:
198 return V_028A6C_TRISTRIP;
199 case V_008958_DI_PT_RECTLIST:
200 return is_ngg ? V_028A6C_RECTLIST : V_028A6C_TRISTRIP;
201 default:
202 assert(0);
203 return 0;
204 }
205 }
206
207 static inline uint32_t
radv_conv_gl_prim_to_gs_out(unsigned gl_prim)208 radv_conv_gl_prim_to_gs_out(unsigned gl_prim)
209 {
210 switch (gl_prim) {
211 case MESA_PRIM_POINTS:
212 return V_028A6C_POINTLIST;
213 case MESA_PRIM_LINES:
214 case MESA_PRIM_LINE_STRIP:
215 case MESA_PRIM_LINES_ADJACENCY:
216 return V_028A6C_LINESTRIP;
217
218 case MESA_PRIM_TRIANGLES:
219 case MESA_PRIM_TRIANGLE_STRIP_ADJACENCY:
220 case MESA_PRIM_TRIANGLE_STRIP:
221 case MESA_PRIM_QUADS:
222 return V_028A6C_TRISTRIP;
223 default:
224 assert(0);
225 return 0;
226 }
227 }
228
229 static inline uint32_t
radv_translate_prim(unsigned topology)230 radv_translate_prim(unsigned topology)
231 {
232 switch (topology) {
233 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
234 return V_008958_DI_PT_POINTLIST;
235 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
236 return V_008958_DI_PT_LINELIST;
237 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
238 return V_008958_DI_PT_LINESTRIP;
239 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
240 return V_008958_DI_PT_TRILIST;
241 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
242 return V_008958_DI_PT_TRISTRIP;
243 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
244 return V_008958_DI_PT_TRIFAN;
245 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
246 return V_008958_DI_PT_LINELIST_ADJ;
247 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
248 return V_008958_DI_PT_LINESTRIP_ADJ;
249 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
250 return V_008958_DI_PT_TRILIST_ADJ;
251 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
252 return V_008958_DI_PT_TRISTRIP_ADJ;
253 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
254 return V_008958_DI_PT_PATCH;
255 case VK_PRIMITIVE_TOPOLOGY_META_RECT_LIST_MESA:
256 return V_008958_DI_PT_RECTLIST;
257 default:
258 unreachable("unhandled primitive type");
259 }
260 }
261
262 static inline bool
radv_prim_is_points_or_lines(unsigned topology)263 radv_prim_is_points_or_lines(unsigned topology)
264 {
265 switch (topology) {
266 case V_008958_DI_PT_POINTLIST:
267 case V_008958_DI_PT_LINELIST:
268 case V_008958_DI_PT_LINESTRIP:
269 case V_008958_DI_PT_LINELIST_ADJ:
270 case V_008958_DI_PT_LINESTRIP_ADJ:
271 return true;
272 default:
273 return false;
274 }
275 }
276
277 static inline bool
radv_rast_prim_is_point(unsigned rast_prim)278 radv_rast_prim_is_point(unsigned rast_prim)
279 {
280 return rast_prim == V_028A6C_POINTLIST;
281 }
282
283 static inline bool
radv_rast_prim_is_line(unsigned rast_prim)284 radv_rast_prim_is_line(unsigned rast_prim)
285 {
286 return rast_prim == V_028A6C_LINESTRIP;
287 }
288
289 static inline bool
radv_rast_prim_is_points_or_lines(unsigned rast_prim)290 radv_rast_prim_is_points_or_lines(unsigned rast_prim)
291 {
292 return radv_rast_prim_is_point(rast_prim) || radv_rast_prim_is_line(rast_prim);
293 }
294
295 static inline bool
radv_polygon_mode_is_point(unsigned polygon_mode)296 radv_polygon_mode_is_point(unsigned polygon_mode)
297 {
298 return polygon_mode == V_028814_X_DRAW_POINTS;
299 }
300
301 static inline bool
radv_polygon_mode_is_line(unsigned polygon_mode)302 radv_polygon_mode_is_line(unsigned polygon_mode)
303 {
304 return polygon_mode == V_028814_X_DRAW_LINES;
305 }
306
307 static inline bool
radv_polygon_mode_is_points_or_lines(unsigned polygon_mode)308 radv_polygon_mode_is_points_or_lines(unsigned polygon_mode)
309 {
310 return radv_polygon_mode_is_point(polygon_mode) || radv_polygon_mode_is_line(polygon_mode);
311 }
312
313 static inline bool
radv_primitive_topology_is_line_list(unsigned primitive_topology)314 radv_primitive_topology_is_line_list(unsigned primitive_topology)
315 {
316 return primitive_topology == V_008958_DI_PT_LINELIST || primitive_topology == V_008958_DI_PT_LINELIST_ADJ;
317 }
318
319 static inline unsigned
radv_get_num_vertices_per_prim(const struct radv_graphics_state_key * gfx_state)320 radv_get_num_vertices_per_prim(const struct radv_graphics_state_key *gfx_state)
321 {
322 if (gfx_state->ia.topology == V_008958_DI_PT_NONE) {
323 /* When the topology is unknown (with graphics pipeline library), return the maximum number of
324 * vertices per primitives for VS. This is used to lower NGG (the HW will ignore the extra
325 * bits for points/lines) and also to enable NGG culling unconditionally (it will be disabled
326 * dynamically for points/lines).
327 */
328 return 3;
329 } else {
330 /* Need to add 1, because: V_028A6C_POINTLIST=0, V_028A6C_LINESTRIP=1, V_028A6C_TRISTRIP=2, etc. */
331 return radv_conv_prim_to_gs_out(gfx_state->ia.topology, false) + 1;
332 }
333 }
334
335 static inline uint32_t
radv_translate_fill(VkPolygonMode func)336 radv_translate_fill(VkPolygonMode func)
337 {
338 switch (func) {
339 case VK_POLYGON_MODE_FILL:
340 return V_028814_X_DRAW_TRIANGLES;
341 case VK_POLYGON_MODE_LINE:
342 return V_028814_X_DRAW_LINES;
343 case VK_POLYGON_MODE_POINT:
344 return V_028814_X_DRAW_POINTS;
345 default:
346 assert(0);
347 return V_028814_X_DRAW_POINTS;
348 }
349 }
350
351 static inline uint32_t
radv_translate_stencil_op(VkStencilOp op)352 radv_translate_stencil_op(VkStencilOp op)
353 {
354 switch (op) {
355 case VK_STENCIL_OP_KEEP:
356 return V_02842C_STENCIL_KEEP;
357 case VK_STENCIL_OP_ZERO:
358 return V_02842C_STENCIL_ZERO;
359 case VK_STENCIL_OP_REPLACE:
360 return V_02842C_STENCIL_REPLACE_TEST;
361 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
362 return V_02842C_STENCIL_ADD_CLAMP;
363 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
364 return V_02842C_STENCIL_SUB_CLAMP;
365 case VK_STENCIL_OP_INVERT:
366 return V_02842C_STENCIL_INVERT;
367 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
368 return V_02842C_STENCIL_ADD_WRAP;
369 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
370 return V_02842C_STENCIL_SUB_WRAP;
371 default:
372 return 0;
373 }
374 }
375
376 static inline uint32_t
radv_translate_blend_logic_op(VkLogicOp op)377 radv_translate_blend_logic_op(VkLogicOp op)
378 {
379 switch (op) {
380 case VK_LOGIC_OP_CLEAR:
381 return V_028808_ROP3_CLEAR;
382 case VK_LOGIC_OP_AND:
383 return V_028808_ROP3_AND;
384 case VK_LOGIC_OP_AND_REVERSE:
385 return V_028808_ROP3_AND_REVERSE;
386 case VK_LOGIC_OP_COPY:
387 return V_028808_ROP3_COPY;
388 case VK_LOGIC_OP_AND_INVERTED:
389 return V_028808_ROP3_AND_INVERTED;
390 case VK_LOGIC_OP_NO_OP:
391 return V_028808_ROP3_NO_OP;
392 case VK_LOGIC_OP_XOR:
393 return V_028808_ROP3_XOR;
394 case VK_LOGIC_OP_OR:
395 return V_028808_ROP3_OR;
396 case VK_LOGIC_OP_NOR:
397 return V_028808_ROP3_NOR;
398 case VK_LOGIC_OP_EQUIVALENT:
399 return V_028808_ROP3_EQUIVALENT;
400 case VK_LOGIC_OP_INVERT:
401 return V_028808_ROP3_INVERT;
402 case VK_LOGIC_OP_OR_REVERSE:
403 return V_028808_ROP3_OR_REVERSE;
404 case VK_LOGIC_OP_COPY_INVERTED:
405 return V_028808_ROP3_COPY_INVERTED;
406 case VK_LOGIC_OP_OR_INVERTED:
407 return V_028808_ROP3_OR_INVERTED;
408 case VK_LOGIC_OP_NAND:
409 return V_028808_ROP3_NAND;
410 case VK_LOGIC_OP_SET:
411 return V_028808_ROP3_SET;
412 default:
413 unreachable("Unhandled logic op");
414 }
415 }
416
417 static inline uint32_t
radv_translate_blend_function(VkBlendOp op)418 radv_translate_blend_function(VkBlendOp op)
419 {
420 switch (op) {
421 case VK_BLEND_OP_ADD:
422 return V_028780_COMB_DST_PLUS_SRC;
423 case VK_BLEND_OP_SUBTRACT:
424 return V_028780_COMB_SRC_MINUS_DST;
425 case VK_BLEND_OP_REVERSE_SUBTRACT:
426 return V_028780_COMB_DST_MINUS_SRC;
427 case VK_BLEND_OP_MIN:
428 return V_028780_COMB_MIN_DST_SRC;
429 case VK_BLEND_OP_MAX:
430 return V_028780_COMB_MAX_DST_SRC;
431 default:
432 return 0;
433 }
434 }
435
436 static inline uint32_t
radv_translate_blend_factor(enum amd_gfx_level gfx_level,VkBlendFactor factor)437 radv_translate_blend_factor(enum amd_gfx_level gfx_level, VkBlendFactor factor)
438 {
439 switch (factor) {
440 case VK_BLEND_FACTOR_ZERO:
441 return V_028780_BLEND_ZERO;
442 case VK_BLEND_FACTOR_ONE:
443 return V_028780_BLEND_ONE;
444 case VK_BLEND_FACTOR_SRC_COLOR:
445 return V_028780_BLEND_SRC_COLOR;
446 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
447 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
448 case VK_BLEND_FACTOR_DST_COLOR:
449 return V_028780_BLEND_DST_COLOR;
450 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
451 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
452 case VK_BLEND_FACTOR_SRC_ALPHA:
453 return V_028780_BLEND_SRC_ALPHA;
454 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
455 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
456 case VK_BLEND_FACTOR_DST_ALPHA:
457 return V_028780_BLEND_DST_ALPHA;
458 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
459 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
460 case VK_BLEND_FACTOR_CONSTANT_COLOR:
461 return gfx_level >= GFX11 ? V_028780_BLEND_CONSTANT_COLOR_GFX11 : V_028780_BLEND_CONSTANT_COLOR_GFX6;
462 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
463 return gfx_level >= GFX11 ? V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR_GFX11
464 : V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR_GFX6;
465 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
466 return gfx_level >= GFX11 ? V_028780_BLEND_CONSTANT_ALPHA_GFX11 : V_028780_BLEND_CONSTANT_ALPHA_GFX6;
467 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
468 return gfx_level >= GFX11 ? V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA_GFX11
469 : V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA_GFX6;
470 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
471 return V_028780_BLEND_SRC_ALPHA_SATURATE;
472 case VK_BLEND_FACTOR_SRC1_COLOR:
473 return gfx_level >= GFX11 ? V_028780_BLEND_SRC1_COLOR_GFX11 : V_028780_BLEND_SRC1_COLOR_GFX6;
474 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
475 return gfx_level >= GFX11 ? V_028780_BLEND_INV_SRC1_COLOR_GFX11 : V_028780_BLEND_INV_SRC1_COLOR_GFX6;
476 case VK_BLEND_FACTOR_SRC1_ALPHA:
477 return gfx_level >= GFX11 ? V_028780_BLEND_SRC1_ALPHA_GFX11 : V_028780_BLEND_SRC1_ALPHA_GFX6;
478 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
479 return gfx_level >= GFX11 ? V_028780_BLEND_INV_SRC1_ALPHA_GFX11 : V_028780_BLEND_INV_SRC1_ALPHA_GFX6;
480 default:
481 return 0;
482 }
483 }
484
485 static inline uint32_t
radv_translate_blend_opt_factor(VkBlendFactor factor,bool is_alpha)486 radv_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
487 {
488 switch (factor) {
489 case VK_BLEND_FACTOR_ZERO:
490 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
491 case VK_BLEND_FACTOR_ONE:
492 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
493 case VK_BLEND_FACTOR_SRC_COLOR:
494 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
495 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
496 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
497 case VK_BLEND_FACTOR_SRC_ALPHA:
498 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
499 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
500 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
501 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
502 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
503 default:
504 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
505 }
506 }
507
508 static inline uint32_t
radv_translate_blend_opt_function(VkBlendOp op)509 radv_translate_blend_opt_function(VkBlendOp op)
510 {
511 switch (op) {
512 case VK_BLEND_OP_ADD:
513 return V_028760_OPT_COMB_ADD;
514 case VK_BLEND_OP_SUBTRACT:
515 return V_028760_OPT_COMB_SUBTRACT;
516 case VK_BLEND_OP_REVERSE_SUBTRACT:
517 return V_028760_OPT_COMB_REVSUBTRACT;
518 case VK_BLEND_OP_MIN:
519 return V_028760_OPT_COMB_MIN;
520 case VK_BLEND_OP_MAX:
521 return V_028760_OPT_COMB_MAX;
522 default:
523 return V_028760_OPT_COMB_BLEND_DISABLED;
524 }
525 }
526
527 static inline bool
radv_blend_factor_uses_dst(VkBlendFactor factor)528 radv_blend_factor_uses_dst(VkBlendFactor factor)
529 {
530 return factor == VK_BLEND_FACTOR_DST_COLOR || factor == VK_BLEND_FACTOR_DST_ALPHA ||
531 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE || factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
532 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
533 }
534
535 static inline bool
radv_is_dual_src(VkBlendFactor factor)536 radv_is_dual_src(VkBlendFactor factor)
537 {
538 switch (factor) {
539 case VK_BLEND_FACTOR_SRC1_COLOR:
540 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
541 case VK_BLEND_FACTOR_SRC1_ALPHA:
542 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
543 return true;
544 default:
545 return false;
546 }
547 }
548
549 static ALWAYS_INLINE bool
radv_can_enable_dual_src(const struct vk_color_blend_attachment_state * att)550 radv_can_enable_dual_src(const struct vk_color_blend_attachment_state *att)
551 {
552 VkBlendOp eqRGB = att->color_blend_op;
553 VkBlendFactor srcRGB = att->src_color_blend_factor;
554 VkBlendFactor dstRGB = att->dst_color_blend_factor;
555 VkBlendOp eqA = att->alpha_blend_op;
556 VkBlendFactor srcA = att->src_alpha_blend_factor;
557 VkBlendFactor dstA = att->dst_alpha_blend_factor;
558 bool eqRGB_minmax = eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX;
559 bool eqA_minmax = eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX;
560
561 if (!eqRGB_minmax && (radv_is_dual_src(srcRGB) || radv_is_dual_src(dstRGB)))
562 return true;
563 if (!eqA_minmax && (radv_is_dual_src(srcA) || radv_is_dual_src(dstA)))
564 return true;
565 return false;
566 }
567
568 static inline void
radv_normalize_blend_factor(VkBlendOp op,VkBlendFactor * src_factor,VkBlendFactor * dst_factor)569 radv_normalize_blend_factor(VkBlendOp op, VkBlendFactor *src_factor, VkBlendFactor *dst_factor)
570 {
571 if (op == VK_BLEND_OP_MIN || op == VK_BLEND_OP_MAX) {
572 *src_factor = VK_BLEND_FACTOR_ONE;
573 *dst_factor = VK_BLEND_FACTOR_ONE;
574 }
575 }
576
577 void radv_blend_remove_dst(VkBlendOp *func, VkBlendFactor *src_factor, VkBlendFactor *dst_factor,
578 VkBlendFactor expected_dst, VkBlendFactor replacement_src);
579
580 unsigned radv_format_meta_fs_key(struct radv_device *device, VkFormat format);
581
582 struct radv_ia_multi_vgt_param_helpers radv_compute_ia_multi_vgt_param(const struct radv_device *device,
583 struct radv_shader *const *shaders);
584
585 void radv_get_viewport_xform(const VkViewport *viewport, float scale[3], float translate[3]);
586
587 struct radv_shader *radv_get_shader(struct radv_shader *const *shaders, gl_shader_stage stage);
588
589 struct radv_ps_epilog_state {
590 uint8_t color_attachment_count;
591 VkFormat color_attachment_formats[MAX_RTS];
592 uint8_t color_attachment_mappings[MAX_RTS];
593
594 uint32_t color_write_mask;
595 uint32_t color_blend_enable;
596
597 uint32_t colors_written;
598 bool mrt0_is_dual_src;
599 bool export_depth;
600 bool export_stencil;
601 bool export_sample_mask;
602 bool alpha_to_coverage_via_mrtz;
603 bool alpha_to_one;
604 uint8_t need_src_alpha;
605 };
606
607 struct radv_ps_epilog_key radv_generate_ps_epilog_key(const struct radv_device *device,
608 const struct radv_ps_epilog_state *state);
609
610 void radv_graphics_shaders_compile(struct radv_device *device, struct vk_pipeline_cache *cache,
611 struct radv_shader_stage *stages, const struct radv_graphics_state_key *gfx_state,
612 bool keep_executable_info, bool keep_statistic_info, bool is_internal,
613 bool skip_shaders_cache, struct radv_retained_shaders *retained_shaders,
614 bool noop_fs, struct radv_shader **shaders, struct radv_shader_binary **binaries,
615 struct radv_shader **gs_copy_shader, struct radv_shader_binary **gs_copy_binary);
616
617 struct radv_vgt_shader_key {
618 uint8_t tess : 1;
619 uint8_t gs : 1;
620 uint8_t mesh_scratch_ring : 1;
621 uint8_t mesh : 1;
622 uint8_t ngg_passthrough : 1;
623 uint8_t ngg : 1; /* gfx10+ */
624 uint8_t ngg_streamout : 1;
625 uint8_t hs_wave32 : 1;
626 uint8_t gs_wave32 : 1;
627 uint8_t vs_wave32 : 1;
628 };
629
630 struct radv_vgt_shader_key radv_get_vgt_shader_key(const struct radv_device *device, struct radv_shader **shaders,
631 const struct radv_shader *gs_copy_shader);
632
633 uint32_t radv_get_vgt_gs_out(struct radv_shader **shaders, uint32_t primitive_topology, bool is_ngg);
634
635 bool radv_needs_null_export_workaround(const struct radv_device *device, const struct radv_shader *ps,
636 unsigned custom_blend_mode);
637
638 void radv_destroy_graphics_pipeline(struct radv_device *device, struct radv_graphics_pipeline *pipeline);
639
640 void radv_destroy_graphics_lib_pipeline(struct radv_device *device, struct radv_graphics_lib_pipeline *pipeline);
641
642 struct radv_graphics_pipeline_state {
643 struct vk_graphics_pipeline_state vk;
644 void *vk_data;
645
646 bool compilation_required;
647
648 struct radv_shader_stage *stages;
649
650 struct radv_graphics_pipeline_key key;
651
652 struct radv_pipeline_layout layout;
653 };
654
655 void radv_graphics_pipeline_hash(const struct radv_device *device, const struct radv_graphics_pipeline_state *gfx_state,
656 unsigned char *hash);
657
658 VkResult radv_generate_graphics_pipeline_state(struct radv_device *device,
659 const VkGraphicsPipelineCreateInfo *pCreateInfo,
660 struct radv_graphics_pipeline_state *gfx_state);
661
662 void radv_graphics_pipeline_state_finish(struct radv_device *device, struct radv_graphics_pipeline_state *gfx_state);
663
664 #endif /* RADV_PIPELINE_GRAPHICS_H */
665