1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * SPDX-License-Identifier: MIT
9 */
10
11 #ifndef RADV_QUEUE_H
12 #define RADV_QUEUE_H
13
14 #include "vk_queue.h"
15
16 #include "radv_radeon_winsys.h"
17
18 struct radv_physical_device;
19 struct radv_device;
20
21 struct radv_queue_ring_info {
22 uint32_t scratch_size_per_wave;
23 uint32_t scratch_waves;
24 uint32_t compute_scratch_size_per_wave;
25 uint32_t compute_scratch_waves;
26 uint32_t esgs_ring_size;
27 uint32_t gsvs_ring_size;
28 bool tess_rings;
29 bool task_rings;
30 bool mesh_scratch_ring;
31 bool ge_rings;
32 bool gds;
33 bool gds_oa;
34 bool sample_positions;
35 };
36
37 enum radv_queue_family {
38 RADV_QUEUE_GENERAL,
39 RADV_QUEUE_COMPUTE,
40 RADV_QUEUE_TRANSFER,
41 RADV_QUEUE_SPARSE,
42 RADV_QUEUE_VIDEO_DEC,
43 RADV_QUEUE_VIDEO_ENC,
44 RADV_MAX_QUEUE_FAMILIES,
45 RADV_QUEUE_FOREIGN = RADV_MAX_QUEUE_FAMILIES,
46 RADV_QUEUE_IGNORED,
47 };
48
49 struct radv_queue_state {
50 enum radv_queue_family qf;
51 struct radv_queue_ring_info ring_info;
52
53 struct radeon_winsys_bo *scratch_bo;
54 struct radeon_winsys_bo *descriptor_bo;
55 struct radeon_winsys_bo *compute_scratch_bo;
56 struct radeon_winsys_bo *esgs_ring_bo;
57 struct radeon_winsys_bo *gsvs_ring_bo;
58 struct radeon_winsys_bo *tess_rings_bo;
59 struct radeon_winsys_bo *task_rings_bo;
60 struct radeon_winsys_bo *mesh_scratch_ring_bo;
61 struct radeon_winsys_bo *ge_rings_bo;
62 struct radeon_winsys_bo *gds_bo;
63 struct radeon_winsys_bo *gds_oa_bo;
64
65 struct radeon_cmdbuf *initial_preamble_cs;
66 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
67 struct radeon_cmdbuf *continue_preamble_cs;
68 struct radeon_cmdbuf *gang_wait_preamble_cs;
69 struct radeon_cmdbuf *gang_wait_postamble_cs;
70 struct radeon_cmdbuf *flush_postamble_cs; /* GFX6 only */
71
72 /* the uses_shadow_regs here will be set only for general queue */
73 bool uses_shadow_regs;
74 /* register state is saved in shadowed_regs buffer */
75 struct radeon_winsys_bo *shadowed_regs;
76 /* shadow regs preamble ib. This will be the first preamble ib.
77 * This ib has the packets to start register shadowing.
78 */
79 struct radeon_winsys_bo *shadow_regs_ib;
80 uint32_t shadow_regs_ib_size_dw;
81 };
82
83 struct radv_queue {
84 struct vk_queue vk;
85 struct radeon_winsys_ctx *hw_ctx;
86 enum radeon_ctx_priority priority;
87 struct radv_queue_state state;
88 struct radv_queue_state *follower_state;
89 struct radeon_winsys_bo *gang_sem_bo;
90
91 uint64_t last_shader_upload_seq;
92 bool sqtt_present;
93 };
94
95 VK_DEFINE_HANDLE_CASTS(radv_queue, vk.base, VkQueue, VK_OBJECT_TYPE_QUEUE)
96
97 static inline struct radv_device *
radv_queue_device(const struct radv_queue * queue)98 radv_queue_device(const struct radv_queue *queue)
99 {
100 return (struct radv_device *)queue->vk.base.device;
101 }
102
103 int radv_queue_init(struct radv_device *device, struct radv_queue *queue, int idx,
104 const VkDeviceQueueCreateInfo *create_info,
105 const VkDeviceQueueGlobalPriorityCreateInfo *global_priority);
106
107 void radv_queue_finish(struct radv_queue *queue);
108
109 enum radeon_ctx_priority radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfo *pObj);
110
111 void radv_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs);
112
113 bool radv_queue_internal_submit(struct radv_queue *queue, struct radeon_cmdbuf *cs);
114
115 enum amd_ip_type radv_queue_ring(const struct radv_queue *queue);
116
117 enum amd_ip_type radv_queue_family_to_ring(const struct radv_physical_device *dev, enum radv_queue_family f);
118
119 #endif /* RADV_QUEUE_H */
120