1/* This file contains the definitions and documentation for the 2 Register Transfer Expressions (rtx's) that make up the 3 Register Transfer Language (rtl) used in the Back End of the GNU compiler. 4 Copyright (C) 1987-2013 Free Software Foundation, Inc. 5 6This file is part of GCC. 7 8GCC is free software; you can redistribute it and/or modify it under 9the terms of the GNU General Public License as published by the Free 10Software Foundation; either version 3, or (at your option) any later 11version. 12 13GCC is distributed in the hope that it will be useful, but WITHOUT ANY 14WARRANTY; without even the implied warranty of MERCHANTABILITY or 15FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16for more details. 17 18You should have received a copy of the GNU General Public License 19along with GCC; see the file COPYING3. If not see 20<http://www.gnu.org/licenses/>. */ 21 22 23/* Expression definitions and descriptions for all targets are in this file. 24 Some will not be used for some targets. 25 26 The fields in the cpp macro call "DEF_RTL_EXPR()" 27 are used to create declarations in the C source of the compiler. 28 29 The fields are: 30 31 1. The internal name of the rtx used in the C source. 32 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h". 33 By convention these are in UPPER_CASE. 34 35 2. The name of the rtx in the external ASCII format read by 36 read_rtx(), and printed by print_rtx(). 37 These names are stored in rtx_name[]. 38 By convention these are the internal (field 1) names in lower_case. 39 40 3. The print format, and type of each rtx->u.fld[] (field) in this rtx. 41 These formats are stored in rtx_format[]. 42 The meaning of the formats is documented in front of this array in rtl.c 43 44 4. The class of the rtx. These are stored in rtx_class and are accessed 45 via the GET_RTX_CLASS macro. They are defined as follows: 46 47 RTX_CONST_OBJ 48 an rtx code that can be used to represent a constant object 49 (e.g, CONST_INT) 50 RTX_OBJ 51 an rtx code that can be used to represent an object (e.g, REG, MEM) 52 RTX_COMPARE 53 an rtx code for a comparison (e.g, LT, GT) 54 RTX_COMM_COMPARE 55 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED) 56 RTX_UNARY 57 an rtx code for a unary arithmetic expression (e.g, NEG, NOT) 58 RTX_COMM_ARITH 59 an rtx code for a commutative binary operation (e.g,, PLUS, MULT) 60 RTX_TERNARY 61 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE) 62 RTX_BIN_ARITH 63 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV) 64 RTX_BITFIELD_OPS 65 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT) 66 RTX_INSN 67 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) 68 RTX_MATCH 69 an rtx code for something that matches in insns (e.g, MATCH_DUP) 70 RTX_AUTOINC 71 an rtx code for autoincrement addressing modes (e.g. POST_DEC) 72 RTX_EXTRA 73 everything else 74 75 All of the expressions that appear only in machine descriptions, 76 not in RTL used by the compiler itself, are at the end of the file. */ 77 78/* Unknown, or no such operation; the enumeration constant should have 79 value zero. */ 80DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA) 81 82/* Used in the cselib routines to describe a value. Objects of this 83 kind are only allocated in cselib.c, in an alloc pool instead of in 84 GC memory. The only operand of a VALUE is a cselib_val_struct. 85 var-tracking requires this to have a distinct integral value from 86 DECL codes in trees. */ 87DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ) 88 89/* The RTL generated for a DEBUG_EXPR_DECL. It links back to the 90 DEBUG_EXPR_DECL in the first operand. */ 91DEF_RTL_EXPR(DEBUG_EXPR, "debug_expr", "0", RTX_OBJ) 92 93/* --------------------------------------------------------------------- 94 Expressions used in constructing lists. 95 --------------------------------------------------------------------- */ 96 97/* a linked list of expressions */ 98DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA) 99 100/* a linked list of instructions. 101 The insns are represented in print by their uids. */ 102DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA) 103 104/* SEQUENCE appears in the result of a `gen_...' function 105 for a DEFINE_EXPAND that wants to make several insns. 106 Its elements are the bodies of the insns that should be made. 107 `emit_insn' takes the SEQUENCE apart and makes separate insns. */ 108DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA) 109 110/* Represents a non-global base address. This is only used in alias.c. */ 111DEF_RTL_EXPR(ADDRESS, "address", "i", RTX_EXTRA) 112 113/* ---------------------------------------------------------------------- 114 Expression types used for things in the instruction chain. 115 116 All formats must start with "iuu" to handle the chain. 117 Each insn expression holds an rtl instruction and its semantics 118 during back-end processing. 119 See macros's in "rtl.h" for the meaning of each rtx->u.fld[]. 120 121 ---------------------------------------------------------------------- */ 122 123/* An annotation for variable assignment tracking. */ 124DEF_RTL_EXPR(DEBUG_INSN, "debug_insn", "iuuBeiie", RTX_INSN) 125 126/* An instruction that cannot jump. */ 127DEF_RTL_EXPR(INSN, "insn", "iuuBeiie", RTX_INSN) 128 129/* An instruction that can possibly jump. 130 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */ 131DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBeiie0", RTX_INSN) 132 133/* An instruction that can possibly call a subroutine 134 but which will not change which instruction comes next 135 in the current function. 136 Field ( rtx->u.fld[8] ) is CALL_INSN_FUNCTION_USAGE. 137 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */ 138DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBeiiee", RTX_INSN) 139 140/* A marker that indicates that control will not flow through. */ 141DEF_RTL_EXPR(BARRIER, "barrier", "iuu00000", RTX_EXTRA) 142 143/* Holds a label that is followed by instructions. 144 Operand: 145 4: is used in jump.c for the use-count of the label. 146 5: is used in the sh backend. 147 6: is a number that is unique in the entire compilation. 148 7: is the user-given name of the label, if any. */ 149DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA) 150 151/* Say where in the code a source line starts, for symbol table's sake. 152 Operand: 153 4: note-specific data 154 5: enum insn_note 155 6: unique number if insn_note == note_insn_deleted_label. */ 156DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA) 157 158/* ---------------------------------------------------------------------- 159 Top level constituents of INSN, JUMP_INSN and CALL_INSN. 160 ---------------------------------------------------------------------- */ 161 162/* Conditionally execute code. 163 Operand 0 is the condition that if true, the code is executed. 164 Operand 1 is the code to be executed (typically a SET). 165 166 Semantics are that there are no side effects if the condition 167 is false. This pattern is created automatically by the if_convert 168 pass run after reload or by target-specific splitters. */ 169DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA) 170 171/* Several operations to be done in parallel (perhaps under COND_EXEC). */ 172DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA) 173 174/* A string that is passed through to the assembler as input. 175 One can obviously pass comments through by using the 176 assembler comment syntax. 177 These occur in an insn all by themselves as the PATTERN. 178 They also appear inside an ASM_OPERANDS 179 as a convenient way to hold a string. */ 180DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA) 181 182/* An assembler instruction with operands. 183 1st operand is the instruction template. 184 2nd operand is the constraint for the output. 185 3rd operand is the number of the output this expression refers to. 186 When an insn stores more than one value, a separate ASM_OPERANDS 187 is made for each output; this integer distinguishes them. 188 4th is a vector of values of input operands. 189 5th is a vector of modes and constraints for the input operands. 190 Each element is an ASM_INPUT containing a constraint string 191 and whose mode indicates the mode of the input operand. 192 6th is a vector of labels that may be branched to by the asm. 193 7th is the source line number. */ 194DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEEi", RTX_EXTRA) 195 196/* A machine-specific operation. 197 1st operand is a vector of operands being used by the operation so that 198 any needed reloads can be done. 199 2nd operand is a unique value saying which of a number of machine-specific 200 operations is to be performed. 201 (Note that the vector must be the first operand because of the way that 202 genrecog.c record positions within an insn.) 203 204 UNSPEC can occur all by itself in a PATTERN, as a component of a PARALLEL, 205 or inside an expression. 206 UNSPEC by itself or as a component of a PARALLEL 207 is currently considered not deletable. 208 209 FIXME: Replace all uses of UNSPEC that appears by itself or as a component 210 of a PARALLEL with USE. 211 */ 212DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA) 213 214/* Similar, but a volatile operation and one which may trap. */ 215DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA) 216 217/* Vector of addresses, stored as full words. */ 218/* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */ 219DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA) 220 221/* Vector of address differences X0 - BASE, X1 - BASE, ... 222 First operand is BASE; the vector contains the X's. 223 The machine mode of this rtx says how much space to leave 224 for each difference and is adjusted by branch shortening if 225 CASE_VECTOR_SHORTEN_MODE is defined. 226 The third and fourth operands store the target labels with the 227 minimum and maximum addresses respectively. 228 The fifth operand stores flags for use by branch shortening. 229 Set at the start of shorten_branches: 230 min_align: the minimum alignment for any of the target labels. 231 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC. 232 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC. 233 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC. 234 min_after_base: true iff minimum address target label is after BASE. 235 max_after_base: true iff maximum address target label is after BASE. 236 Set by the actual branch shortening process: 237 offset_unsigned: true iff offsets have to be treated as unsigned. 238 scale: scaling that is necessary to make offsets fit into the mode. 239 240 The third, fourth and fifth operands are only valid when 241 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing 242 compilation. */ 243 244DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA) 245 246/* Memory prefetch, with attributes supported on some targets. 247 Operand 1 is the address of the memory to fetch. 248 Operand 2 is 1 for a write access, 0 otherwise. 249 Operand 3 is the level of temporal locality; 0 means there is no 250 temporal locality and 1, 2, and 3 are for increasing levels of temporal 251 locality. 252 253 The attributes specified by operands 2 and 3 are ignored for targets 254 whose prefetch instructions do not support them. */ 255DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA) 256 257/* ---------------------------------------------------------------------- 258 At the top level of an instruction (perhaps under PARALLEL). 259 ---------------------------------------------------------------------- */ 260 261/* Assignment. 262 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to. 263 Operand 2 is the value stored there. 264 ALL assignment must use SET. 265 Instructions that do multiple assignments must use multiple SET, 266 under PARALLEL. */ 267DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA) 268 269/* Indicate something is used in a way that we don't want to explain. 270 For example, subroutine calls will use the register 271 in which the static chain is passed. 272 273 USE can not appear as an operand of other rtx except for PARALLEL. 274 USE is not deletable, as it indicates that the operand 275 is used in some unknown way. */ 276DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA) 277 278/* Indicate something is clobbered in a way that we don't want to explain. 279 For example, subroutine calls will clobber some physical registers 280 (the ones that are by convention not saved). 281 282 CLOBBER can not appear as an operand of other rtx except for PARALLEL. 283 CLOBBER of a hard register appearing by itself (not within PARALLEL) 284 is considered undeletable before reload. */ 285DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA) 286 287/* Call a subroutine. 288 Operand 1 is the address to call. 289 Operand 2 is the number of arguments. */ 290 291DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA) 292 293/* Return from a subroutine. */ 294 295DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA) 296 297/* Like RETURN, but truly represents only a function return, while 298 RETURN may represent an insn that also performs other functions 299 of the function epilogue. Like RETURN, this may also occur in 300 conditional jumps. */ 301DEF_RTL_EXPR(SIMPLE_RETURN, "simple_return", "", RTX_EXTRA) 302 303/* Special for EH return from subroutine. */ 304 305DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA) 306 307/* Conditional trap. 308 Operand 1 is the condition. 309 Operand 2 is the trap code. 310 For an unconditional trap, make the condition (const_int 1). */ 311DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA) 312 313/* ---------------------------------------------------------------------- 314 Primitive values for use in expressions. 315 ---------------------------------------------------------------------- */ 316 317/* numeric integer constant */ 318DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ) 319 320/* fixed-point constant */ 321DEF_RTL_EXPR(CONST_FIXED, "const_fixed", "www", RTX_CONST_OBJ) 322 323/* numeric floating point or integer constant. If the mode is 324 VOIDmode it is an int otherwise it has a floating point mode and a 325 floating point value. Operands hold the value. They are all 'w' 326 and there may be from 2 to 6; see real.h. */ 327DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ) 328 329/* Describes a vector constant. */ 330DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ) 331 332/* String constant. Used for attributes in machine descriptions and 333 for special cases in DWARF2 debug output. NOT used for source- 334 language string constants. */ 335DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ) 336 337/* This is used to encapsulate an expression whose value is constant 338 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be 339 recognized as a constant operand rather than by arithmetic instructions. */ 340 341DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ) 342 343/* program counter. Ordinary jumps are represented 344 by a SET whose first operand is (PC). */ 345DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ) 346 347/* A register. The "operand" is the register number, accessed with 348 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER 349 than a hardware register is being referred to. The second operand 350 holds the original register number - this will be different for a 351 pseudo register that got turned into a hard register. The third 352 operand points to a reg_attrs structure. 353 This rtx needs to have as many (or more) fields as a MEM, since we 354 can change REG rtx's into MEMs during reload. */ 355DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ) 356 357/* A scratch register. This represents a register used only within a 358 single insn. It will be turned into a REG during register allocation 359 or reload unless the constraint indicates that the register won't be 360 needed, in which case it can remain a SCRATCH. This code is 361 marked as having one operand so it can be turned into a REG. */ 362DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ) 363 364/* A reference to a part of another value. The first operand is the 365 complete value and the second is the byte offset of the selected part. */ 366DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA) 367 368/* This one-argument rtx is used for move instructions 369 that are guaranteed to alter only the low part of a destination. 370 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...)) 371 has an unspecified effect on the high part of REG, 372 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...)) 373 is guaranteed to alter only the bits of REG that are in HImode. 374 375 The actual instruction used is probably the same in both cases, 376 but the register constraints may be tighter when STRICT_LOW_PART 377 is in use. */ 378 379DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA) 380 381/* (CONCAT a b) represents the virtual concatenation of a and b 382 to make a value that has as many bits as a and b put together. 383 This is used for complex values. Normally it appears only 384 in DECL_RTLs and during RTL generation, but not in the insn chain. */ 385DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ) 386 387/* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of 388 all An to make a value. This is an extension of CONCAT to larger 389 number of components. Like CONCAT, it should not appear in the 390 insn chain. Every element of the CONCATN is the same size. */ 391DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ) 392 393/* A memory location; operand is the address. The second operand is the 394 alias set to which this MEM belongs. We use `0' instead of `w' for this 395 field so that the field need not be specified in machine descriptions. */ 396DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ) 397 398/* Reference to an assembler label in the code for this function. 399 The operand is a CODE_LABEL found in the insn chain. */ 400DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ) 401 402/* Reference to a named label: 403 Operand 0: label name 404 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h) 405 Operand 2: tree from which this symbol is derived, or null. 406 This is either a DECL node, or some kind of constant. */ 407DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ) 408 409/* The condition code register is represented, in our imagination, 410 as a register holding a value that can be compared to zero. 411 In fact, the machine has already compared them and recorded the 412 results; but instructions that look at the condition code 413 pretend to be looking at the entire value and comparing it. */ 414DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ) 415 416/* ---------------------------------------------------------------------- 417 Expressions for operators in an rtl pattern 418 ---------------------------------------------------------------------- */ 419 420/* if_then_else. This is used in representing ordinary 421 conditional jump instructions. 422 Operand: 423 0: condition 424 1: then expr 425 2: else expr */ 426DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY) 427 428/* Comparison, produces a condition code result. */ 429DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH) 430 431/* plus */ 432DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH) 433 434/* Operand 0 minus operand 1. */ 435DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH) 436 437/* Minus operand 0. */ 438DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY) 439 440DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH) 441 442/* Multiplication with signed saturation */ 443DEF_RTL_EXPR(SS_MULT, "ss_mult", "ee", RTX_COMM_ARITH) 444/* Multiplication with unsigned saturation */ 445DEF_RTL_EXPR(US_MULT, "us_mult", "ee", RTX_COMM_ARITH) 446 447/* Operand 0 divided by operand 1. */ 448DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH) 449/* Division with signed saturation */ 450DEF_RTL_EXPR(SS_DIV, "ss_div", "ee", RTX_BIN_ARITH) 451/* Division with unsigned saturation */ 452DEF_RTL_EXPR(US_DIV, "us_div", "ee", RTX_BIN_ARITH) 453 454/* Remainder of operand 0 divided by operand 1. */ 455DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH) 456 457/* Unsigned divide and remainder. */ 458DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH) 459DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH) 460 461/* Bitwise operations. */ 462DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH) 463DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH) 464DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH) 465DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY) 466 467/* Operand: 468 0: value to be shifted. 469 1: number of bits. */ 470DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */ 471DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */ 472DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */ 473DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */ 474DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */ 475 476/* Minimum and maximum values of two operands. We need both signed and 477 unsigned forms. (We cannot use MIN for SMIN because it conflicts 478 with a macro of the same name.) The signed variants should be used 479 with floating point. Further, if both operands are zeros, or if either 480 operand is NaN, then it is unspecified which of the two operands is 481 returned as the result. */ 482 483DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH) 484DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH) 485DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH) 486DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH) 487 488/* These unary operations are used to represent incrementation 489 and decrementation as they occur in memory addresses. 490 The amount of increment or decrement are not represented 491 because they can be understood from the machine-mode of the 492 containing MEM. These operations exist in only two cases: 493 1. pushes onto the stack. 494 2. created automatically by the auto-inc-dec pass. */ 495DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC) 496DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC) 497DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC) 498DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC) 499 500/* These binary operations are used to represent generic address 501 side-effects in memory addresses, except for simple incrementation 502 or decrementation which use the above operations. They are 503 created automatically by the life_analysis pass in flow.c. 504 The first operand is a REG which is used as the address. 505 The second operand is an expression that is assigned to the 506 register, either before (PRE_MODIFY) or after (POST_MODIFY) 507 evaluating the address. 508 Currently, the compiler can only handle second operands of the 509 form (plus (reg) (reg)) and (plus (reg) (const_int)), where 510 the first operand of the PLUS has to be the same register as 511 the first operand of the *_MODIFY. */ 512DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC) 513DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC) 514 515/* Comparison operations. The ordered comparisons exist in two 516 flavors, signed and unsigned. */ 517DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE) 518DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE) 519DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE) 520DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE) 521DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE) 522DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE) 523DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE) 524DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE) 525DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE) 526DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE) 527 528/* Additional floating point unordered comparison flavors. */ 529DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE) 530DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE) 531 532/* These are equivalent to unordered or ... */ 533DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE) 534DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE) 535DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE) 536DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE) 537DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE) 538 539/* This is an ordered NE, ie !UNEQ, ie false for NaN. */ 540DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE) 541 542/* Represents the result of sign-extending the sole operand. 543 The machine modes of the operand and of the SIGN_EXTEND expression 544 determine how much sign-extension is going on. */ 545DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY) 546 547/* Similar for zero-extension (such as unsigned short to int). */ 548DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY) 549 550/* Similar but here the operand has a wider mode. */ 551DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY) 552 553/* Similar for extending floating-point values (such as SFmode to DFmode). */ 554DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY) 555DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY) 556 557/* Conversion of fixed point operand to floating point value. */ 558DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY) 559 560/* With fixed-point machine mode: 561 Conversion of floating point operand to fixed point value. 562 Value is defined only when the operand's value is an integer. 563 With floating-point machine mode (and operand with same mode): 564 Operand is rounded toward zero to produce an integer value 565 represented in floating point. */ 566DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY) 567 568/* Conversion of unsigned fixed point operand to floating point value. */ 569DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY) 570 571/* With fixed-point machine mode: 572 Conversion of floating point operand to *unsigned* fixed point value. 573 Value is defined only when the operand's value is an integer. */ 574DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY) 575 576/* Conversions involving fractional fixed-point types without saturation, 577 including: 578 fractional to fractional (of different precision), 579 signed integer to fractional, 580 fractional to signed integer, 581 floating point to fractional, 582 fractional to floating point. 583 NOTE: fractional can be either signed or unsigned for conversions. */ 584DEF_RTL_EXPR(FRACT_CONVERT, "fract_convert", "e", RTX_UNARY) 585 586/* Conversions involving fractional fixed-point types and unsigned integer 587 without saturation, including: 588 unsigned integer to fractional, 589 fractional to unsigned integer. 590 NOTE: fractional can be either signed or unsigned for conversions. */ 591DEF_RTL_EXPR(UNSIGNED_FRACT_CONVERT, "unsigned_fract_convert", "e", RTX_UNARY) 592 593/* Conversions involving fractional fixed-point types with saturation, 594 including: 595 fractional to fractional (of different precision), 596 signed integer to fractional, 597 floating point to fractional. 598 NOTE: fractional can be either signed or unsigned for conversions. */ 599DEF_RTL_EXPR(SAT_FRACT, "sat_fract", "e", RTX_UNARY) 600 601/* Conversions involving fractional fixed-point types and unsigned integer 602 with saturation, including: 603 unsigned integer to fractional. 604 NOTE: fractional can be either signed or unsigned for conversions. */ 605DEF_RTL_EXPR(UNSIGNED_SAT_FRACT, "unsigned_sat_fract", "e", RTX_UNARY) 606 607/* Absolute value */ 608DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY) 609 610/* Square root */ 611DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY) 612 613/* Swap bytes. */ 614DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY) 615 616/* Find first bit that is set. 617 Value is 1 + number of trailing zeros in the arg., 618 or 0 if arg is 0. */ 619DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY) 620 621/* Count number of leading redundant sign bits (number of leading 622 sign bits minus one). */ 623DEF_RTL_EXPR(CLRSB, "clrsb", "e", RTX_UNARY) 624 625/* Count leading zeros. */ 626DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY) 627 628/* Count trailing zeros. */ 629DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY) 630 631/* Population count (number of 1 bits). */ 632DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY) 633 634/* Population parity (number of 1 bits modulo 2). */ 635DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY) 636 637/* Reference to a signed bit-field of specified size and position. 638 Operand 0 is the memory unit (usually SImode or QImode) which 639 contains the field's first bit. Operand 1 is the width, in bits. 640 Operand 2 is the number of bits in the memory unit before the 641 first bit of this field. 642 If BITS_BIG_ENDIAN is defined, the first bit is the msb and 643 operand 2 counts from the msb of the memory unit. 644 Otherwise, the first bit is the lsb and operand 2 counts from 645 the lsb of the memory unit. 646 This kind of expression can not appear as an lvalue in RTL. */ 647DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS) 648 649/* Similar for unsigned bit-field. 650 But note! This kind of expression _can_ appear as an lvalue. */ 651DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS) 652 653/* For RISC machines. These save memory when splitting insns. */ 654 655/* HIGH are the high-order bits of a constant expression. */ 656DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ) 657 658/* LO_SUM is the sum of a register and the low-order bits 659 of a constant expression. */ 660DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ) 661 662/* Describes a merge operation between two vector values. 663 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask 664 that specifies where the parts of the result are taken from. Set bits 665 indicate operand 0, clear bits indicate operand 1. The parts are defined 666 by the mode of the vectors. */ 667DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY) 668 669/* Describes an operation that selects parts of a vector. 670 Operands 0 is the source vector, operand 1 is a PARALLEL that contains 671 a CONST_INT for each of the subparts of the result vector, giving the 672 number of the source subpart that should be stored into it. */ 673DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH) 674 675/* Describes a vector concat operation. Operands 0 and 1 are the source 676 vectors, the result is a vector that is as long as operands 0 and 1 677 combined and is the concatenation of the two source vectors. */ 678DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH) 679 680/* Describes an operation that converts a small vector into a larger one by 681 duplicating the input values. The output vector mode must have the same 682 submodes as the input vector mode, and the number of output parts must be 683 an integer multiple of the number of input parts. */ 684DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY) 685 686/* Addition with signed saturation */ 687DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH) 688 689/* Addition with unsigned saturation */ 690DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH) 691 692/* Operand 0 minus operand 1, with signed saturation. */ 693DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH) 694 695/* Negation with signed saturation. */ 696DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY) 697/* Negation with unsigned saturation. */ 698DEF_RTL_EXPR(US_NEG, "us_neg", "e", RTX_UNARY) 699 700/* Absolute value with signed saturation. */ 701DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY) 702 703/* Shift left with signed saturation. */ 704DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH) 705 706/* Shift left with unsigned saturation. */ 707DEF_RTL_EXPR(US_ASHIFT, "us_ashift", "ee", RTX_BIN_ARITH) 708 709/* Operand 0 minus operand 1, with unsigned saturation. */ 710DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH) 711 712/* Signed saturating truncate. */ 713DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY) 714 715/* Unsigned saturating truncate. */ 716DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY) 717 718/* Floating point multiply/add combined instruction. */ 719DEF_RTL_EXPR(FMA, "fma", "eee", RTX_TERNARY) 720 721/* Information about the variable and its location. */ 722/* Changed 'te' to 'tei'; the 'i' field is for recording 723 initialization status of variables. */ 724DEF_RTL_EXPR(VAR_LOCATION, "var_location", "tei", RTX_EXTRA) 725 726/* Used in VAR_LOCATION for a pointer to a decl that is no longer 727 addressable. */ 728DEF_RTL_EXPR(DEBUG_IMPLICIT_PTR, "debug_implicit_ptr", "t", RTX_OBJ) 729 730/* Represents value that argument had on function entry. The 731 single argument is the DECL_INCOMING_RTL of the corresponding 732 parameter. */ 733DEF_RTL_EXPR(ENTRY_VALUE, "entry_value", "0", RTX_OBJ) 734 735/* Used in VAR_LOCATION for a reference to a parameter that has 736 been optimized away completely. */ 737DEF_RTL_EXPR(DEBUG_PARAMETER_REF, "debug_parameter_ref", "t", RTX_OBJ) 738 739/* All expressions from this point forward appear only in machine 740 descriptions. */ 741#ifdef GENERATOR_FILE 742 743/* Pattern-matching operators: */ 744 745/* Use the function named by the second arg (the string) 746 as a predicate; if matched, store the structure that was matched 747 in the operand table at index specified by the first arg (the integer). 748 If the second arg is the null string, the structure is just stored. 749 750 A third string argument indicates to the register allocator restrictions 751 on where the operand can be allocated. 752 753 If the target needs no restriction on any instruction this field should 754 be the null string. 755 756 The string is prepended by: 757 '=' to indicate the operand is only written to. 758 '+' to indicate the operand is both read and written to. 759 760 Each character in the string represents an allocable class for an operand. 761 'g' indicates the operand can be any valid class. 762 'i' indicates the operand can be immediate (in the instruction) data. 763 'r' indicates the operand can be in a register. 764 'm' indicates the operand can be in memory. 765 'o' a subset of the 'm' class. Those memory addressing modes that 766 can be offset at compile time (have a constant added to them). 767 768 Other characters indicate target dependent operand classes and 769 are described in each target's machine description. 770 771 For instructions with more than one operand, sets of classes can be 772 separated by a comma to indicate the appropriate multi-operand constraints. 773 There must be a 1 to 1 correspondence between these sets of classes in 774 all operands for an instruction. 775 */ 776DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH) 777 778/* Match a SCRATCH or a register. When used to generate rtl, a 779 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies 780 the desired mode and the first argument is the operand number. 781 The second argument is the constraint. */ 782DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH) 783 784/* Apply a predicate, AND match recursively the operands of the rtx. 785 Operand 0 is the operand-number, as in match_operand. 786 Operand 1 is a predicate to apply (as a string, a function name). 787 Operand 2 is a vector of expressions, each of which must match 788 one subexpression of the rtx this construct is matching. */ 789DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH) 790 791/* Match a PARALLEL of arbitrary length. The predicate is applied 792 to the PARALLEL and the initial expressions in the PARALLEL are matched. 793 Operand 0 is the operand-number, as in match_operand. 794 Operand 1 is a predicate to apply to the PARALLEL. 795 Operand 2 is a vector of expressions, each of which must match the 796 corresponding element in the PARALLEL. */ 797DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH) 798 799/* Match only something equal to what is stored in the operand table 800 at the index specified by the argument. Use with MATCH_OPERAND. */ 801DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH) 802 803/* Match only something equal to what is stored in the operand table 804 at the index specified by the argument. Use with MATCH_OPERATOR. */ 805DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH) 806 807/* Match only something equal to what is stored in the operand table 808 at the index specified by the argument. Use with MATCH_PARALLEL. */ 809DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH) 810 811/* Appears only in define_predicate/define_special_predicate 812 expressions. Evaluates true only if the operand has an RTX code 813 from the set given by the argument (a comma-separated list). If the 814 second argument is present and nonempty, it is a sequence of digits 815 and/or letters which indicates the subexpression to test, using the 816 same syntax as genextract/genrecog's location strings: 0-9 for 817 XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to 818 the result of the one before it. */ 819DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH) 820 821/* Used to inject a C conditional expression into an .md file. It can 822 appear in a predicate definition or an attribute expression. */ 823DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH) 824 825/* Insn (and related) definitions. */ 826 827/* Definition of the pattern for one kind of instruction. 828 Operand: 829 0: names this instruction. 830 If the name is the null string, the instruction is in the 831 machine description just to be recognized, and will never be emitted by 832 the tree to rtl expander. 833 1: is the pattern. 834 2: is a string which is a C expression 835 giving an additional condition for recognizing this pattern. 836 A null string means no extra condition. 837 3: is the action to execute if this pattern is matched. 838 If this assembler code template starts with a * then it is a fragment of 839 C code to run to decide on a template to use. Otherwise, it is the 840 template to use. 841 4: optionally, a vector of attributes for this insn. 842 */ 843DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA) 844 845/* Definition of a peephole optimization. 846 1st operand: vector of insn patterns to match 847 2nd operand: C expression that must be true 848 3rd operand: template or C code to produce assembler output. 849 4: optionally, a vector of attributes for this insn. 850 851 This form is deprecated; use define_peephole2 instead. */ 852DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA) 853 854/* Definition of a split operation. 855 1st operand: insn pattern to match 856 2nd operand: C expression that must be true 857 3rd operand: vector of insn patterns to place into a SEQUENCE 858 4th operand: optionally, some C code to execute before generating the 859 insns. This might, for example, create some RTX's and store them in 860 elements of `recog_data.operand' for use by the vector of 861 insn-patterns. 862 (`operands' is an alias here for `recog_data.operand'). */ 863DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA) 864 865/* Definition of an insn and associated split. 866 This is the concatenation, with a few modifications, of a define_insn 867 and a define_split which share the same pattern. 868 Operand: 869 0: names this instruction. 870 If the name is the null string, the instruction is in the 871 machine description just to be recognized, and will never be emitted by 872 the tree to rtl expander. 873 1: is the pattern. 874 2: is a string which is a C expression 875 giving an additional condition for recognizing this pattern. 876 A null string means no extra condition. 877 3: is the action to execute if this pattern is matched. 878 If this assembler code template starts with a * then it is a fragment of 879 C code to run to decide on a template to use. Otherwise, it is the 880 template to use. 881 4: C expression that must be true for split. This may start with "&&" 882 in which case the split condition is the logical and of the insn 883 condition and what follows the "&&" of this operand. 884 5: vector of insn patterns to place into a SEQUENCE 885 6: optionally, some C code to execute before generating the 886 insns. This might, for example, create some RTX's and store them in 887 elements of `recog_data.operand' for use by the vector of 888 insn-patterns. 889 (`operands' is an alias here for `recog_data.operand'). 890 7: optionally, a vector of attributes for this insn. */ 891DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA) 892 893/* Definition of an RTL peephole operation. 894 Follows the same arguments as define_split. */ 895DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA) 896 897/* Define how to generate multiple insns for a standard insn name. 898 1st operand: the insn name. 899 2nd operand: vector of insn-patterns. 900 Use match_operand to substitute an element of `recog_data.operand'. 901 3rd operand: C expression that must be true for this to be available. 902 This may not test any operands. 903 4th operand: Extra C code to execute before generating the insns. 904 This might, for example, create some RTX's and store them in 905 elements of `recog_data.operand' for use by the vector of 906 insn-patterns. 907 (`operands' is an alias here for `recog_data.operand'). 908 5th: optionally, a vector of attributes for this expand. */ 909DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEssV", RTX_EXTRA) 910 911/* Define a requirement for delay slots. 912 1st operand: Condition involving insn attributes that, if true, 913 indicates that the insn requires the number of delay slots 914 shown. 915 2nd operand: Vector whose length is the three times the number of delay 916 slots required. 917 Each entry gives three conditions, each involving attributes. 918 The first must be true for an insn to occupy that delay slot 919 location. The second is true for all insns that can be 920 annulled if the branch is true and the third is true for all 921 insns that can be annulled if the branch is false. 922 923 Multiple DEFINE_DELAYs may be present. They indicate differing 924 requirements for delay slots. */ 925DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA) 926 927/* Define attribute computation for `asm' instructions. */ 928DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA) 929 930/* Definition of a conditional execution meta operation. Automatically 931 generates new instances of DEFINE_INSN, selected by having attribute 932 "predicable" true. The new pattern will contain a COND_EXEC and the 933 predicate at top-level. 934 935 Operand: 936 0: The predicate pattern. The top-level form should match a 937 relational operator. Operands should have only one alternative. 938 1: A C expression giving an additional condition for recognizing 939 the generated pattern. 940 2: A template or C code to produce assembler output. */ 941DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA) 942 943/* Definition of an operand predicate. The difference between 944 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will 945 not warn about a match_operand with no mode if it has a predicate 946 defined with DEFINE_SPECIAL_PREDICATE. 947 948 Operand: 949 0: The name of the predicate. 950 1: A boolean expression which computes whether or not the predicate 951 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND, 952 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog 953 can calculate the set of RTX codes that can possibly match. 954 2: A C function body which must return true for the predicate to match. 955 Optional. Use this when the test is too complicated to fit into a 956 match_test expression. */ 957DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA) 958DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA) 959 960/* Definition of a register operand constraint. This simply maps the 961 constraint string to a register class. 962 963 Operand: 964 0: The name of the constraint (often, but not always, a single letter). 965 1: A C expression which evaluates to the appropriate register class for 966 this constraint. If this is not just a constant, it should look only 967 at -m switches and the like. 968 2: A docstring for this constraint, in Texinfo syntax; not currently 969 used, in future will be incorporated into the manual's list of 970 machine-specific operand constraints. */ 971DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA) 972 973/* Definition of a non-register operand constraint. These look at the 974 operand and decide whether it fits the constraint. 975 976 DEFINE_CONSTRAINT gets no special treatment if it fails to match. 977 It is appropriate for constant-only constraints, and most others. 978 979 DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made 980 to match, if it doesn't already, by converting the operand to the form 981 (mem (reg X)) where X is a base register. It is suitable for constraints 982 that describe a subset of all memory references. 983 984 DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made 985 to match, if it doesn't already, by converting the operand to the form 986 (reg X) where X is a base register. It is suitable for constraints that 987 describe a subset of all address references. 988 989 When in doubt, use plain DEFINE_CONSTRAINT. 990 991 Operand: 992 0: The name of the constraint (often, but not always, a single letter). 993 1: A docstring for this constraint, in Texinfo syntax; not currently 994 used, in future will be incorporated into the manual's list of 995 machine-specific operand constraints. 996 2: A boolean expression which computes whether or not the constraint 997 matches. It should follow the same rules as a define_predicate 998 expression, including the bit about specifying the set of RTX codes 999 that could possibly match. MATCH_TEST subexpressions may make use of 1000 these variables: 1001 `op' - the RTL object defining the operand. 1002 `mode' - the mode of `op'. 1003 `ival' - INTVAL(op), if op is a CONST_INT. 1004 `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE. 1005 `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE. 1006 `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point 1007 CONST_DOUBLE. 1008 Do not use ival/hval/lval/rval if op is not the appropriate kind of 1009 RTL object. */ 1010DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA) 1011DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA) 1012DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA) 1013 1014 1015/* Constructions for CPU pipeline description described by NDFAs. */ 1016 1017/* (define_cpu_unit string [string]) describes cpu functional 1018 units (separated by comma). 1019 1020 1st operand: Names of cpu functional units. 1021 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON). 1022 1023 All define_reservations, define_cpu_units, and 1024 define_query_cpu_units should have unique names which may not be 1025 "nothing". */ 1026DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA) 1027 1028/* (define_query_cpu_unit string [string]) describes cpu functional 1029 units analogously to define_cpu_unit. The reservation of such 1030 units can be queried for automaton state. */ 1031DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA) 1032 1033/* (exclusion_set string string) means that each CPU functional unit 1034 in the first string can not be reserved simultaneously with any 1035 unit whose name is in the second string and vise versa. CPU units 1036 in the string are separated by commas. For example, it is useful 1037 for description CPU with fully pipelined floating point functional 1038 unit which can execute simultaneously only single floating point 1039 insns or only double floating point insns. All CPU functional 1040 units in a set should belong to the same automaton. */ 1041DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA) 1042 1043/* (presence_set string string) means that each CPU functional unit in 1044 the first string can not be reserved unless at least one of pattern 1045 of units whose names are in the second string is reserved. This is 1046 an asymmetric relation. CPU units or unit patterns in the strings 1047 are separated by commas. Pattern is one unit name or unit names 1048 separated by white-spaces. 1049 1050 For example, it is useful for description that slot1 is reserved 1051 after slot0 reservation for a VLIW processor. We could describe it 1052 by the following construction 1053 1054 (presence_set "slot1" "slot0") 1055 1056 Or slot1 is reserved only after slot0 and unit b0 reservation. In 1057 this case we could write 1058 1059 (presence_set "slot1" "slot0 b0") 1060 1061 All CPU functional units in a set should belong to the same 1062 automaton. */ 1063DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA) 1064 1065/* (final_presence_set string string) is analogous to `presence_set'. 1066 The difference between them is when checking is done. When an 1067 instruction is issued in given automaton state reflecting all 1068 current and planned unit reservations, the automaton state is 1069 changed. The first state is a source state, the second one is a 1070 result state. Checking for `presence_set' is done on the source 1071 state reservation, checking for `final_presence_set' is done on the 1072 result reservation. This construction is useful to describe a 1073 reservation which is actually two subsequent reservations. For 1074 example, if we use 1075 1076 (presence_set "slot1" "slot0") 1077 1078 the following insn will be never issued (because slot1 requires 1079 slot0 which is absent in the source state). 1080 1081 (define_reservation "insn_and_nop" "slot0 + slot1") 1082 1083 but it can be issued if we use analogous `final_presence_set'. */ 1084DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA) 1085 1086/* (absence_set string string) means that each CPU functional unit in 1087 the first string can be reserved only if each pattern of units 1088 whose names are in the second string is not reserved. This is an 1089 asymmetric relation (actually exclusion set is analogous to this 1090 one but it is symmetric). CPU units or unit patterns in the string 1091 are separated by commas. Pattern is one unit name or unit names 1092 separated by white-spaces. 1093 1094 For example, it is useful for description that slot0 can not be 1095 reserved after slot1 or slot2 reservation for a VLIW processor. We 1096 could describe it by the following construction 1097 1098 (absence_set "slot2" "slot0, slot1") 1099 1100 Or slot2 can not be reserved if slot0 and unit b0 are reserved or 1101 slot1 and unit b1 are reserved . In this case we could write 1102 1103 (absence_set "slot2" "slot0 b0, slot1 b1") 1104 1105 All CPU functional units in a set should to belong the same 1106 automaton. */ 1107DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA) 1108 1109/* (final_absence_set string string) is analogous to `absence_set' but 1110 checking is done on the result (state) reservation. See comments 1111 for `final_presence_set'. */ 1112DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA) 1113 1114/* (define_bypass number out_insn_names in_insn_names) names bypass 1115 with given latency (the first number) from insns given by the first 1116 string (see define_insn_reservation) into insns given by the second 1117 string. Insn names in the strings are separated by commas. The 1118 third operand is optional name of function which is additional 1119 guard for the bypass. The function will get the two insns as 1120 parameters. If the function returns zero the bypass will be 1121 ignored for this case. Additional guard is necessary to recognize 1122 complicated bypasses, e.g. when consumer is load address. If there 1123 are more one bypass with the same output and input insns, the 1124 chosen bypass is the first bypass with a guard in description whose 1125 guard function returns nonzero. If there is no such bypass, then 1126 bypass without the guard function is chosen. */ 1127DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA) 1128 1129/* (define_automaton string) describes names of automata generated and 1130 used for pipeline hazards recognition. The names are separated by 1131 comma. Actually it is possibly to generate the single automaton 1132 but unfortunately it can be very large. If we use more one 1133 automata, the summary size of the automata usually is less than the 1134 single one. The automaton name is used in define_cpu_unit and 1135 define_query_cpu_unit. All automata should have unique names. */ 1136DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA) 1137 1138/* (automata_option string) describes option for generation of 1139 automata. Currently there are the following options: 1140 1141 o "no-minimization" which makes no minimization of automata. This 1142 is only worth to do when we are debugging the description and 1143 need to look more accurately at reservations of states. 1144 1145 o "time" which means printing additional time statistics about 1146 generation of automata. 1147 1148 o "v" which means generation of file describing the result 1149 automata. The file has suffix `.dfa' and can be used for the 1150 description verification and debugging. 1151 1152 o "w" which means generation of warning instead of error for 1153 non-critical errors. 1154 1155 o "ndfa" which makes nondeterministic finite state automata. 1156 1157 o "progress" which means output of a progress bar showing how many 1158 states were generated so far for automaton being processed. */ 1159DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA) 1160 1161/* (define_reservation string string) names reservation (the first 1162 string) of cpu functional units (the 2nd string). Sometimes unit 1163 reservations for different insns contain common parts. In such 1164 case, you can describe common part and use its name (the 1st 1165 parameter) in regular expression in define_insn_reservation. All 1166 define_reservations, define_cpu_units, and define_query_cpu_units 1167 should have unique names which may not be "nothing". */ 1168DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA) 1169 1170/* (define_insn_reservation name default_latency condition regexpr) 1171 describes reservation of cpu functional units (the 3nd operand) for 1172 instruction which is selected by the condition (the 2nd parameter). 1173 The first parameter is used for output of debugging information. 1174 The reservations are described by a regular expression according 1175 the following syntax: 1176 1177 regexp = regexp "," oneof 1178 | oneof 1179 1180 oneof = oneof "|" allof 1181 | allof 1182 1183 allof = allof "+" repeat 1184 | repeat 1185 1186 repeat = element "*" number 1187 | element 1188 1189 element = cpu_function_unit_name 1190 | reservation_name 1191 | result_name 1192 | "nothing" 1193 | "(" regexp ")" 1194 1195 1. "," is used for describing start of the next cycle in 1196 reservation. 1197 1198 2. "|" is used for describing the reservation described by the 1199 first regular expression *or* the reservation described by the 1200 second regular expression *or* etc. 1201 1202 3. "+" is used for describing the reservation described by the 1203 first regular expression *and* the reservation described by the 1204 second regular expression *and* etc. 1205 1206 4. "*" is used for convenience and simply means sequence in 1207 which the regular expression are repeated NUMBER times with 1208 cycle advancing (see ","). 1209 1210 5. cpu functional unit name which means its reservation. 1211 1212 6. reservation name -- see define_reservation. 1213 1214 7. string "nothing" means no units reservation. */ 1215 1216DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA) 1217 1218/* Expressions used for insn attributes. */ 1219 1220/* Definition of an insn attribute. 1221 1st operand: name of the attribute 1222 2nd operand: comma-separated list of possible attribute values 1223 3rd operand: expression for the default value of the attribute. */ 1224DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA) 1225 1226/* Definition of an insn attribute that uses an existing enumerated type. 1227 1st operand: name of the attribute 1228 2nd operand: the name of the enumerated type 1229 3rd operand: expression for the default value of the attribute. */ 1230DEF_RTL_EXPR(DEFINE_ENUM_ATTR, "define_enum_attr", "sse", RTX_EXTRA) 1231 1232/* Marker for the name of an attribute. */ 1233DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA) 1234 1235/* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and 1236 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that 1237 pattern. 1238 1239 (set_attr "name" "value") is equivalent to 1240 (set (attr "name") (const_string "value")) */ 1241DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA) 1242 1243/* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to 1244 specify that attribute values are to be assigned according to the 1245 alternative matched. 1246 1247 The following three expressions are equivalent: 1248 1249 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1") 1250 (eq_attrq "alternative" "2") (const_string "a2")] 1251 (const_string "a3"))) 1252 (set_attr_alternative "att" [(const_string "a1") (const_string "a2") 1253 (const_string "a3")]) 1254 (set_attr "att" "a1,a2,a3") 1255 */ 1256DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA) 1257 1258/* A conditional expression true if the value of the specified attribute of 1259 the current insn equals the specified value. The first operand is the 1260 attribute name and the second is the comparison value. */ 1261DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA) 1262 1263/* A special case of the above representing a set of alternatives. The first 1264 operand is bitmap of the set, the second one is the default value. */ 1265DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA) 1266 1267/* A conditional expression which is true if the specified flag is 1268 true for the insn being scheduled in reorg. 1269 1270 genattr.c defines the following flags which can be tested by 1271 (attr_flag "foo") expressions in eligible_for_delay: forward, backward. */ 1272 1273DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA) 1274 1275/* General conditional. The first operand is a vector composed of pairs of 1276 expressions. The first element of each pair is evaluated, in turn. 1277 The value of the conditional is the second expression of the first pair 1278 whose first expression evaluates nonzero. If none of the expressions is 1279 true, the second operand will be used as the value of the conditional. */ 1280DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA) 1281 1282DEF_RTL_EXPR(DEFINE_SUBST, "define_subst", "sEsE", RTX_EXTRA) 1283DEF_RTL_EXPR(DEFINE_SUBST_ATTR, "define_subst_attr", "ssss", RTX_EXTRA) 1284#endif /* GENERATOR_FILE */ 1285 1286/* 1287Local variables: 1288mode:c 1289End: 1290*/ 1291