1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 /*
4 * Helper functions for dealing with power management registers
5 * and the differences between PCH variants.
6 */
7
8 /*
9 * This file is created based on Intel Tiger Lake Processor PCH Datasheet
10 * Document number: 575857
11 * Chapter number: 4
12 */
13
14 #define __SIMPLE_DEVICE__
15
16 #include <acpi/acpi_pm.h>
17 #include <console/console.h>
18 #include <device/mmio.h>
19 #include <device/device.h>
20 #include <device/pci.h>
21 #include <gpio.h>
22 #include <intelblocks/pmclib.h>
23 #include <intelblocks/rtc.h>
24 #include <intelblocks/tco.h>
25 #include <soc/espi.h>
26 #include <soc/gpe.h>
27 #include <soc/iomap.h>
28 #include <soc/pci_devs.h>
29 #include <soc/pm.h>
30 #include <soc/smbus.h>
31 #include <soc/soc_chip.h>
32 #include <security/vboot/vbnv.h>
33
34 /*
35 * SMI
36 */
37
soc_smi_sts_array(size_t * a)38 const char *const *soc_smi_sts_array(size_t *a)
39 {
40 static const char *const smi_sts_bits[] = {
41 [BIOS_STS_BIT] = "BIOS",
42 [LEGACY_USB_STS_BIT] = "LEGACY_USB",
43 [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
44 [APM_STS_BIT] = "APM",
45 [SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
46 [PM1_STS_BIT] = "PM1",
47 [GPE0_STS_BIT] = "GPE0",
48 [GPIO_STS_BIT] = "GPI",
49 [MCSMI_STS_BIT] = "MCSMI",
50 [DEVMON_STS_BIT] = "DEVMON",
51 [TCO_STS_BIT] = "TCO",
52 [PERIODIC_STS_BIT] = "PERIODIC",
53 [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI",
54 [SMBUS_SMI_STS_BIT] = "SMBUS_SMI",
55 [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",
56 [MONITOR_STS_BIT] = "MONITOR",
57 [SPI_SMI_STS_BIT] = "SPI",
58 [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK",
59 [ESPI_SMI_STS_BIT] = "ESPI_SMI",
60 };
61
62 *a = ARRAY_SIZE(smi_sts_bits);
63 return smi_sts_bits;
64 }
65
66 /*
67 * TCO
68 */
69
soc_tco_sts_array(size_t * a)70 const char *const *soc_tco_sts_array(size_t *a)
71 {
72 static const char *const tco_sts_bits[] = {
73 [0] = "NMI2SMI",
74 [1] = "SW_TCO",
75 [2] = "TCO_INT",
76 [3] = "TIMEOUT",
77 [7] = "NEWCENTURY",
78 [8] = "BIOSWR",
79 [9] = "DMISCI",
80 [10] = "DMISMI",
81 [12] = "DMISERR",
82 [13] = "SLVSEL",
83 [16] = "INTRD_DET",
84 [17] = "SECOND_TO",
85 [18] = "BOOT",
86 [20] = "SMLINK_SLV"
87 };
88
89 *a = ARRAY_SIZE(tco_sts_bits);
90 return tco_sts_bits;
91 }
92
93 /*
94 * GPE0
95 */
96
soc_std_gpe_sts_array(size_t * a)97 const char *const *soc_std_gpe_sts_array(size_t *a)
98 {
99 static const char *const gpe_sts_bits[] = {
100 [1] = "HOTPLUG",
101 [2] = "SWGPE",
102 [6] = "TCO_SCI",
103 [7] = "SMB_WAK",
104 [9] = "PCI_EXP",
105 [10] = "BATLOW",
106 [11] = "PME",
107 [12] = "ME",
108 [13] = "PME_B0",
109 [14] = "eSPI",
110 [15] = "GPIO Tier-2",
111 [16] = "LAN_WAKE",
112 [18] = "WADT"
113 };
114
115 *a = ARRAY_SIZE(gpe_sts_bits);
116 return gpe_sts_bits;
117 }
118
pmc_set_disb(void)119 void pmc_set_disb(void)
120 {
121 /* Set the DISB after DRAM init */
122 uint8_t disb_val;
123 /* Only care about bits [23:16] of register GEN_PMCON_A */
124 uint8_t *addr = (uint8_t *)(pmc_mmio_regs() + GEN_PMCON_A + 2);
125
126 disb_val = read8(addr);
127 disb_val |= (DISB >> 16);
128
129 /* Don't clear bits that are write-1-to-clear */
130 disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16);
131 write8(addr, disb_val);
132 }
133
134 /*
135 * PMC controller gets hidden from PCI bus
136 * during FSP-Silicon init call. Hence PWRMBASE
137 * can't be accessible using PCI configuration space
138 * read/write.
139 */
pmc_mmio_regs(void)140 uint8_t *pmc_mmio_regs(void)
141 {
142 return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
143 }
144
soc_read_pmc_base(void)145 uintptr_t soc_read_pmc_base(void)
146 {
147 return (uintptr_t)pmc_mmio_regs();
148 }
149
soc_pmc_etr_addr(void)150 uint32_t *soc_pmc_etr_addr(void)
151 {
152 return (uint32_t *)(soc_read_pmc_base() + ETR);
153 }
154
soc_get_gpi_gpe_configs(uint8_t * dw0,uint8_t * dw1,uint8_t * dw2)155 void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
156 {
157 DEVTREE_CONST struct soc_intel_tigerlake_config *config;
158
159 config = config_of_soc();
160
161 /* Assign to out variable */
162 *dw0 = config->pmc_gpe0_dw0;
163 *dw1 = config->pmc_gpe0_dw1;
164 *dw2 = config->pmc_gpe0_dw2;
165 }
166
rtc_failed(uint32_t gen_pmcon_b)167 static int rtc_failed(uint32_t gen_pmcon_b)
168 {
169 return !!(gen_pmcon_b & RTC_BATTERY_DEAD);
170 }
171
clear_rtc_failed(void)172 static void clear_rtc_failed(void)
173 {
174 clrbits8(pmc_mmio_regs() + GEN_PMCON_B, RTC_BATTERY_DEAD);
175 }
176
check_rtc_failed(uint32_t gen_pmcon_b)177 static int check_rtc_failed(uint32_t gen_pmcon_b)
178 {
179 const int failed = rtc_failed(gen_pmcon_b);
180 if (failed) {
181 clear_rtc_failed();
182 printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", failed);
183 }
184
185 return failed;
186 }
187
soc_get_rtc_failed(void)188 int soc_get_rtc_failed(void)
189 {
190 const struct chipset_power_state *ps;
191
192 if (acpi_fetch_pm_state(&ps, PS_CLAIMER_RTC) < 0)
193 return 1;
194
195 return check_rtc_failed(ps->gen_pmcon_b);
196 }
197
vbnv_cmos_failed(void)198 int vbnv_cmos_failed(void)
199 {
200 return check_rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
201 }
202
deep_s3_enabled(void)203 static inline int deep_s3_enabled(void)
204 {
205 uint32_t deep_s3_pol;
206
207 deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
208 return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
209 }
210
211 /* Return 0, 3, or 5 to indicate the previous sleep state. */
soc_prev_sleep_state(const struct chipset_power_state * ps,int prev_sleep_state)212 int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
213 {
214 /*
215 * Check for any power failure to determine if this a wake from
216 * S5 because the PCH does not set the WAK_STS bit when waking
217 * from a true G3 state.
218 */
219 if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)))
220 prev_sleep_state = ACPI_S5;
221
222 /*
223 * If waking from S3 determine if deep S3 is enabled. If not,
224 * need to check both deep sleep well and normal suspend well.
225 * Otherwise just check deep sleep well.
226 */
227 if (prev_sleep_state == ACPI_S3) {
228 /* PWR_FLR represents deep sleep power well loss. */
229 uint32_t mask = PWR_FLR;
230
231 /* If deep s3 isn't enabled check the suspend well too. */
232 if (!deep_s3_enabled())
233 mask |= SUS_PWR_FLR;
234
235 if (ps->gen_pmcon_a & mask)
236 prev_sleep_state = ACPI_S5;
237 }
238
239 return prev_sleep_state;
240 }
241
soc_fill_power_state(struct chipset_power_state * ps)242 void soc_fill_power_state(struct chipset_power_state *ps)
243 {
244 uint8_t *pmc;
245
246 ps->tco1_sts = tco_read_reg(TCO1_STS);
247 ps->tco2_sts = tco_read_reg(TCO2_STS);
248
249 printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
250
251 pmc = pmc_mmio_regs();
252 ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
253 ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
254 ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
255 ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
256 ps->hpr_cause0 = read32(pmc + HPR_CAUSE0);
257
258 printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
259 ps->gen_pmcon_a, ps->gen_pmcon_b);
260
261 printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
262 ps->gblrst_cause[0], ps->gblrst_cause[1]);
263
264 printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0);
265 }
266
267 /* STM Support */
get_pmbase(void)268 uint16_t get_pmbase(void)
269 {
270 return (uint16_t)ACPI_BASE_ADDRESS;
271 }
272
273 /*
274 * Set which power state system will be after reapplying
275 * the power (from G3 State)
276 */
pmc_soc_set_afterg3_en(const bool on)277 void pmc_soc_set_afterg3_en(const bool on)
278 {
279 uint8_t reg8;
280 uint8_t *const pmcbase = pmc_mmio_regs();
281
282 reg8 = read8(pmcbase + GEN_PMCON_A);
283 if (on)
284 reg8 &= ~SLEEP_AFTER_POWER_FAIL;
285 else
286 reg8 |= SLEEP_AFTER_POWER_FAIL;
287 write8(pmcbase + GEN_PMCON_A, reg8);
288 }
289