1## SPDX-License-Identifier: GPL-2.0-only 2 3config PSP_VERSTAGE_CCP_DMA 4 bool 5 default n 6 help 7 Configure PSP Verstage to use Crypto Co-processor (CCP) DMA while 8 accessing the boot device. Select it on platforms which supports 9 using CCP DMA to access the boot device. 10 11config PSP_S0I3_RESUME_VERSTAGE 12 bool "S0i3 resume verstage" 13 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK 14 default n 15 help 16 Select this item to enable running verstage during S0i3 resume. 17 18config PSP_INIT_TPM_ON_S0I3_RESUME 19 bool 20 depends on TPM2 && PSP_S0I3_RESUME_VERSTAGE 21 default PSP_S0I3_RESUME_VERSTAGE 22 help 23 If the TPM is reset while in S0i3, it must be reinitialized 24 during s0i3 resume. This must be performed in PSP verstage since 25 coreboot is otherwise not involved with s0i3 resume. 26 27config PSP_SUPPORTS_EFS2_RELATIVE_ADDR 28 bool 29 default n 30 help 31 On SoCs where PSP uses A/B recovery layout, PSP support relative addressing 32 from the start of the SPI ROM. Enable this config on SoCs where PSP supports 33 relative addressing so that PSP verstage can pass the offset. 34 35config SEPARATE_SIGNED_PSPFW 36 def_bool n 37 help 38 Put signed AMD/PSP firmwares outside FW_MAIN_[AB] so vboot doesn't verify them, 39 and rely on PSP's verification. 40 41config PSP_VERSTAGE_STACK_IS_MAPPED 42 bool 43 default y if SOC_AMD_PICASSO 44 default n 45 help 46 This configuration indicates whether the PSP Verstage stack is mapped to a virtual 47 address space. This has been the case so far only in Picasso SoC. 48 49config PSP_VERSTAGE_MAP_ENTIRE_SPIROM 50 bool 51 default n 52 help 53 This configuration indicates whether PSP Verstage needs to map the entire SPI ROM. 54 This is required only in Cezanne SoC at the moment. 55