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1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <memlayout.h>
4
5#include <arch/header.ld>
6
7/*
8 * SRAM_L2C is the half part of L2 cache that we borrow it to be used as SRAM.
9 * It will be returned before starting the ramstage.
10 * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
11 */
12#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
13#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
14
15#define DRAM_DMA(addr, size) \
16	REGION(dram_dma, addr, size, 4K) \
17	_ = ASSERT(size % 4K == 0, \
18		"DRAM DMA buffer should be multiple of smallest page size (4K)!");
19
20SECTIONS
21{
22	SRAM_L2C_START(0x000C0000)
23	BOOTBLOCK(0x000C1000, 85K)
24	VERSTAGE(0x000D7000, 114K)
25	SRAM_L2C_END(0x00100000)
26
27	SRAM_START(0x00100000)
28	VBOOT2_WORK(0x00100000, 12K)
29	TPM_LOG(0x00103000, 2K)
30	FMAP_CACHE(0x00103800, 2K)
31	PRERAM_CBMEM_CONSOLE(0x00104000, 12K)
32	WATCHDOG_TOMBSTONE(0x00107000, 4)
33	PRERAM_CBFS_CACHE(0x00107004, 8K - 4)
34	CBFS_MCACHE(0x00109000, 8K)
35	TIMESTAMP(0x0010B000, 4K)
36	ROMSTAGE(0x0010C000, 92K)
37	STACK(0x00124000, 16K)
38	TTB(0x00128000, 28K)
39	DMA_COHERENT(0x0012F000, 4K)
40	SRAM_END(0x00130000)
41
42	DRAM_START(0x40000000)
43	DRAM_DMA(0x40000000, 1M)
44	POSTRAM_CBFS_CACHE(0x40100000, 1M)
45	RAMSTAGE(0x40200000, 2M)
46}
47