1-- 2-- Copyright 2024 The Android Open Source Project 3-- 4-- Licensed under the Apache License, Version 2.0 (the 'License'); 5-- you may not use this file except in compliance with the License. 6-- You may obtain a copy of the License at 7-- 8-- https://www.apache.org/licenses/LICENSE-2.0 9-- 10-- Unless required by applicable law or agreed to in writing, software 11-- distributed under the License is distributed on an 'AS IS' BASIS, 12-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13-- See the License for the specific language governing permissions and 14-- limitations under the License. 15 16-- Contains ARM Statistical Profiling Extension records 17CREATE PERFETTO VIEW linux_perf_spe_record ( 18 -- Timestap when the operation was sampled 19 ts TIMESTAMP, 20 -- Thread the operation executed in 21 utid JOINID(thread.id), 22 -- Exception level the instruction was executed in 23 exception_level STRING, 24 -- Instruction virtual address 25 instruction_frame_id LONG, 26 -- Type of operation sampled 27 operation STRING, 28 -- The virtual address accessed by the operation (0 if no memory access was 29 -- performed) 30 data_virtual_address LONG, 31 -- The physical address accessed by the operation (0 if no memory access was 32 -- performed) 33 data_physical_address LONG, 34 -- Cycle count from the operation being dispatched for issue to the operation 35 -- being complete. 36 total_latency LONG, 37 -- Cycle count from the operation being dispatched for issue to the operation 38 -- being issued for execution. 39 issue_latency LONG, 40 -- Cycle count from a virtual address being passed to the MMU for translation 41 -- to the result of the translation being available. 42 translation_latency LONG, 43 -- Where the data returned for a load operation was sourced 44 data_source STRING, 45 -- Operation generated an exception 46 exception_gen BOOL, 47 -- Operation architecturally retired 48 retired BOOL, 49 -- Operation caused a level 1 data cache access 50 l1d_access BOOL, 51 -- Operation caused a level 1 data cache refill 52 l1d_refill BOOL, 53 -- Operation caused a TLB access 54 tlb_access BOOL, 55 -- Operation caused a TLB refill involving at least one translation table walk 56 tlb_refill BOOL, 57 -- Conditional instruction failed its condition code check 58 not_taken BOOL, 59 -- Whether a branch caused a correction to the predicted program flow 60 mispred BOOL, 61 -- Operation caused a last level data or unified cache access 62 llc_access BOOL, 63 -- Whether the operation could not be completed by the last level data cache 64 -- (or any above) 65 llc_refill BOOL, 66 -- Operation caused an access to another socket in a multi-socket system 67 remote_access BOOL, 68 -- Operation that incurred additional latency due to the alignment of the 69 -- address and the size of the data being accessed 70 alignment BOOL, 71 -- Whether the operation executed in transactional state 72 tme_transaction BOOL, 73 -- SVE or SME operation with at least one false element in the governing 74 -- predicate(s) 75 sve_partial_pred BOOL, 76 -- SVE or SME operation with no true element in the governing predicate(s) 77 sve_empty_pred BOOL, 78 -- Whether a load operation caused a cache access to at least the level 2 data 79 -- or unified cache 80 l2d_access BOOL, 81 -- Whether a load operation accessed and missed the level 2 data or unified 82 -- cache. Not set for accesses that are satisfied from refilling data of a 83 -- previous miss 84 l2d_hit BOOL, 85 -- Whether a load operation accessed modified data in a cache 86 cache_data_modified BOOL, 87 -- Wheter a load operation hit a recently fetched line in a cache 88 recenty_fetched BOOL, 89 -- Whether a load operation snooped data from a cache outside the cache 90 -- hierarchy of this core 91 data_snooped BOOL 92) AS 93SELECT 94 ts, 95 utid, 96 exception_level, 97 instruction_frame_id, 98 operation, 99 data_virtual_address, 100 data_physical_address, 101 total_latency, 102 issue_latency, 103 translation_latency, 104 data_source, 105 ( 106 events_bitmask & ( 107 1 << 0 108 ) 109 ) != 0 AS exception_gen, 110 ( 111 events_bitmask & ( 112 1 << 1 113 ) 114 ) != 0 AS retired, 115 ( 116 events_bitmask & ( 117 1 << 2 118 ) 119 ) != 0 AS l1d_access, 120 ( 121 events_bitmask & ( 122 1 << 3 123 ) 124 ) != 0 AS l1d_refill, 125 ( 126 events_bitmask & ( 127 1 << 4 128 ) 129 ) != 0 AS tlb_access, 130 ( 131 events_bitmask & ( 132 1 << 5 133 ) 134 ) != 0 AS tlb_refill, 135 ( 136 events_bitmask & ( 137 1 << 6 138 ) 139 ) != 0 AS not_taken, 140 ( 141 events_bitmask & ( 142 1 << 7 143 ) 144 ) != 0 AS mispred, 145 ( 146 events_bitmask & ( 147 1 << 8 148 ) 149 ) != 0 AS llc_access, 150 ( 151 events_bitmask & ( 152 1 << 9 153 ) 154 ) != 0 AS llc_refill, 155 ( 156 events_bitmask & ( 157 1 << 10 158 ) 159 ) != 0 AS remote_access, 160 ( 161 events_bitmask & ( 162 1 << 11 163 ) 164 ) != 0 AS alignment, 165 ( 166 events_bitmask & ( 167 1 << 17 168 ) 169 ) != 0 AS tme_transaction, 170 ( 171 events_bitmask & ( 172 1 << 17 173 ) 174 ) != 0 AS sve_partial_pred, 175 ( 176 events_bitmask & ( 177 1 << 18 178 ) 179 ) != 0 AS sve_empty_pred, 180 ( 181 events_bitmask & ( 182 1 << 19 183 ) 184 ) != 0 AS l2d_access, 185 ( 186 events_bitmask & ( 187 1 << 20 188 ) 189 ) != 0 AS l2d_hit, 190 ( 191 events_bitmask & ( 192 1 << 21 193 ) 194 ) != 0 AS cache_data_modified, 195 ( 196 events_bitmask & ( 197 1 << 22 198 ) 199 ) != 0 AS recenty_fetched, 200 ( 201 events_bitmask & ( 202 1 << 23 203 ) 204 ) != 0 AS data_snooped 205FROM __intrinsic_spe_record; 206