1-- 2-- Copyright 2024 The Android Open Source Project 3-- 4-- Licensed under the Apache License, Version 2.0 (the "License"); 5-- you may not use this file except in compliance with the License. 6-- You may obtain a copy of the License at 7-- 8-- https://www.apache.org/licenses/LICENSE-2.0 9-- 10-- Unless required by applicable law or agreed to in writing, software 11-- distributed under the License is distributed on an "AS IS" BASIS, 12-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13-- See the License for the specific language governing permissions and 14-- limitations under the License. 15 16-- Converts event counter from count to rate (num of accesses per ns). 17CREATE PERFETTO FUNCTION _get_rate( 18 event STRING 19) 20RETURNS TABLE ( 21 ts TIMESTAMP, 22 dur DURATION, 23 access_rate LONG 24) AS 25SELECT 26 ts, 27 lead(ts) OVER (PARTITION BY track_id ORDER BY ts) - ts AS dur, 28 -- Rate of event accesses in a section (i.e. count / dur). 29 value / ( 30 lead(ts) OVER (PARTITION BY track_id ORDER BY ts) - ts 31 ) AS access_rate 32FROM counter AS c 33JOIN counter_track AS t 34 ON c.track_id = t.id 35WHERE 36 t.name = $event; 37 38-- The rate of L3 misses for each time slice based on the ARM DSU PMU counter's 39-- bus_access event. Units will be in number of L3 misses per ns. The number of 40-- accesses in a given duration can be calculated by multiplying the appropriate 41-- rate with the time in the window of interest. 42CREATE PERFETTO TABLE _arm_l3_miss_rate AS 43SELECT 44 ts, 45 dur, 46 access_rate AS l3_miss_rate 47FROM _get_rate("arm_dsu_0/bus_access/_cpu0"); 48 49-- The rate of L3 accesses for each time slice based on the ARM DSU PMU 50-- counter's l3d_cache event. Units will be in number of DDR accesses per ns. 51-- The number of accesses in a given duration can be calculated by multiplying 52-- the appropriate rate with the time in the window of interest. 53CREATE PERFETTO TABLE _arm_l3_hit_rate AS 54SELECT 55 ts, 56 dur, 57 access_rate AS l3_hit_rate 58FROM _get_rate("arm_dsu_0/l3d_cache/_cpu0"); 59