1 /* 2 * Copyright (C) 2018-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP_COMMON_H 8 #define STM32MP_COMMON_H 9 10 #include <stdbool.h> 11 12 #include <platform_def.h> 13 14 #define JEDEC_ST_BKID U(0x0) 15 #define JEDEC_ST_MFID U(0x20) 16 17 #define STM32MP_CHIP_SEC_CLOSED U(0x34D9CCC5) 18 #define STM32MP_CHIP_SEC_OPEN U(0xA764D182) 19 20 /* FWU configuration (max supported value is 15) */ 21 #define FWU_MAX_TRIAL_REBOOT U(3) 22 23 /* Define maximum page size for NAND devices */ 24 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) 25 26 /* Needed by STM32CubeProgrammer support */ 27 #define DWL_BUFFER_SIZE U(0x01000000) 28 29 /* Functions to save and get boot context address given by ROM code */ 30 void stm32mp_save_boot_ctx_address(uintptr_t address); 31 uintptr_t stm32mp_get_boot_ctx_address(void); 32 uint16_t stm32mp_get_boot_itf_selected(void); 33 34 bool stm32mp_is_single_core(void); 35 bool stm32mp_is_auth_supported(void); 36 uint32_t stm32mp_check_closed_device(void); 37 38 /* Return the base address of the DDR controller */ 39 uintptr_t stm32mp_ddrctrl_base(void); 40 41 /* Return the base address of the DDR PHY */ 42 uintptr_t stm32mp_ddrphyc_base(void); 43 44 /* Return the base address of the PWR peripheral */ 45 uintptr_t stm32mp_pwr_base(void); 46 47 /* Return the base address of the RCC peripheral */ 48 uintptr_t stm32mp_rcc_base(void); 49 50 void stm32mp_gic_pcpu_init(void); 51 void stm32mp_gic_init(void); 52 53 /* Check MMU status to allow spinlock use */ 54 bool stm32mp_lock_available(void); 55 56 int stm32_get_otp_index(const char *otp_name, uint32_t *otp_idx, 57 uint32_t *otp_len); 58 int stm32_get_otp_value(const char *otp_name, uint32_t *otp_val); 59 int stm32_get_otp_value_from_idx(const uint32_t otp_idx, uint32_t *otp_val); 60 61 /* Get IWDG platform instance ID from peripheral IO memory base address */ 62 uint32_t stm32_iwdg_get_instance(uintptr_t base); 63 64 /* Return bitflag mask for expected IWDG configuration from OTP content */ 65 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst); 66 67 #if defined(IMAGE_BL2) 68 /* Update OTP shadow registers with IWDG configuration from device tree */ 69 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags); 70 #endif 71 72 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) 73 /* Get the UART address from its instance number */ 74 uintptr_t get_uart_address(uint32_t instance_nb); 75 #endif 76 77 /* Setup the UART console */ 78 int stm32mp_uart_console_setup(void); 79 80 bool stm32mp_is_wakeup_from_standby(void); 81 82 /* 83 * Platform util functions for the GPIO driver 84 * @bank: Target GPIO bank ID as per DT bindings 85 * 86 * Platform shall implement these functions to provide to stm32_gpio 87 * driver the resource reference for a target GPIO bank. That are 88 * memory mapped interface base address, interface offset (see below) 89 * and clock identifier. 90 * 91 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 92 * check DT configuration matches platform implementation of the banks 93 * description. 94 */ 95 uintptr_t stm32_get_gpio_bank_base(unsigned int bank); 96 unsigned long stm32_get_gpio_bank_clock(unsigned int bank); 97 uint32_t stm32_get_gpio_bank_offset(unsigned int bank); 98 bool stm32_gpio_is_secure_at_reset(unsigned int bank); 99 100 /* Return node offset for target GPIO bank ID @bank or a FDT error code */ 101 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank); 102 103 /* Get the chip revision */ 104 uint32_t stm32mp_get_chip_version(void); 105 /* Get the chip device ID */ 106 uint32_t stm32mp_get_chip_dev_id(void); 107 108 /* Get SOC name */ 109 #define STM32_SOC_NAME_SIZE 20 110 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]); 111 112 /* Print CPU information */ 113 void stm32mp_print_cpuinfo(void); 114 115 /* Print board information */ 116 void stm32mp_print_boardinfo(void); 117 118 /* Initialise the IO layer and register platform IO devices */ 119 void stm32mp_io_setup(void); 120 121 /* Functions to map DDR in MMU with non-cacheable attribute, and unmap it */ 122 int stm32mp_map_ddr_non_cacheable(void); 123 int stm32mp_unmap_ddr(void); 124 125 /* Functions to map RETRAM, and unmap it */ 126 int stm32mp_map_retram(void); 127 int stm32mp_unmap_retram(void); 128 129 /* Function to save boot info */ 130 void stm32_save_boot_info(boot_api_context_t *boot_context); 131 /* Function to get boot peripheral info */ 132 void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance); 133 /* Function to get BOOT_MODE backup register address */ 134 uintptr_t stm32_get_bkpr_boot_mode_addr(void); 135 136 /* Display board information from the value found in OTP fuse */ 137 void stm32_display_board_info(uint32_t board_id); 138 139 #if PSA_FWU_SUPPORT 140 uintptr_t stm32_get_bkpr_fwu_info_addr(void); 141 void stm32_fwu_set_boot_idx(void); 142 uint32_t stm32_get_and_dec_fwu_trial_boot_cnt(void); 143 void stm32_set_max_fwu_trial_boot_cnt(void); 144 void stm32_clear_fwu_trial_boot_cnt(void); 145 #endif /* PSA_FWU_SUPPORT */ 146 147 #endif /* STM32MP_COMMON_H */ 148