1 /* SPDX-License-Identifier: Apache-2.0 */
2 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /* See the file LICENSE for further information */
4
5 #ifndef _SIFIVE_UX00DDR_H
6 #define _SIFIVE_UX00DDR_H
7
8 #ifndef __ASSEMBLER__
9
10 #include <stdint.h>
11 #include <stddef.h>
12
13 #define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
14
15 #define DRAM_CLASS_OFFSET 8
16 #define DRAM_CLASS_DDR4 0xA
17 #define OPTIMAL_RMODW_EN_OFFSET 0
18 #define DISABLE_RD_INTERLEAVE_OFFSET 16
19 #define OUT_OF_RANGE_OFFSET 1
20 #define MULTIPLE_OUT_OF_RANGE_OFFSET 2
21 #define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7
22 #define MC_INIT_COMPLETE_OFFSET 8
23 #define LEVELING_OPERATION_COMPLETED_OFFSET 22
24 #define DFI_PHY_WRLELV_MODE_OFFSET 24
25 #define DFI_PHY_RDLVL_MODE_OFFSET 24
26 #define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0
27 #define VREF_EN_OFFSET 24
28 #define PORT_ADDR_PROTECTION_EN_OFFSET 0
29 #define AXI0_ADDRESS_RANGE_ENABLE 8
30 #define AXI0_RANGE_PROT_BITS_0_OFFSET 24
31 #define RDLVL_EN_OFFSET 16
32 #define RDLVL_GATE_EN_OFFSET 24
33 #define WRLVL_EN_OFFSET 0
34
35 #define PHY_RX_CAL_DQ0_0_OFFSET 0
36 #define PHY_RX_CAL_DQ1_0_OFFSET 16
37
phy_reset(volatile uint32_t * ddrphyreg,const uint32_t * physettings)38 static inline void phy_reset(volatile uint32_t *ddrphyreg, const uint32_t *physettings) {
39 unsigned int i;
40 for (i=1152;i<=1214;i++) {
41 uint32_t physet = physettings[i];
42 /*if (physet!=0)*/ ddrphyreg[i] = physet;
43 }
44 for (i=0;i<=1151;i++) {
45 uint32_t physet = physettings[i];
46 /*if (physet!=0)*/ ddrphyreg[i] = physet;
47 }
48 }
49
ux00ddr_writeregmap(size_t ahbregaddr,const uint32_t * ctlsettings,const uint32_t * physettings)50 static inline void ux00ddr_writeregmap(size_t ahbregaddr, const uint32_t *ctlsettings, const uint32_t *physettings) {
51 volatile uint32_t *ddrctlreg = (volatile uint32_t *)ahbregaddr;
52 volatile uint32_t *ddrphyreg = ((volatile uint32_t *)ahbregaddr) + (0x2000 / sizeof(uint32_t));
53
54 unsigned int i;
55 for (i=0;i<=264;i++) {
56 uint32_t ctlset = ctlsettings[i];
57 /*if (ctlset!=0)*/ ddrctlreg[i] = ctlset;
58 }
59
60 phy_reset(ddrphyreg, physettings);
61 }
62
ux00ddr_start(size_t ahbregaddr,size_t filteraddr,size_t ddrend)63 static inline void ux00ddr_start(size_t ahbregaddr, size_t filteraddr, size_t ddrend) {
64 // START register at ddrctl register base offset 0
65 uint32_t regdata = _REG32(0<<2, ahbregaddr);
66 regdata |= 0x1;
67 _REG32(0<<2, ahbregaddr) = regdata;
68 // WAIT for initialization complete : bit 8 of INT_STATUS (DENALI_CTL_132) 0x210
69 while ((_REG32(132<<2, ahbregaddr) & (1<<MC_INIT_COMPLETE_OFFSET)) == 0) {}
70
71 // Disable the BusBlocker in front of the controller AXI slave ports
72 volatile uint64_t *filterreg = (volatile uint64_t *)filteraddr;
73 filterreg[0] = 0x0f00000000000000UL | (ddrend >> 2);
74 // ^^ RWX + TOR
75 }
76
ux00ddr_mask_mc_init_complete_interrupt(size_t ahbregaddr)77 static inline void ux00ddr_mask_mc_init_complete_interrupt(size_t ahbregaddr) {
78 // Mask off Bit 8 of Interrupt Status
79 // Bit [8] The MC initialization has been completed
80 _REG32(136<<2, ahbregaddr) |= (1<<MC_INIT_COMPLETE_OFFSET);
81 }
82
ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr)83 static inline void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr) {
84 // Mask off Bit 8, Bit 2 and Bit 1 of Interrupt Status
85 // Bit [2] Multiple accesses outside the defined PHYSICAL memory space have occurred
86 // Bit [1] A memory access outside the defined PHYSICAL memory space has occurred
87 _REG32(136<<2, ahbregaddr) |= ((1<<OUT_OF_RANGE_OFFSET) | (1<<MULTIPLE_OUT_OF_RANGE_OFFSET));
88 }
89
ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr)90 static inline void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr) {
91 // Mask off Bit 7 of Interrupt Status
92 // Bit [7] An error occurred on the port command channel
93 _REG32(136<<2, ahbregaddr) |= (1<<PORT_COMMAND_CHANNEL_ERROR_OFFSET);
94 }
95
ux00ddr_mask_leveling_completed_interrupt(size_t ahbregaddr)96 static inline void ux00ddr_mask_leveling_completed_interrupt(size_t ahbregaddr) {
97 // Mask off Bit 22 of Interrupt Status
98 // Bit [22] The leveling operation has completed
99 _REG32(136<<2, ahbregaddr) |= (1<<LEVELING_OPERATION_COMPLETED_OFFSET);
100 }
101
ux00ddr_setuprangeprotection(size_t ahbregaddr,size_t end_addr)102 static inline void ux00ddr_setuprangeprotection(size_t ahbregaddr, size_t end_addr) {
103 _REG32(209<<2, ahbregaddr) = 0x0;
104 size_t end_addr_16Kblocks = ((end_addr >> 14) & 0x7FFFFF)-1;
105 _REG32(210<<2, ahbregaddr) = ((uint32_t)end_addr_16Kblocks);
106 _REG32(212<<2, ahbregaddr) = 0x0;
107 _REG32(214<<2, ahbregaddr) = 0x0;
108 _REG32(216<<2, ahbregaddr) = 0x0;
109 _REG32(224<<2, ahbregaddr) |= (0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET);
110 _REG32(225<<2, ahbregaddr) = 0xFFFFFFFF;
111 _REG32(208<<2, ahbregaddr) |= (1 << AXI0_ADDRESS_RANGE_ENABLE);
112 _REG32(208<<2, ahbregaddr) |= (1 << PORT_ADDR_PROTECTION_EN_OFFSET);
113 }
114
ux00ddr_disableaxireadinterleave(size_t ahbregaddr)115 static inline void ux00ddr_disableaxireadinterleave(size_t ahbregaddr) {
116 _REG32(120<<2, ahbregaddr) |= (1<<DISABLE_RD_INTERLEAVE_OFFSET);
117 }
118
ux00ddr_disableoptimalrmodw(size_t ahbregaddr)119 static inline void ux00ddr_disableoptimalrmodw(size_t ahbregaddr) {
120 _REG32(21<<2, ahbregaddr) &= (~(1<<OPTIMAL_RMODW_EN_OFFSET));
121 }
122
ux00ddr_enablewriteleveling(size_t ahbregaddr)123 static inline void ux00ddr_enablewriteleveling(size_t ahbregaddr) {
124 _REG32(170<<2, ahbregaddr) |= ((1<<WRLVL_EN_OFFSET) | (1<<DFI_PHY_WRLELV_MODE_OFFSET));
125 }
126
ux00ddr_enablereadleveling(size_t ahbregaddr)127 static inline void ux00ddr_enablereadleveling(size_t ahbregaddr) {
128 _REG32(181<<2, ahbregaddr) |= (1<<DFI_PHY_RDLVL_MODE_OFFSET);
129 _REG32(260<<2, ahbregaddr) |= (1<<RDLVL_EN_OFFSET);
130 }
131
ux00ddr_enablereadlevelinggate(size_t ahbregaddr)132 static inline void ux00ddr_enablereadlevelinggate(size_t ahbregaddr) {
133 _REG32(260<<2, ahbregaddr) |= (1<<RDLVL_GATE_EN_OFFSET);
134 _REG32(182<<2, ahbregaddr) |= (1<<DFI_PHY_RDLVL_GATE_MODE_OFFSET);
135 }
136
ux00ddr_enablevreftraining(size_t ahbregaddr)137 static inline void ux00ddr_enablevreftraining(size_t ahbregaddr) {
138 _REG32(184<<2, ahbregaddr) |= (1<<VREF_EN_OFFSET);
139 }
140
ux00ddr_getdramclass(size_t ahbregaddr)141 static inline uint32_t ux00ddr_getdramclass(size_t ahbregaddr) {
142 return ((_REG32(0, ahbregaddr) >> DRAM_CLASS_OFFSET) & 0xF);
143 }
144
ux00ddr_phy_fixup(size_t ahbregaddr)145 static inline uint64_t ux00ddr_phy_fixup(size_t ahbregaddr) {
146 // return bitmask of failed lanes
147
148 size_t ddrphyreg = ahbregaddr + 0x2000;
149
150 // uint64_t fails=0;
151 uint32_t slicebase = 0;
152 // uint32_t dq = 0;
153
154 // check errata condition
155 for (uint32_t slice = 0; slice < 8; slice++) {
156 uint32_t regbase = slicebase + 34;
157 for (uint32_t reg = 0 ; reg < 4; reg++) {
158 uint32_t updownreg = _REG32((regbase+reg)<<2, ddrphyreg);
159 for (uint32_t bit = 0; bit < 2; bit++) {
160 uint32_t phy_rx_cal_dqn_0_offset;
161
162 if (bit==0) {
163 phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ0_0_OFFSET;
164 }else{
165 phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ1_0_OFFSET;
166 }
167
168 uint32_t down = (updownreg >> phy_rx_cal_dqn_0_offset) & 0x3F;
169 uint32_t up = (updownreg >> (phy_rx_cal_dqn_0_offset+6)) & 0x3F;
170
171 uint8_t failc0 = ((down == 0) && (up == 0x3F));
172 uint8_t failc1 = ((up == 0) && (down == 0x3F));
173
174 // print error message on failure
175 if (failc0 || failc1) {
176 //if (fails==0) uart_puts((void*) UART0_CTRL_ADDR, "DDR error in fixing up \n");
177 //fails |= (1<<dq);
178 /* char slicelsc = '0'; */
179 /* char slicemsc = '0'; */
180 /* slicelsc += (dq % 10); */
181 /* slicemsc += (dq / 10); */
182 //uart_puts((void*) UART0_CTRL_ADDR, "S ");
183 //uart_puts((void*) UART0_CTRL_ADDR, &slicemsc);
184 //uart_puts((void*) UART0_CTRL_ADDR, &slicelsc);
185 //if (failc0) uart_puts((void*) UART0_CTRL_ADDR, "U");
186 //else uart_puts((void*) UART0_CTRL_ADDR, "D");
187 //uart_puts((void*) UART0_CTRL_ADDR, "\n");
188 }
189 //dq++;
190 }
191 }
192 slicebase+=128;
193 }
194 return (0);
195 }
196
197 #endif
198
199 #endif
200